TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 D D D D D D D D D N OR D PACKAGE (TOP VIEW) Four 8-Bit Voltage Output DACs 5-V Single-Supply Operation Serial Interface High-Impedance Reference Inputs Programmable 1 or 2 Times Output Range Simultaneous Update Facility Internal Power-On Reset Low-Power Consumption Half-Buffered Output GND REFA REFB REFC REFD DATA CLK 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD LDAC DACA DACB DACC DACD LOAD applications D D D D D D Programmable Voltage Sources Digitally Controlled Amplifiers/Attenuators Mobile Communications Automatic Test Equipment Process Monitoring and Control Signal Synthesis description The TLC5620C and TLC5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two times the reference voltages and GND, and the DACs are monotonic. The device is simple to use, running from a single supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLC5620C and TLC5620I are over a simple three-wire serial bus that is CMOS compatible and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word comprises eight bits of data, two DAC-select bits, and a range bit, the latter allowing selection between the times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital inputs feature Schmitt triggers for high noise immunity. The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical applications. The TLC5620C is characterized for operation from 0°C to 70°C. The TLC5620I is characterized for operation from – 40°C to 85°C. The TLC5620C and TLC5620I do not require external trimming. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) PLASTIC DIP (N) 0°C to 70°C TLC5620CD TLC5620CN – 40°C to 85°C TLC5620ID TLC5620IN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 functional block diagram REFA 2 + – DAC 8 REFB REFC REFD 3 4 Latch Latch 8 8 Latch Latch 8 8 Latch Latch 8 Latch 8 + – DAC + – DAC ×2 + – 12 ×2 + – 11 ×2 + – 10 ×2 + – 9 DACB DACC 5 + – DAC 8 CLK 7 6 DATA LOAD 8 Latch Serial Interface 13 LDAC Power-On Reset Terminal Functions TERMINAL I/O DESCRIPTION 7 I Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock applied to the CLK terminal. DACA 12 O DAC A analog output DACB 11 O DAC B analog output DACC 10 O DAC C analog output DACD 9 O DAC D analog output DATA 6 I Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially. Each data bit is clocked into the register on the falling edge of the clock signal. GND 1 I Ground return and reference terminal LDAC 13 I Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is taken from high to low. LOAD 8 I Serial Interface load control. When LDAC is low, the falling edge of the LOAD signal latches the digital data into the output latch and immediately produces the analog voltage at the DAC output terminal. REFA 2 I Reference voltage input to DAC A. This voltage defines the output analog range. REFB 3 I Reference voltage input to DAC B. This voltage defines the output analog range. REFC 4 I Reference voltage input to DAC C. This voltage defines the output analog range. 5 I Reference voltage input to DAC D. This voltage defines the output analog range. 14 I Positive supply voltage NAME CLK REFD VDD 2 DACA NO. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DACD TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 detailed description The TLC5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance load to the reference source. Each DAC output is buffered by a configurable-gain output amplifier that can be programmed to times 1 or times 2 gain. On power up, the DACs are reset to CODE 0. Each output voltage is given by: V (DACA|B|C|D) O + REF CODE 256 (1 ) RNG bit value) where CODE is in the range 0 to 255 and the range (RNG) bit is 0 or 1 within the serial control word. Table 1. Ideal Output Transfer D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 OUTPUT VOLTAGE GND 0 0 0 0 0 0 0 1 (1/256) × REF (1+RNG) • • • • • • • • • • • • • • • • • • 0 1 1 1 1 1 1 1 (127/256) × REF (1+RNG) 1 0 0 0 0 0 0 0 (128/256) × REF (1+RNG) • • • • • • • • • • • • • • • • • • 1 1 1 1 1 1 1 1 (255/256) × REF (1+RNG) data interface With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit (MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4. CLK tsu(DATA-CLK) tsu(LOAD-CLK) tv(DATA-CLK) DATA A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0 tsu(CLK-LOAD) tw(LOAD) LOAD DAC Update Figure 1. LOAD-Controlled Update (LDAC = Low) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A1 RNG A0 D7 D6 D5 D4 D3 D2 D1 D0 tsu(LOAD-LDAC) LOAD tw(LDAC) LDAC DAC Update Figure 2. LDAC-Controlled Update CLK Low CLK ÎÎÎÎÎÎ DATA A1 A0 RNG ÎÎÎ D7 D6 D5 D4 D3 D2 D1 D0 ÎÎÎ LOAD LDAC Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low) CLK Low CLK ÎÎÎÎÎÎÎ DATA A1 A0 ÎÎÎÎ RNG D7 D6 D5 D4 D3 D2 D1 D0 ÎÎÎÎ LOAD LDAC Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output range. When RNG = low, the output range is between the applied reference voltage and GND, and when RNG = high, the range is between twice the applied reference voltage and GND. Table 2. Serial Input Decode 4 A1 A0 DAC UPDATED 0 0 DACA 0 1 DACB 1 0 DACC 1 1 DACD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 linearity, offset, and gain error using single-end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5. Output Voltage 0V DAC Code Negative Offset Figure 5. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below ground. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. The code is calculated from the maximum specification for the negative offset voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 equivalent inputs and outputs INPUT CIRCUIT OUTPUT CIRCUIT VDD VDD _ Input from Decoded DAC Register String Vref Input + ×1 Output Range × 2 Select To DAC Resistor String DAC Voltage Output 84 kΩ ISINK 60 µA Typical 84 kΩ GND GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD – GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to VDD + 0.3 V Reference input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLC5620C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC5620I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN Supply voltage, VDD NOM 4.75 High-level input voltage, VIH MAX UNIT 5.25 V 0.8 VDD V Low-level input voltage, VIL 0.8 Reference voltage, Vref [A|B|C|D] VDD – 1.5 Analog full-scale output voltage, RL = 10 kΩ 3.5 V V V Load resistance, RL 10 kΩ Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2) 50 ns Valid time, data input valid after CLK↓, tv(DATA-CLK) (see Figures 1 and 2) 50 ns Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure 1) 50 ns Setup time, LOAD↑ to CLK↓, tsu(LOAD-CLK) (see Figure 1) 50 ns Pulse duration, LOAD, tw(LOAD) (see Figure 1) 250 ns Pulse duration, LDAC, tw(LDAC) (see Figure 2) 250 ns Setup time, LOAD↑ to LDAC↓, tsu(LOAD-LDAC) (see Figure 2) 0 CLK frequency Operating free-air free air temperature, temperature TA 6 TLC5620C TLC5620I POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 1 MHz 0 70 °C – 40 85 °C TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref = 2 V, × 1 gain output range (unless otherwise noted) PARAMETER IIH IIL High-level input current IO(sink) IO(source) Output sink current Ci TEST CONDITIONS Output source current 15 Linearity error (end point corrected) EZS Zero-scale error Vref = 2 V, Vref = 2 V, Differential-linearity error pF 2 mA ± 10 µA ±1 LSB × 2 gain (see Note 2) ± 0.9 LSB 30 mV × 2 gain (see Note 3) × 2 gain (see Note 5) Full-scale-error temperature coefficient Vref = 2 V, Vref = 2 V, Power-supply rejection ratio See Notes 7 and 8 Full-scale error µA Vref = 2 V × 2 gain (see Note 1) Vref = 2 V, Vref = 2 V, Zero-scale-error temperature coefficient µA ± 10 mA Reference input capacitance EL ED ± 10 2 15 VDD = 5 V VDD = 5 V, UNIT µA Input capacitance Reference input current MAX 20 Each DAC output Supply current PSRR TYP VI = VDD VI = 0 V Low-level input current IDD Iref EFS MIN 0 × 2 gain (see Note 4) µV/°C 10 ± 60 × 2 gain (see Note 6) mV ± 25 µV/°C 0.5 mV/V NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full-scale errors). 2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(Tmax) – ZSE(Tmin)]/Vref × 106/(Tmax – Tmin). 5. Full-scale error is the deviation from the ideal full-scale output (Vref – 1 LSB) with an output load of 10 kΩ. 6. Full-scale-error temperature coefficient is given by: FSETC = [FSE(Tmax) – FSE (Tmin)]/Vref × 106/(Tmax – Tmin). 7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage. 8. Full-scale-error rejection ratio (FSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage. operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref = 2 V, × 1 gain output range (unless otherwise noted) TEST CONDITIONS Output slew rate CL = 100 pF, RL = 10 kΩ Output settling time To ± 0.5 LSB, CL = 100 pF, Large-signal bandwidth Digital crosstalk MIN TYP MAX UNIT 1 V/µs 10 µs Measured at – 3 dB point 100 kHz CLK = 1-MHz square wave measured at DACA-DACD – 50 dB Reference feedthrough See Note 10 – 60 dB Channel-to-channel isolation See Note 11 – 60 dB Reference input bandwidth See Note 12 100 kHz RL = 10 kΩ, See Note 9 NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full scale voltage within +/– 0.5 LSB starting from an initial output voltage equal to zero. 10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at 10 kHz. 11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex with Vref input = 1 V dc + 1 Vpp at 10 kHz. 12. Reference bandwidth is the –3 dB bandwidth with an input at Vref = 1.25 V dc + 2 Vpp and with a full-scale digital-input code. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION TLC5620 DACA DACB • • • DACD 10 kΩ CL = 100 pF Figure 6. Slew, Settling Time, and Linearity Measurements TYPICAL CHARACTERISTICS NEGATIVE FALL AND SETTLING TIME POSITIVE RISE AND SETTLING TIME LDAC LDAC 3 VDD = 5 V TA = 25°C Code 00 to FF Hex 2 Range = × 2 Vref = 2 V VO – Output Voltage – V VO – Output Voltage – V 3 1 VDD = 5 V TA = 25°C Code FF to 00 Hex Range = × 2 Vref = 2 V 2 1 0 0 0 2 4 6 8 10 12 14 16 18 0 2 6 8 10 t – Time – µs t – Time – µs Figure 8 Figure 7 8 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 14 16 18 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 TYPICAL CHARACTERISTICS DAC OUTPUT VOLTAGE vs OUTPUT LOAD 5 4 4.8 3.5 VO – DAC Output Voltage – V VO – DAC Output Voltage – V DAC OUTPUT VOLTAGE vs OUTPUT LOAD 4.6 4.4 4.2 4 3.8 3.6 VDD = 5 V, Vref = 2.5 V, Range = 2x 3.4 3 2.5 2 1.5 1 VDD = 5 V, Vref = 3.5 V, Range = 1x 0.5 3.2 3 0 10 20 30 40 50 60 70 80 RL – Output Load – kΩ 0 90 100 0 10 20 30 40 Figure 9 80 90 100 SUPPLY CURRENT vs TEMPERATURE 1.2 8 VDD = 5 V TA = 25°C Vref = 2 V Range = × 2 Input Code = 255 7 6 1.15 I DD – Supply Current – mA I O(source) – Output Source Current – mA 70 60 Figure 10 OUTPUT SOURCE CURRENT vs OUTPUT VOLTAGE 5 4 3 2 1.1 1.05 Range = × 2 Input Code = 255 VDD = 5 V Vref 2 V 1 0.95 0.9 0.85 1 0 50 RL – Output Load – kΩ 0 1 2 3 4 5 0.8 – 50 0 50 VO – Output Voltage – V t – Temperature – °C Figure 11 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 9 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 TYPICAL CHARACTERISTICS RELATIVE GAIN vs FREQUENCY RELATIVE GAIN vs FREQUENCY 10 0 –2 0 –6 –8 – 10 – 12 – 14 – 20 – 30 – 18 – 50 – 60 1 10 VDD = 5 V TA = 25°C Vref = 2 Vdc + 0.5 Vpp Input Code = 255 – 40 VDD = 5 V TA = 25°C Vref = 1.25 Vdc + 2 Vpp Input Code = 255 – 16 – 20 – 10 G – Relative Gain – dB G – Relative Gain – dB –4 100 1000 1 10 100 f – Frequency – kHz f – Frequency – kHz Figure 13 Figure 14 APPLICATION INFORMATION _ TLC5620 DACA DACB • • • DACD R NOTE A: Resistor R w 10 kΩ + Figure 15. Output Buffering Scheme 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VO 1000 10000 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN PINS ** 0.050 (1,27) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.157 (4,00) 0.150 (3,81) 1 Gage Plane 7 A 0.010 (0,25) 0°– 8° 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) 4040047 / B 10/94 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Four center pins are connected to die mount pad. Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23.37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21.59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0°– 15° 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001) 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5620CD ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC5620CDR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC5620CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NA-NA-NA TLC5620ID ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC5620IDR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC5620IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NA-NA-NA Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated