bq2050H Low-Cost Lithium Ion Power Gauge™ IC Features General Description ➤ Accurate measurement of available capacity in Lithium Ion batteries The bq2050H Lithium Ion Power Gauge™ IC is intended for batterypack or in-system installation to maintain an accurate record of available battery capacity. The IC monitors a voltage drop across a sense resistor connected in series between the negative battery termina l a n d g r ou n d t o d e t e r m i n e charge and discharge activity of the battery. Compensations for battery temperature, self discharge, and rate of discharge are applied to the charge counter to provide available capacity information across a wide range of operating conditions. Battery capacity is automatically recalibrated, or “learned,” in the course of a discharge cycle from full to empty. ➤ Provides a low-cost battery management solution for pack integration - Complete circuit can fit in as little as 1 2 square inch of PCB - Low operating current (120µA typical) - Less than 100nA of data retention current ➤ High-speed (5kb) single-wire communication interface (HDQ bus) for critical battery parameters ➤ Monitors and controls charge FET in Li-Ion pack protection circuit ➤ Direct drive of remaining capacity LEDs ments are used to graphically indic a t e a v a ila b le c a p a c it y . T h e bq2050H also supports a simple single-line bidirectional serial link to an external processor (common ground). The 5kb HDQ bus interface reduces communications overhead in the external microcontroller. Internal registers include available capacity, temperature, scaled available energy, battery ID, battery status, and Li-Ion charge FET status. The external processor may also overwrite some of the bq2050H power gauge data registers. The bq2050H can operate from the batteries in the pack. The REF output and an external transistor allow a simple, inexpensive voltage regulator to supply power to the circuit from the cells. Nominal available capacity may be directly indicated using a fivesegment LED display. These seg- ➤ Measurements automatically compensated for rate and temperature ➤ 16-pin narrow SOIC Pin Connections Pin Names LCOM LCOM 1 16 VCC SEG1/PROG1 2 15 REF SEG2/PROG2 3 14 PSTAT SEG3/PROG3 4 13 HDQ SEG4/PROG4 5 12 RBI SEG5/PROG5 6 11 SB CFC 7 10 DISP VSS 8 9 SR 16-Pin Narrow SOIC PN2050H1.eps LED common output SEG1/PROG1 LED segment 1/ program 1 input SEG2/PROG2 LED segment 2/ program 2 input SEG3/PROG3 LED segment 3/ program 3 input SEG4/PROG4 LED segment 4/ program 4 input SEG5/PROG5 LED segment 5/ program 5 input CFC Charge FET control output SLUS150–MAY 1999 D 1 VSS System ground SR Sense resistor input DISP Display control input SB Battery sense input RBI Register backup input HDQ Serial communications input/output PSTAT Protector status input REF Voltage reference output VCC Supply voltage bq2050H Pin Descriptions DISP LCOM DISP high disables the LED display. DISP tied to VCC allows PROGX to connect directly to VCC or VSS instead of through a pull-up or pull-down resistor. DISP floating allows the LED display to be active during charge. DISP low activates the display. See Table 1. This open-drain output switches V CC to source current for the LEDs. The switch is off during initialization to allow reading of the soft pull-up or pull-down program resistors. LCOM is also high impedance when the display is off. SEG1– SEG5 LED display segment outputs (dual function with PROG1–PROG5) SB Programmed full count selection inputs (dual function with SEG1–SEG2) RBI These three-level input pins define the programmed full count (PFC) thresholds described in Table 2. PROG3– PROG4 Power gauge scale selection inputs (dual function with SEG3–SEG4) HDQ Self-discharge rate selection (dual function with SEG5) PSTAT REF This pin can be used as an additional control to the charge FET of the Li-Ion pack protection circuitry. Ground SR Sense resistor input Protector status input This input provides overvoltage status from the Li-Ion protector circuit. It should connect to VSS when not used. Charge FET control output VSS Serial communication input/output This is the open-drain bidirectional communications port. This three-level input pin defines the self-discharge and battery compensation factors as shown in Table 1. CFC Register backup input This pin is used to provide backup potential to the bq2050H registers during periods when VCC ≤ 3V. A storage capacitor or a battery can be connected to RBI. These three-level input pins define the scale factor described in Table 2. PROG5 Secondary battery input This input monitors the battery cell voltage potential through a high-impedance resistive divider network for end-of-discharge voltage (EDV) thresholds and battery-removed detection. Each output may activate an LED to sink the current sourced from LCOM. PROG1– PROG2 Display control input LED common output Voltage reference output for regulator REF provides a voltage reference output for an optional micro-regulator. VCC The voltage drop (VSR) across the sense resistor RS is monitored and integrated over time to interpret charge and discharge activity. The SR input is tied between the negative terminal of the battery and the sense resistor. VSR < VSS indicates discharge, and VSR > VSS indicates charge. The effective voltage drop, VSRO, as seen by the bq2050H is VSR + VOS . 2 Supply voltage input bq2050H capacity. The scaled available energy measurement is corrected for environmental and operating conditions. Functional Description General Operation Figure 1 shows a typical battery pack application of the bq2050H using the LED display capability as a chargestate indicator. The bq2050H is configured to display capacity in relative display mode. The relative display mode uses the last measured discharge capacity of the battery as the battery “full” reference. A push-button display feature is available for momentarily enabling the LED display. The bq2050H determines battery capacity by monitoring the amount of current input to or removed from a rechargeable battery. The bq2050H measures discharge and charge currents, measures battery voltage, estimates self-discharge, monitors the battery for low battery-voltage thresholds, and compensates for temperature and discharge rate. Current measurement is measured by monitoring the voltage across a small-value series sense resistor between the negative battery terminal and ground. Scaled available energy is estimated using the remaining average battery voltage during the discharge cycle and the remaining nominal available The bq2050H monitors the charge and discharge currents as a voltage across a sense resistor. (See RS in Figure 1.) A filter between the negative battery terminal and the SR pin is required. R1 bq2050H Power Gauge IC Q1 ZVNL110A REF C1 LCOM SEG1/PROG1 RB1 VCC SB VCC SEG2/PROG2 C2 RB2 SEG3/PROG3 DISP SEG4/PROG4 SR 100K 0.1µF SEG5/PROG5 CFC VSS PSTAT HDQ RS RBI See note 4 Notes: 1. Charger Indicates optional. Load 2. Programming resistors and ESD-protection diodes are not shown. 3. RC on SR is required. 4. A series diode is required on RBI if the bottom series cell is used as the backup source. If the cell is used, the backup capacitor is not required, and the anode is connected to the positive terminal of the cell. FG2050H1.eps Figure 1. Battery Pack Application Diagram—LED Display 3 bq2050H Voltage Thresholds TMP (hex) Temperature Range 0x < -30°C 1x -30°C to -20°C 2x -20°C to -10°C where N is the number of cells, RB1 is connected to the positive battery terminal, and RB2 is connected to the negative battery terminal. The single-cell battery voltage is monitored for the end-of-discharge voltage (EDV) thresholds. The EDV threshold levels are used to determine when the battery has reached an “empty” state. 3x -10°C to 0°C 4x 0°C to 10°C 5x 10°C to 20°C The EDV thresholds for the bq2050H are programmable with the default values fixed at: 6x 20°C to 30°C EDV1 (first) = 0.76V 7x 30°C to 40°C EDVF (final) = EDV1-0.025V = 0.735V 8x 40°C to 50°C 9x 50°C to 60°C Ax 60°C to 70°C Bx 70°C to 80°C Cx > 80°C In conjunction with monitoring VSR for charge/discharge currents, the bq2050H monitors the battery potential through the SB pin. The voltage is determined through a resistor-divider network per the following equation: RB1 = 4N − 1 RB2 If VSB is below either of the two EDV thresholds, the associated flag is latched and remains latched, independent of VSB, until the next valid charge. The VSB value is also available over the serial port. During discharge and charge, the bq2050H monitors V SR for various thresholds used to compensate the charge counter. EDV monitoring is disabled if the discharge rate is greater than 2C (OVLD Flag = 1) and resumes 1 2 second after the rate falls below 2C. RBI Input Layout Considerations The RBI input pin is intended to be used with a storage capacitor or external supply to provide backup potential to the internal bq2050H registers when VCC drops below 3.0V. VCC is output on RBI when VCC is above 3.0V. If using an external supply (such as the bottom series cell) as the backup source, an external diode is required for isolation. The bq2050H measures the voltage differential between the SR and VSS pins. VOS (the offset voltage at the SR pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally: Reset The bq2050H can be reset by removing VCC and grounding the RBI pin for 15 seconds or by commands over the serial port. The serial port reset command sequence requires writing 00h to register PPFC (address = 1Eh) and then writing 00h to register LMD (address = 05h). ■ The capacitors (C1 and C2) should be placed as close as possible to the VCC and SB pins, respectively, and their paths to VSS should be as short as possible. A high-quality ceramic capacitor of 0.1µF is recommended for VCC. ■ The sense-resistor capacitor should be placed as close as possible to the SR pin. ■ The sense resistor (RS) should be as close as possible to the bq2050H. Temperature The bq2050H internally determines the temperature in 10°C steps centered from approximately -35°C to +85°C. The temperature steps are used to adapt charge and discharge rate compensations, self-discharge counting, and available charge display translation. The temperature range is available over the serial port in 10°C increments as shown in the following table: 4 bq2050H The battery's initial capacity equals the Programmed Full Count (PFC) shown in Table 2. Until LMD is updated, NAC counts up to but not beyond this threshold during subsequent charges. This approach allows the gas gauge to be charger-independent and compatible with any type of charge regime. Gas Gauge Operation The operational overview diagram in Figure 2 illustrates the operation of the bq2050H. The bq2050H accumulates a measure of charge and discharge currents, as well as an estimation of self-discharge. The accumulated charge and discharge currents are adjusted for temperature and rate to provide the indication of compensated available capacity to the host system or user. 1. LMD is the last measured discharge capacity of the battery. On initialization (application of VCC or battery replacement), LMD = PFC. During subsequent discharges, the LMD is updated with the latest measured capacity in the Discharge Count Register representing a discharge from full to below EDV1. A qualified discharge is necessary for a capacity transfer from the DCR to the LMD register. The LMD also serves as the 100% reference threshold used by the relative display mode. The main counter, Nominal Available Capacity (NAC), represents the available battery capacity at any given time. Battery charging increments the NAC register, while battery discharging and self-discharge decrement the NAC register and increment the DCR (Discharge Count Register). The Discharge Count Register is used to update the Last Measured Discharge (LMD) register only if a complete battery discharge from full to empty occurs without any partial battery charges. Therefore, the bq2050H adapts its capacity determination based on the actual conditions of discharge. Inputs Last Measured Discharge (LMD) or learned battery capacity: Charge Current Discharge Current Rate and Temperature Temperature Compensation Compensation Temperature Compensation + Main Counters and Capacity Reference (LMD) + - Nominal Available Charge (NAC) Last Measured < Discharged (LMD) Rate and Temperature Compensation Outputs Self-Discharge Timer Compensated Available Charge LED Display, etc. Discharge Count Qualified Register (DCR) Transfer Temperature Step, Other Data Serial Port Figure 2. Operational Overview 5 + FG2050H2.eps bq2050H 2. Programmed Full Count (PFC) or initial battery capacity: Example: Selecting a PFC Value Given: The initial LMD and gas gauge rate values are programmed by using PROG1–PROG4. The bq2050H is configured for a given application by selecting a PFC value from Table 2. The correct PFC may be determined by multiplying the rated battery capacity in mAh by the sense resistor value: Sense resistor = 0.05Ω Number of cells = 2 Capacity = 1000mAh, Li-Ion battery, coke-anode Current range = 50mA to 1A Relative display mode Self-discharge = NAC 512 per day @ 25°C Voltage drop over sense resistor = 2.5mV to 50mV Nominal discharge voltage = 3.6V Battery capacity (mAh) * sense resistor (Ω) = PFC (mVh) Therefore: Selecting a PFC slightly less than the rated capacity provides a conservative capacity reference until the bq2050H “learns” a new capacity reference. 1000mAh * 0.05Ω = 50mVh Table 1. Self-Discharge and Capacity Compensation Pin Connection PROG5 Compensation/Self-Discharge (See Tables 3 and 4) DISP Display State H Coke anode/disabled LEDs disabled Z Coke anode/ L Graphite anode/ NAC LEDs on when charging 512 NAC LEDs on for 4 s 512 Table 2. bq2050H Programmed Full Count mVh, VSR Gain Selections PROGx 1 2 Programmed Full Count (PFC) PROG4 = L PROG3 = H PROG4 = Z or H PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L Units - - - SCALE = 1/80 H H 49152 614 307 154 76.8 38.4 19.2 mVh H Z 45056 563 282 141 70.4 35.2 17.6 mVh H L 40960 512 256 128 64.0 32.0 16.0 mVh Z H 36864 461 230 115 57.6 28.8 14.4 mVh Z Z 33792 422 211 106 53.0 26.4 13.2 mVh Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh L H 27648 346 173 86.4 43.2 21.6 10.8 mVh L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh L L 22528 282 141 70.4 35.2 17.6 8.8 mVh 90 45 22.5 11.25 5.6 2.8 mV VSR equivalent to 2 counts/s (nom.) SCALE = 1/160 SCALE = 1/320 SCALE = 1/640 SCALE = 1/1280 SCALE = 1/2560 mVh/ count 6 bq2050H E(mWh) = (SAEH ∗ 256 + SAEL) ∗ Select: 1.2 ∗ SCALE ∗ (RB1 + RB2) RS ∗ RB2 PFC = 30720 counts or 48mVh PROG1 = float PROG2 = low PROG3 = high PROG4 = float PROG5 = float where RB1, RB2, and RS are resistor values in ohms, as shown in Figure 1. SCALE is the selected scale from Table 2. 6. Compensated Available Capacity (CACT) The initial full battery capacity is 48mVh (960mAh) until the bq2050H “learns” a new capacity with a qualified discharge from full to EDV1. 3. CACT counts similarly to NAC, but contains the available capacity compensated for discharge rate and temperature. Nominal Available Capacity (NAC): Charge Counting NAC counts up during charge to a maximum value of LMD and down during discharge and self-discharge to 0. NAC is reset to 0 on initialization and on the first valid charge following discharge to EDV1. To prevent overstatement of charge during periods of overcharge, NAC stops incrementing when NAC = LMD. 4. Charge activity is detected based on a positive voltage on the SR input. If charge activity is detected, the bq2050H increments NAC at a rate proportional to VSR and, if enabled, activates an LED display. The bq2050H counts charge activity when the voltage at the SR input (V SRO ) exceeds the minimum charge threshold (VSRQ). A valid charge is detected when NAC has been updated twice without discharging or reaching the digital magnitude filter time-out. Once a valid charge is detected, charge counting continues until VSR, including offset, falls below VSRQ. Discharge Count Register (DCR): The DCR counts up during discharge independent of NAC and could continue increasing after NAC has decremented to 0. Prior to NAC = 0 (empty battery), both discharge and self-discharge increment the DCR. After NAC = 0, only discharge increments the DCR. The DCR resets to 0 when NAC = LMD. The DCR does not roll over but stops counting when it reaches FFh. Discharge Counting Discharge activity is detected based on a negative voltage on the SR input. All discharge counts where VSRO is less than the minimum discharge threshold (VSRD) cause the NAC register to decrement and the DCR to increment. The DCR value becomes the new LMD value on the first charge after a valid discharge to VEDV1 if all the following conditions are met: ■ ■ ■ ■ Self-Discharge Counting No valid charge initiations (charges greater than 2 NAC updates where VSRO > VSRQ) occurred during the period between NAC = LMD and EDV1. The bq2050H continuously decrements NAC and increments DCR for self-discharge based on time and temperature. The self-discharge is less than 6% of NAC. The temperature is ≥ 0°C when the EDV1 level is reached during discharge. Charge/Discharge Current The bq2050H current-scale registers, VSRH and VSRL, can be used to determine the battery charge or discharge current. See the Current Scale Register description for details. VDQ is set The valid discharge flag (VDQ) indicates whether the present discharge is valid for LMD update. If the DCR update value is less than 0.94 ∗ LMD, LMD will only be modified by 0.94 ∗ LMD. This prevents invalid DCR values from corrupting LMD. 5. Count Compensations Scaled Available Energy (SAE): Compensated Available Capacity SAE is useful in determining the available energy within the battery, and may provide a more useful capacity reference in battery chemistries with sloped voltage profiles during discharge. SAE may be converted to an mWh value using the following formula: Compensated Available Capacity compensation is based on the rate of discharge, temperature, and negative electrode type. Tables 3A and 3B outline the correction factor typically used for graphite-anode Li-Ion batteries, and Tables 4A and 4B outline the factors typically used for coke-anode Li-Ion batteries. The compensation factor is applied to NAC to derive the CACD and CACT values. 7 bq2050H Charge Compensation Table 3A. Graphite Anode Approximate Discharge Rate Available Capacity Reduction < 0.5C 0 ≥ 0.5C 0.05 ∗ LMD The bq2050H also monitors temperature during charge. If the temperature is <0°C, NAC will only increment up to 0.94 * LMD, inhibiting VDQ from being set. This keeps a “learn” cycle from occurring when the battery is charged at very low temperatures. If the temperature rises above 0°C, NAC will be allowed to count up to NAC = LMD. Self-Discharge Compensation Table 3B. Graphite Anode Temperature Available Capacity Reduction ≥ 10°C 0 The self-discharge compensation is programmed for a nominal rate of 1 512 ∗ NAC per day. This is the rate that NAC is reduced for a battery within the 20–30°C temperature range. This rate varies across 8 ranges from <10°C to >70°C, as shown in Table 5. 0°C to 10°C 0.05 ∗ LMD Table 5. Self-Discharge Compensation -20°C to 0°C 0.15 ∗ LMD ≤ -20°C 0.37 ∗ LMD Typical Rate Temperature Range Table 4A. Coke Anode PROG5 = Z or L < 10°C NAC 10–20°C NAC 2048 1024 Approximate Discharge Rate Available Capacity Reduction 20–30°C NAC 30–40°C NAC <0.5C 0 40–50°C NAC ≥ 0.5C 0.10 ∗ LMD 50–60°C NAC 60–70°C NAC > 70°C NAC Table 4B. Coke Anode 512 256 128 64 32 16 Self-discharge may be disabled by connecting PROG5 = H. Temperature Available Capacity Reduction ≥ 10°C 0 0°C to 10°C 0.10 ∗ LMD -20°C to 0°C 0.30 ∗ LMD ≤ -20°C 0.60 ∗ LMD Digital Magnitude Filter The bq2050H has a digital filter to eliminate charge and discharge counting below a set threshold. The minimum charge (VSRQ) and discharge (VSRD) threshold for the bq2050H is 250µV. Pack Protection Supervision The bq2050H can monitor the charge FET in a Li-Ion pack protector circuit as shown in Figure 3. If the battery voltage is too high or the temperature is out of the 0—60°C range, the bq2050H disables the charge FET with the CFC output, which turns off the charge to the pack. The CACD value is the available charge compensated for the rate of discharge. At high discharge rates, CACD is reduced. The reduction is maintained until a valid charge is detected. The CACT value is the available charge compensated for the rate of discharge and temperature. The CACT value is used to drive the LED display. The PSTAT input is used to monitor the protector state. If PSTAT is above 2.5V, bit 5 of FLGS1 is set to 1. If PSTAT is below 0.5V, bit 5 of FLGS1 is cleared to zero. Using this input, the system can monitor the state of the charge con- 8 bq2050H Table 6. bq2050H Current-Sensing Errors Symbol Parameter Typical Maximum Units Notes INL Integrated non-linearity error ±2 ±4 % Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V. INR Integrated nonrepeatability error ±1 ±2 % Measurement repeatability given similar operating conditions. trol FET signal and can quickly determine if the protector circuit is operating properly during charge. Register 15h, NMCV, is used to set the maximum battery voltage for the battery stack. If VSB > NMCV or the battery temperature is < 0°C or > 60°C, then CFC is driven low. A Capacity Inaccurate counter (CPI) is maintained and incremented each time a valid charge occurs (qualified by NAC; see the CPI register description). It is reset whenever LMD is updated from the DCR. The counter does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges. Error Summary Current-Sensing Error Capacity Inaccurate Table 6 shows the non-linearity and non-repeatability errors associated with the bq2050H current sensing. The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value includes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated (see the DCR description). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in actual battery capacity. Table 7 illustrates the current-sensing error as a function of VOS. A digital filter prevents charge and discharge counts to the NAC register when VSRO is between VSRQ and VSRD. Charger Discharge Control PSTAT RLOAD bq2050H CFC Charge Control SR VSS RS FG2050H3.eps Figure 3. bq2050H Pack Supervision 9 bq2050H should be held for a period, tDH;DV, to allow the host or bq2050H to sample the data bit. Table 7. VOS-Related Current Sense Error (Current = 1A) VOS (µV) 50 100 150 180 20 0.25 0.50 0.75 0.90 Sense Resistor 50 100 0.10 0.05 0.20 0.10 0.30 0.15 0.36 0.18 The final section is used to stop the transmission by returning the HDQ pin to a logic-high state by at least a period, tSSU;B, after the negative edge used to start communication. The final logic-high state should be until a period tCYCH;B, to allow time to ensure that the bit transmission was stopped properly. The timings for data and break communication are given in the serial communication timing specification and illustration sections. mΩ % % % % Communication with the bq2050H is always performed with the least-significant bit being transmitted first. Figure 5 shows an example of a communication sequence to read the bq2050H NACH register. Communicating With the bq2050H The bq2050H includes a simple single-pin (HDQ plus return) serial data interface. A host processor uses the interface to access various bq2050H registers. Battery characteristics may be easily monitored by adding a single contact to the battery pack. The open-drain HDQ pin on the bq2050H should be pulled up by the host system, or may be left floating if the serial interface is not used. bq2050H Command Code and Registers The bq2050H status registers are listed in Table 8 and described below. All registers are Read/Write in the bq2050H. Caution: When writing to bq2050H registers ensure that proper data is written. A write-verify read is recommended. The interface uses a command-based protocol, where the host processor sends a command byte to the bq2050H. The command directs the bq2050H to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte. (See Figure 4.) Command Code The bq2050H latches the command code when eight valid command bits have been received by the bq2050H. The command code contains two fields: The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 5K bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2050H may be sampled using the pulse-width capture timers available on some microcontrollers. ■ W/R bit ■ Command address The W/R bit of the command code is used to select whether the received command is for a read or a write function. The W/R values are: Command Code Bits If a communication error occurs (e.g., tCYCB > 250µs), the bq2050H should be sent a BREAK to reinitiate the serial interface. A BREAK is detected when the HDQ pin is driven to a logic-low state for a time, tB or greater. The HDQ pin should then be returned to its normal ready-high logic state for a time, tBR. The bq2050H is now ready to receive a command from the host processor. 7 6 5 4 3 2 1 0 W/R - - - - - - - Where W/R is: The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2050H taking the HDQ pin to a logic-low state for a period, tSTRH;B. The next section is the actual data transmission, where the data should be valid by a period, tDSU;B, after the negative edge used to start communication. The data 0 The bq2050H outputs the requested register contents specified by the address portion of command code. 1 The following eight bits should be written to the register specified by the address portion of command code. The lower seven-bit field of the command code contains the address portion of the register to be accessed. 10 bq2050H Send Host to bq-HDQ Send Host to bq-HDQ or Receive from bq-HDQ Data CDMR R/W MSB Bit7 Address LSB Bit0 Break tRR tRSPS Start-bit Address-Bit/ Data-Bit Stop-Bit TD201807.eps Figure 4. bq2050H Communication Example Written by Host to bq2050H CMDR = 03h LSB MSB Break 1 1 0 0 0 0 0 0 Received by Host to bq2050H NACH = 65h LSB MSB 1 01 0 011 0 HDQ tRSPS TD2050H2.eps Figure 5. Typical Communication With the bq2050H 11 bq2050H Table 8. bq2050H Command and Status Registers Symbol FLGS1 TMP NACH NACL BATID LMD FLGS2 PPD PPU CPI VSB VTS CACT CACD SAEH SAEL RCAC VSRH VSRL NMCV DCR PPFC INTSS RST HEXFF Notes: Register Name Loc. Read/ Control Field (hex) Write 7(MSB) 6 5 4 3 2 1 Primary status flags 01h R CHGS BRP PSTAT CI VDQ 1 EDV1 register Temperature register 02h R TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 Nominal available capac03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 ity high byte register Nominal available 17h R/W NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 capacity low byte register Battery identification 04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 register Last measured 05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 discharge register Secondary status flags 06h R RSVD DR2 DR1 DR0 ENINT VQ RSVD register Program pin pull-down 07h R RSVD RSVD RSVD PPD5 PPD4 PPD3 PPD2 register Program pin pull-up 08h R RSVD RSVD RSVD PPU5 PPU4 PPU3 PPU2 register Capacity 09h R/W CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 inaccurate count register Battery voltage 0bh R VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 register End-of-discharge thresh0ch R/W VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 old select register Temperature and Discharge Rate compensated 0dh R/W CACT7 CACT6 CACT5 CACT4 CACT3 CACT2 CACT1 available capacity Discharge Rate compensated available 0eh R/W CACD7 CACD6 CACD5 CACD4 CACD3 CACD2 CACD1 capacity Scaled available energy 0fh R SAEH7 SAEH6 SAEH5 SAEH4 SAEH3 SAEH2 SAEH1 high byte register Scaled available energy 10h R SAEL7 SAEL6 SAEL5 SAEL4 SAEL3 SAEL2 SAEL1 low byte register Relative CAC 11h R RCAC6 RCAC5 RCAC4 RCAC3 RCAC2 RCAC1 Current scale high 12h R VSRH7 VSRH6 VSRH5 VSRH4 VSRH3 VSRH2 VSRH1 Current scale low 13h R VSRL7 VSRL6 VSRL5 VSRL4 VSRL3 VSRL2 VSRL1 Maximum cell voltage 15h R/W NMCV7 NMCV6 NMCV5 NMCV4 NMCV3 NMCV2 NMCV1 Discharge register 18h R/W DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 Program pin data 1eh R/W RSVD RSVD RSVD RSVD RSVD RSVD RSVD VOS Interrupt 38h R RSVD RSVD RSVD RSVD DCHGI RSVD RSVD Reset register 39h R/W RST 0 0 0 0 0 0 Check register 3fh R/W 1 1 1 1 1 1 1 RSVD = reserved. All other registers not documented are reserved. 12 0(LSB) EDVF GG0 NACH0 NACL0 BATID0 LMD0 OVLD PPD1 PPU1 CPI0 VSB0 VTS0 CACT0 CACD0 SAEH0 SAEL0 RCAC0 VSRH0 VSRL0 NMCV0 DCR0 RSVD CHGI 0 1 bq2050H The PSTAT values are: Command Code Bits 7 - 6 5 4 AD6 AD5 3 AD4 2 AD3 1 AD2 FLGS1 Bits 0 AD1 AD0 (LSB) 7 6 5 4 3 2 1 0 - - PSTAT - - - - - Where PSTAT is: Primary Status Flags Register (FLGS1) The FLGS1 register (address = 01h) contains the primary bq2050H flags. 0 PSTAT input is low (PSTAT < 0.5V) 1 PSTAT input is high (PSTAT > 2.5V) The capacity inaccurate flag (CI) is used to warn the user that the battery has been charged a substantial number of times since LMD has been updated. The CI flag is asserted on the 64th charge after the last LMD update or when the bq2050H is reset. The flag is cleared after an LMD update. The charge status flag (CHGS) is asserted when a valid charge rate is detected. Charge rate is deemed valid when VSRO > VSRQ. A VSRO of less than VSRQ or discharge activity clears CHGS. The CHGS values are: The CI values are: FLGS1 Bits 7 6 5 4 3 2 1 0 CHGS - - - - - - - FLGS1 Bits 7 6 5 4 3 2 1 0 - - - CI - - - - Where CHGS is: 0 Either discharge activity detected or VSRO ≤ VSRQ 1 VSRO > VSRQ Where CI is: The battery replaced flag (BRP) is asserted whenever the bq2050H is reset either by application of VCC or by a serial port command. BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is detected after the EDV1 flag is asserted. BRP = 1 signifies that the device has been reset. 5 4 3 2 1 0 - BRP - - - - - - 1 After the 64th valid charge action with no LMD updates or the bq2050H is reset When NAC has been reduced by more than 6% because of self-discharge since VDQ was set. ■ A valid charge action sustained at VSRO > VSRQ for at least 2 NAC updates. ■ The EDV1 flag was set at a temperature below 0°C The VDQ values are: Where BRP is: 0 1 ■ FLGS1 Bits 6 When LMD is updated with a valid full discharge The valid discharge flag (VDQ) is asserted when the bq2050H is discharged from NAC=LMD. The flag remains set until either LMD is updated or one of three actions that can clear VDQ occurs: The BRP values are: 7 0 Battery is charged until NAC = LMD or discharged until the EDV1 flag is asserted FLGS1 Bits bq2050H is reset The protector status flag (PSTAT) provides information on the state of the overvoltage protector within the LiIon battery pack. The PSTAT flag is asserted whenever this input is high and is cleared when the input is low. 7 6 5 4 3 2 1 0 - - - - VDQ - - - Where VDQ is: 13 0 Self-discharge of 6% of NAC, valid charge action detected, EDV1 asserted with the temperature less than 0°C, or reset 1 On first discharge after NAC = LMD bq2050H The bq2050H calculates the gas gauge bits, GG3-GG0 as a function of CACT and LMD. The results of the calculation give available capacity in 1 16 increments from 0 to 15 16. The first end-of-discharge warning flag (EDV1) warns the user that the battery is almost empty. The first segment pin, SEG1, is modulated at a 4Hz rate if the display is enabled once EDV1 is asserted, which should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has been detected. The EDV1 threshold is externally controlled via the VTS register (see Voltage Threshold Register). TMP Gas Gauge Bits 7 6 5 4 3 2 1 0 - - - - GG3 GG2 GG1 GG0 The EDV1 values are: Table 9. Temperature Register FLGS1 Bits TMP3 TMP2 TMP1 TMP0 7 6 5 4 3 2 1 0 0 0 0 0 T < -30°C - - - - - - EDV1 - 0 0 0 1 -30°C < T < -20°C 0 0 1 0 -20°C < T < -10°C -10°C < T < 0°C Where EDV1 is: Temperature 0 0 1 1 0 Valid charge action detected, VSB ≥ VTS 0 1 0 0 0°C < T < 10°C 1 VSB < VTS providing that the discharge rate is < 2C 0 1 0 1 10°C < T < 20°C 0 1 1 0 20°C < T < 30°C The final end-of-discharge warning flag (EDVF) flag is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag is latched until a valid charge has been detected. The EDVF threshold is set 25mV below the EDV1 threshold. 0 1 1 1 30°C < T < 40°C 1 0 0 0 40°C < T < 50°C 1 0 0 1 50°C < T < 60°C 1 0 1 0 60°C < T < 70°C 1 0 1 1 70°C < T < 80°C 1 1 0 0 T > 80°C The EDVF values are: FLGS1 Bits 7 6 5 4 3 2 1 0 - - - - - - - EDVF Nominal Available Capacity Registers (NACH/NACL) The NACH high-byte register (address=03h) and the NACL low-byte register (address=17h) are the main gas gauging registers for the bq2050H. The NAC registers are incremented during charge actions and decremented during discharge and self-discharge actions. NACH and NACL are set to 0 during a bq2050H reset. Where EDVF is: 0 Valid charge action detected, VSB ≥ (VTS - 25mV) 1 VSB < (VTS -25mV) providing the discharge rate is < 2C Writing to the NAC registers affects the available charge counts and, therefore, affects the bq2050H gas gauge operation. Do not write the NAC registers to a value greater than LMD. Temperature Register (TMP) The TMP register (address=02h) contains the battery temperature. Battery Identification Register (BATID) The bq2050H contains an internal temperature sensor. The temperature is used to set charge and discharge efficiency factors as well as to adjust the self-discharge coefficient. The temperature register contents may be translated as shown in Table 9. The BATID register (address=04h) is available for use by the system to determine the type of battery pack. The BATID contents are retained as long as VRBI is greater than 2V. The contents of BATID have no effect on the operation of the bq2050H. There is no default setting for this register. TMP Temperature Bits 7 6 5 4 TMP3 TMP2 TMP1 TMP0 3 2 1 0 - - - - 14 bq2050H Where VQ is: Last Measured Discharge Register (LMD) LMD is the register (address=05h) that the bq2050H uses as a measured full reference. The bq2050H adjusts LMD based on the measured discharge capacity of the battery from full to empty. In this way the bq2050H updates the capacity of the battery. LMD is set to PFC during a bq2050H reset. If DCR < 0.94 LMD, then LMD is set to 0.94 ∗ LMD. Secondary Status Flags Register (FLGS2) Bit 7 and bit 1 of FLGS2 are reserved. Do not write to these bits. 2 - 1 - DR1 0 0 1 DR0 0 1 0 0 6 - 2 - 1 - 7 5 - FLGS2 Bits 4 3 - 2 VQ 1 - 0 OVLD 6 5 4 3 2 1 0 RSVD RSVD RSVD PPU5 PPU4 PPU3 PPU2 PPU1 0 RSVD RSVD RSVD PPD5 PPD4 PPD3 PPD2 PPD1 Capacity Inaccurate Count Register (CPI) The CPI register (address=09h) is used to indicate the number of times a battery has been charged without an LMD update. Because the capacity of a rechargeable battery varies with age and operating conditions, the bq2050H adapts to the changing capacity over time. A complete discharge from full (NAC=LMD) to empty (EDV1=1) is required to perform an LMD update assuming there have been no intervening valid charges, the temperature is greater than or equal to 0°C, and there has been no more than a 6% self-discharge reduction. The VQ values are: 6 - 1 - PPD/PPU Bits The valid charge flag (VQ), bit 2 of FLGS2, is used to indicate whether the bq2050H recognizes a valid charge condition. This bit is reset on the first discharge after NAC = LMD. 7 - 2 - The PPU register (address=08h) contains the rest of the programming pin information for the bq2050H. The segment drivers, SEG1–5, have a corresponding PPU register location, PPU1–5. A given location is set if a pull-up resistor has been detected on its corresponding segment driver. For example, if SEG3 and SEG5 have pull-up resistors, the contents of PPU are xxx10100. The enable interrupt flag (ENINT) is a test bit used to determine VSR activity sensed by the bq2050H. The state of this bit will vary and should be ignored by the system. 7 - FLGS2 Bits 4 3 - 5 - Program Pin Pull-Up Register (PPU) Discharge Rate DRATE < 0.5C 0.5C ≤ DRATE < 2C 2C < DRATE FLGS2 Bits 5 4 3 ENINT 6 - The PPD register (address=07h) contains some of the programming pin information for the bq2050H. The segment drivers, SEG1–5, have a corresponding PPD register location, PPD1–5. A given location is set if a pull-down resistor has been detected on its corresponding segment driver. For example, if SEG1 and SEG4 have pull-down resistors, the contents of PPD are xxx01001. They are used to determine the current discharge regime as follows: DR2 0 0 0 Valid charge action detected Program Pin Pull-Down Register (PPD) The discharge rate flags, DR2–0, are bits 6–4. FLGS2 Bits 5 4 3 DR1 DR0 - 1 7 - The FLGS2 register (address=06h) contains the secondary bq2050H flags. 6 DR2 Valid charge action not detected between a discharge from NAC = LMD and EDV1 The overload flag (OVLD) is asserted when a discharge rate in excess of 2C is detected. OVLD remains asserted as long as the condition persists and is cleared 0.5 seconds after the rate drops below 2C. The overload condition is used to stop sampling of the battery terminal characteristics for end-of-discharge determination. LMD is set to DCR upon the first valid charge after EDV is set if VDQ is set. 7 - 0 0 15 bq2050H The CPI register is incremented every time a valid charge is detected. When NAC > 0.94 * LMD, however, the CPI register increments on the first valid charge; CPI does not increment again for a valid charge until NAC < 0.94 * LMD. This prevents continuous trickle charging from incrementing CPI if self-discharge decrements NAC. The CPI register increments to 255 without rolling over. When the contents of CPI are incremented to 64, the capacity inaccurate flag, CI, is asserted in the FLGS1 register. The CPI register is reset whenever an update of the LMD register is performed, and the CI flag is also cleared. Scaled Available Energy Registers (SAEH/SAEL) The SAEH high-byte register (address = 0Fh) and the SAEL low-byte register (address = 10h) are used to scale battery voltage and CACT to a value that can be translated to watt-hours remaining under the present conditions. Relative CAC Register (RCAC) The RCAC register (address = 11h) provides the relative battery state-of-charge by dividing CACT by LMD. RCAC varies from 0 to 64h representing relative stateof-charge from 0 to 100%. Battery Voltage Register (VSB) The battery voltage register is used to read the single-cell battery voltage on the SB pin. The VSB register (address = 0Bh) is updated approximately once per second with the present value of the battery voltage. VSB = 1.2V * (VSB/256). Current Scale Register (VSRH/VSRL) The VSRH register (address = 12h) and the VSRL register (address = 13h) report the average signal across the SR and VSS pins. The bq2050H updates this register pair every 22.5s. VSRH (high-byte) and VSRL (low-byte) form a 16-bit signed integer value representing the average current during this time. The battery pack current can be calculated from: VSB Register Bits 7 6 5 4 3 2 1 0 VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0 I(mA) = (VSRH ∗ 256 + VSRL)/(8 ∗RS) Voltage Threshold Register (VTS) where: The end-of-discharge threshold voltages (EDV1 and EDVF) can be set using the VTS register (address = 0Ch). The VTS register sets the EDV1 trip point. EDVF is set 25mV below EDV1. The default value in the VTS register is A2h, representing EDV1 = 0.76V and EDVF = 0.735V. EDV1 = 1.2V * (VTS/256). RS = sense resistor value in Ω. VSRH = high-byte value of battery current VSRL = low-byte value of battery current The bq2050H indicates an average discharge current with a “1” in the MSB position of the VSRH register. To calculate discharge current, use the 2’s complement if the concatenated register contents in the above equation. VTS Register Bits 7 6 5 4 3 2 1 0 VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0 Compensated Available Charge Registers (CACT/CACD) The CACD register (address = 0Eh) contains the NAC value compensated for discharge rate. This is a monotonicly decreasing value during discharge. If the discharge rate is > 0.5C then this value is lower than NAC. CACD is updated only when the discharge rate compensated NAC value is a lower value than CACD during discharge. During charge, CACD is continuously updated with the NAC value. The CACT register (address = 0Dh) contains the CACD value compensated for temperature. CACT will contain a value lower than CACD when the battery temperature is below 10°C. The CACT value is also used in calculating the LED display pattern. 16 bq2050H Maximum Cell Voltage Register (NMCV) After these operations, a software reset will occur. The NMCV register (address 15h) is used to set the maximum battery pack voltage for control of the CFC pin. If desired, the system can write a value to NMCV to enable CFC to go low if VSB exceeds this value. This may be useful as a secondary protection of the Li-Ion battery pack. NMCV should be set to the following equation: Resetting the bq2050H sets the following: 256 ∗ MCV ∗ RB2 NMCV = 2s complement of 1.2 ∗ (RB1 + RB2) NMCV = set to 00h on power up or reset and should be programmed to the desired value by the host system. ■ CI and BRP = 1 The bq2050H can directly display capacity information using low-power LEDs. If LEDs are used, the program pins should be resistively tied to VCC or VSS for a program high or program low, respectively. The DCR register (address = 18h) stores the high-byte of the discharge count. DCR is reset to zero at the start of a valid discharge cycle and can count to a maximum of FFh. DCR will not increment if EDV1 = 1 and will not roll over from FFh. The bq2050H displays the battery charge state in relative mode. In relative mode, the battery charge is represented as a percentage of the LMD. Each LED segment represents 20% of the LMD. Program Pin Full Count (PPFC) The capacity display is also adjusted for the present battery temperature and discharge rate. The temperature adjustment reflects the available capacity at a given temperature but does not affect the NAC register. The temperature adjustments are detailed in the CACT and CACD register descriptions. The PPFC register contains information concerning the program pin configuration. This information is used to determine the data integrity of the bq2050H. The only approved user application for this register is to write a zero to this register as part of a reset request. When DISP is tied to VCC, the SEG1–5 outputs are inactive. When DISP is left floating, the display becomes active whenever the bq2050H detects a charge in progress VSRO > VSRQ. When pulled low, the segment outputs become active for a period of four seconds, ± 0.5 seconds. Voltage Offset (VOS) Interrupt (INTSS) The INTSS register (address = 38h) is useful during intial characterization of bq2050H designs. When the bq2050H counts a charge pulse, CHGI (bit 0) will be set to 1. When the bq2050H counts a discharge pulse, DCHGI (bit 3) will be set to 1. All other locations in the INTSS register are reserved. The segment outputs are modulated as two banks, with segments 1, 3, and 5 alternating with segments 2 and 4. The segment outputs are modulated at approximately 100Hz with each segment bank active for 30% of the period. SEG1 blinks at a 4Hz rate whenever VSB has been detected to be below VEDV1 (EDV1 = 1), indicating a lowbattery condition. VSB below VEDVF (EDVF = 1) disables the display output. Reset Register (RST) The reset register (address = 39h) provides an alternate means of initializing the bq2050H via software. Since this register contains device test bits, it is recommended to use the PPFC and LMD registers to reset the bq2050H. Setting any bits in the reset register is not allowed and will result in improper bq2050H operation. The recommended reset method for the bq2050H is : Write LMD to zero CPI, VDQ, RCAC, NACH/L, CACH/L, SAEH/L, NMCV = 0 Display Discharge Count Register (DCR) ■ ■ The HEXFF register (address = 3F) is useful in determing if the device is a bq2050H or a bq2050. This register is always set to FFh for the bq2050H. The bq2050 returns data other than FFh. MCV = maximum desired battery stack voltage. Write PPFC to zero LMD = PFC Check Register (HEXFF) Where: ■ ■ Microregulator A micropower source for the bq2050H can be inexpensively built using a FET and an external resistor. (See Figure 1.) 17 bq2050H Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit Notes VCC Relative to VSS -0.3 +7.0 V All other pins Relative to VSS -0.3 +7.0 V REF Relative to VSS -0.3 +8.5 V Current limited by R1 (see Figure 1) VSR Relative to VSS -0.3 Vcc+0.7 V 100kΩ series resistor should be used to protect SR in case of a shorted battery. TOPR Operating temperature 0 +70 °C Commercial Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V) Symbol Parameter Minimum Typical Maximum Unit Notes VEDV1 First empty warning 0.73 0.76 0.79 V SB, default VEDVF Final empty warning VEDV1 - 0.035 VEDV1 - 0.025 VEDV1 - 0.015 V SB, default VSRO SR sense range -300 - +500 mV SR, VSR + VOS VSRQ Valid charge 250 - - µV VSR + VOS (see note) VSRD Valid discharge - - -250 µV VSR + VOS (see note) VMCV Maximum SB voltage 1.10 1.12 1.15 V Note: SB pin VOS is affected by PC board layout. Proper layout guidelines should be followed for optimal performance. See “Layout Considerations.” 18 bq2050H DC Electrical Characteristics (TA = TOPR) Symbol Parameter VCC Supply voltage VOS Offset referred to VSR Minimum Typical Maximum Unit 3.0 4.25 6.5 V 5.7 4.5 2.0 0 10 -0.2 500 10 VCC - 0.2 float ±50 6.0 5.0 90 120 170 - ±150 6.3 7.5 135 180 250 VCC 5 0.2 100 VSS + 0.2 float µV V V MΩ µA µA µA V MΩ µA µA nA KΩ MΩ V V V Notes VCC excursion from < 2.0V to ≥ 3.0V initializes the unit. DISP = VCC IREF = 5µA IREF = 5µA VREF = 3V VCC = 3.0V, HDQ = 0 VCC = 4.25V, HDQ = 0 VCC = 6.5V, HDQ = 0 RREF Reference at 25°C Reference at -40°C to +85°C Reference input impedance ICC Normal operation VSB RSBmax IDISP ILCOM IRBI RHDQ RSR VIHPFC VILPFC VIZPFC Battery input SB input impedance DISP input leakage LCOM input leakage RBI data retention current Internal pulldown SR input impedance Logic input high Logic input low Logic input Z VOLSL SEG output low, low VCC - 0.1 - V VOLSH SEG output low, high VCC - 0.4 - V VOHML VOHMH IOLS IOL VOL VIHDQ VILDQ VIH VIL LCOM output high, low VCC VCC - 0.3 LCOM output high, high VCC VCC - 0.6 SEG sink current 11.0 Open-drain sink current 5.0 Open-drain output low HDQ input high 2.5 HDQ input low Logic input high 2.5 Logic input low Soft pull-up or pull-down resistor value (for programming) Float state external impedance - - 0.3 0.8 0.5 V V mA mA V V V V V -200mV < VSR < VCC PROG1–5 PROG1–5 PROG1–5 VCC = 3V, IOLS ≤ 1.75mA SEG1–SEG5, CFC VCC = 6.5V, IOLS ≤ 11.0mA SEG1–SEG5, CFC VCC = 3V, IOHLCOM = -5.25mA VCC > 3.5V, IOHLCOM = -33.0mA At VOLSH = 0.4V, VCC = 6.5V At VOL = VSS + 0.3V, HDQ IOL ≤ 5mA, HDQ HDQ HDQ PSTAT PSTAT - 200 KΩ PROG1–5 5 - MΩ PROG1–5 VREF RPROG RFLOAT Note: All voltages relative to VSS. 19 0 < VSB < VCC VDISP = VSS DISP = VCC VRBI > VCC < 3V bq2050H High-Speed Serial Communication Timing Specification (TA = TOPR) Parameter Minimum tCYCH Symbol Cycle time, host to bq2050H (write) 190 - - µs tCYCB Cycle time, bq2050H to host (read) 190 205 250 µs tSTRH Start hold, host to bq2050H (write) 5 - - ns tSTRB Start hold, bq2050H to host (read) 32 - - µs tDSU Data setup - - 50 µs tDSUB Data setup - - 50 µs tDH Data hold 90 - - µs tDV Data valid - - 80 µs tSSU Stop setup - - 145 µs tSSUB Stop setup - - 145 µs tRSPS Response time, bq2050H to host 190 - 320 µs tB Break 190 - - µs tBR Break recovery 40 - - µs Note: Typical Maximum Unit Notes See note The open-drain HDQ pin should be pulled to at least VCC by the host system for proper HDQ operation. HDQ may be left floating if the serial interface is not used. 20 bq2050H Break Timing tBR tB TD201803.eps Host to bq2050H Write "1" Write "0" tSTRH tDSU tDH tSSU tCYCH bq2050H to Host Read "1" Read "0" tSTRB tDSUB tDV tSSUB tCYCB 21 bq2050H 16-Pin SOIC Narrow (SN) 16-Pin SN (0.150" SOIC) D e Inches B E H A C A1 .004 L 22 Millimeters Dimension Min. Max. Min. Max. A 0.060 0.070 1.52 1.78 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.18 0.25 D 0.385 0.400 9.78 10.16 E 0.150 0.160 3.81 4.06 e 0.045 0.055 1.14 1.40 H 0.225 0.245 5.72 6.22 L 0.015 0.035 0.38 0.89 bq2050H Data Sheet Revision History ChangeNo. Page No. 1 All 2 8 Digital magnitude filter changed from 200µV to 250µV. 2 18 VSRQ changed from 200µV(min) to 250µV(min). 2 18 VSRD changed from -200µV(max) to -250µV(max). 3 3 Updated application diagram 3 12 Changed designation on appropriate locations from “R/W” to “R” 3 16 Clarified current scale register description 3 18 Changed VSRO max. from +2000mV to +500mV 3 19 Changed VOL max. from 0.5V to 0.3V 3 20 Changed tSSUB max. from 95µs to 145µs Notes: Description of Change “Final” changes from “Preliminary” version Change 1 = Aug. 1997 B changes from June 1996 “Preliminary.” Change 2 = June 1998 C changes from Aug. 1997 B. Change 3 = May 1999 D changes from June 1998 C. Ordering Information bq2050H Temperature Range: blank = Commercial (0 to +70°C) Package Option: SN = 16-pin narrow SOIC Device: bq2050H Power Gauge IC 23 PACKAGE OPTION ADDENDUM www.ti.com 8-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BQ2050HSN-A508 ACTIVE SOIC D 16 40 None CU NIPDAU Level-1-220C-UNLIM BQ2050HSN-A508TR ACTIVE SOIC D 16 2500 None CU NIPDAU Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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