SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 3.3-V CAN TRANSCEIVERS FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • (1) Operates With a 3.3-V Supply Low Power Replacement for the PCA82C250 Footprint Bus/Pin ESD Protection Exceeds 16 kV HBM High Input Impedance Allows for 120 Nodes on a Bus Controlled Driver Output Transition Times for Improved Signal Quality on the SN65HVD230 and SN65HVD231 Unpowered Node Does Not Disturb the Bus Compatible With the Requirements of the ISO 11898 Standard Low-Current SN65HVD230 Standby Mode 370 µA Typical Low-Current SN65HVD231 Sleep Mode 40 nA Typical Designed for Signaling Rates(1) up to 1 Megabit/Second (Mbps) Thermal Shutdown Protection Open-Circuit Fail-Safe Design Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications Motor Control Industrial Automation Basestation Control and Status Robotics Automotive UPS Control SN65HVD230D (Marked as VP230) SN65HVD231D (Marked as VP231) (TOP VIEW) D GND VCC R 1 8 2 7 3 6 4 5 RS CANH CANL Vref SN65HVD232D (Marked as VP232) (TOP VIEW) D GND VCC R 1 8 2 7 3 6 4 5 NC CANH CANL NC NC – No internal connection The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). LOGIC DIAGRAM (POSITIVE LOGIC) SN65HVD230, SN65HVD231 Logic Diagram (Positive Logic) VCC 3 5 SN65HVD232 Logic Diagram (Positive Logic) Vref D D RS R 1 1 8 4 R 7 6 4 7 6 CANH CANL CANH CANL Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320Lx240x is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2006, Texas Instruments Incorporated SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The SN65HVD230, SN65HVD231, and SN65HVD232 controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x™; 3.3-V DSPs with CAN controllers, or with equivalent devices. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Designed for operation in especially-harsh environments, these devices feature cross-wire protection, loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range. The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial, building automation, and automotive applications. It operates over a -2-V to 7-V common-mode range on the bus, and it can withstand common-mode transients of ±25 V. On the SN65HVD230 and SN65HVD231, pin 8 provides three different modes of operation: high-speed, slope control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground, allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the slope is proportional to the pin's output current. This slope control is implemented with external resistor values of 10 kΩ, to achieve a 15-V/µs slew rate, to 100 kΩ, to achieve a 2-V/µs slew rate. See the Application Information section of this data sheet. The circuit of the SN65HVD230 enters a low-current standby mode during which the driver is switched off and the receiver remains active if a high logic level is applied to pin 8. The DSP controller reverses this low-current standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The unique difference between the SN65HVD230 and the SN65HVD231 is that both the driver and the receiver are switched off in the SN65HVD231 when a high logic level is applied to pin 8 and remain in this sleep mode until the circuit is reactivated by a low logic level on pin 8. The Vref pin 5 on the SN65HVD230 and SN65HVD231 is available as a VCC/2 voltage reference. The SN65HVD232 is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection. AVAILABLE OPTIONS (1) PART NUMBER LOW POWER MODE INTEGRATED SLOPE CONTROL Vref PIN SN65HVD230 Standby mode Yes Yes SN65HVD231 Sleep mode Yes Yes SN65HVD232 No standby or sleep mode No No (1) TA MARKED AS: VP230 40°C to 85°C VP231 VP232 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. FUNCTION TABLES DRIVER (SN65HVD230, SN65HVD231) (1) INPUT D L H (1) 2 RS V(Rs) < 1.2 V OUTPUTS CANH CANL BUS STATE H L Dominant Z Z Recessive Open X Z Z Recessive X V(Rs) > 0.75 VCC Z Z Recessive H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance Submit Documentation Feedback SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 DRIVER (SN65HVD232) (1) OUTPUTS INPUT D (1) CANH BUS STATE CANL L H L Dominant H Z Z Recessive Open Z Z Recessive H = high level; L = low level; Z = high impedance RECEIVER (SN65HVD230) (1) (1) DIFFERENTIAL INPUTS RS OUTPUT R VID ≥ 0.9 V X L 0.5 V < VID < 0.9 V X ? VID ≤ 0.5 V X H Open X H H = high level; L = low level; X = irrelevant; ? = indeterminate RECEIVER (SN65HVD231) (1) DIFFERENTIAL INPUTS RS OUTPUT R VID ≥ 0.9 V L 0.5 V < VID < 0.9 V V(Rs) < 1.2 V ? VID ≤ 0.5 V (1) H X V(Rs) > 0.75 VCC X 1.2 V < V(Rs) < 0.75 VCC H ? Open X H H = high level; L = low level; X = irrelevant; ? = indeterminate RECEIVER (SN65HVD232) (1) (1) DIFFERENTIAL INPUTS OUTPUT R VID ≥ 0.9 V L 0.5 V < VID < 0.9 V ? VID ≤ 0.5 V H Open H H = high level; L = low level; X = irrelevant; ? = indeterminate TRANSCEIVER MODES (SN65HVD230, SN65HVD231) V(Rs) OPERATING MODE V(Rs) > 0.75 VCC Standby 10 kΩ to 100 kΩ to ground Slope control V(Rs) < 1 V High speed (no slope control) TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. SN65HVD230, SN65HVD231 CANL 6 Low bus output CANH 7 High bus output D 1 Driver input GND 2 Ground R 4 Receiver output Submit Documentation Feedback 3 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 TERMINAL FUNCTIONS (continued) TERMINAL NAME DESCRIPTION NO. RS 8 Standby/slope control VCC 3 Supply voltage Vref 5 Reference output CANL 6 Low bus output CANH 7 High bus output D 1 Driver input GND 2 Ground SN65HVD232 NC 5, 8 No connection R 4 Receiver output VCC 3 Supply voltage EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS CANH and CANL Inputs D Input VCC VCC 16 V 110 kΩ 9 kΩ 100 kΩ 45 kΩ Input 1 kΩ Input 20 V 9 kΩ 9V CANH and CANL Outputs R Output VCC VCC 16 V 5Ω Output 9V 20 V 4 Output Submit Documentation Feedback SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) UNIT Supply voltage range, VCC -0.3 V to 6 V Voltage range at any bus terminal (CANH or CANL) -4 V to 16 V Voltage input range, transient pulse, CANH and CANL, through 100 Ω (see Figure 7) -25 V to 25 V Input voltage range, VI (D or R) -0.5 V to VCC + 0.5 V ±11 mA Receiver output current, IO Human body model (3) Electrostatic discharge Charged-device model (4) CANH, CANL and GND 16 kV All Pins 4 kV All pins 1 kV Continuous total power dissipation (1) (2) (3) (4) See Dissipation Rating Table Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods amy affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. DISSIPATION RATING TABLE (1) PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supply voltage, VCC Voltage at any bus terminal (common mode) VIC Voltage at any bus terminal (separately) VI High-level input voltage, VIH D, R Low-level input voltage, VIL D, R Differential input voltage, VID (see Figure 5) Input voltage, V(Rs) Input voltage for standby or sleep, V(Rs) Wave-shaping resistance, Rs High-level output current, IOH Low-level output current, IOL Driver Receiver 3.6 V 7 V -2.5 7.5 V 2 V 0.8 V -6 6 V V 0 VCC 0.75 VCC VCC V 0 100 kΩ -40 mA -8 Driver 48 Receiver Operating free-air temperature, TA (1) 3 -2 (1) 8 -40 85 mA °C The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. Submit Documentation Feedback 5 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VOH TEST CONDITIONS Dominant VI = 0 V, See Figure 1 and Figure 3 CANH Recessive VI = 3 V, See Figure 1 and Figure 3 CANH Bus output voltage VOL VOD(D) Dominant Differential output voltage VOD(R) Recessive VCC CANL 0.5 1.25 2.3 CANL See Figure 1 1.5 2 3 VI = 0 V, See Figure 2 1.2 2 3 VI = 3 V, See Figure 1 -120 0 12 VI = 3 V, No load -0.5 -0.2 0.05 High-level input current VI = 2 V -30 Low-level input current VI = 0.8 V -30 Co Output capacitance Supply current ICC V V mV V µA µA VCANH = -2 V -250 250 VCANL = 7 V -250 250 mA See receiver Standby SN65HVD230 V(Rs) = VCC 370 600 Sleep SN65HVD231 V(Rs) = VCC, D at VCC 0.04 1 Dominant VI = 0 V, No load Dominant 10 17 Recessive VI = VCC, No load Recessive 10 17 All devices (1) UNIT 2.3 VI = 0 V, IIL Short-circuit output current MAX 2.45 IIH IOS TYP (1) MIN µA mA All typical values are at 25°C and with a 3.3-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT SN65HVD230 AND SN65HVD231 tPLH tPHL Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output V(Rs) = 0 V 35 85 RS with 10 kΩ to ground 70 125 RS with 100 kΩ to ground 500 870 70 120 V(Rs) = 0 V RS with 10 kΩ to ground 130 180 RS with 100 kΩ to ground 870 1200 V(Rs) = 0 V tsk(p) Pulse skew (|tPHL - tPLH|) RS with 10 kΩ to ground Differential output signal rise time tf Differential output signal fall time tr Differential output signal rise time tf Differential output signal fall time tr Differential output signal rise time tf Differential output signal fall time ns 35 CL = 50 pF, See Figure 4 60 RS with 100 kΩ to ground tr ns ns 370 V(Rs) = 0 V RS with 10 kΩ to ground RS with 100 kΩ to ground 25 50 100 ns 40 55 80 ns 80 120 160 ns 80 125 150 ns 600 800 1200 ns 600 825 1000 ns SN65HVD232 6 tPLH Propagation delay time, low-to-high-level output 35 85 tPHL Propagation delay time, high-to-low-level output 70 120 tsk(p) Pulse skew (|tPHL - tPLH|) tr Differential output signal rise time 25 50 100 tf Differential output signal fall time 40 55 80 CL = 50 pF, See Figure 4 Submit Documentation Feedback 35 ns SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIT+ Positive-going input threshold voltage VIT- Negative-going input threshold voltage Vhys Hysteresis voltage (VIT+ - VIT-) VOH High-level output voltage -6 V ≤ VID ≤ 500 mV, IO = -8 mA, See Figure 5 VOL Low-level output voltage 900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5 See Table 1 UNIT 900 mV 650 mV 100 VIH = 7 V, Bus input current MAX 750 500 2.4 0.4 VIH = 7 V II TYP (1) VCC = 0 V Other input at 0 V, D=3V VIH = -2 V VIH = -2 V, VCC = 0 V 100 250 100 350 -200 -30 -100 -20 V µA µA Ci CANH, CANL input capacitance Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 32 pF Cdiff Differential input capacitance Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 16 pF Rdiff Differential input resistance Pin-to-pin, RI CANH, CANL input resistance ICC Supply current (1) V(D) = 3 V 40 70 100 kΩ 20 35 50 kΩ See driver All typical values are at 25°C and with a 3.3-V supply. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tPHL - tPLH|) tr Output signal rise time tf Output signal fall time MIN See Figure 6 See Figure 6 TYP MAX UNIT 35 50 ns 35 50 ns 10 ns 1.5 ns 1.5 ns DEVICE SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER t(LOOP1) t(LOOP2) TEST CONDITIONS Total loop delay, driver input to receiver output, recessive to dominant Total loop delay, driver input to receiver output, dominant to recessive TYP MAX V(Rs) = 0 V, See Figure 9 MIN 70 115 RS with 10 kΩ to ground, See Figure 9 105 175 RS with 100 kΩ to ground, See Figure 9 535 920 V(Rs) = 0 V, See Figure 9 100 135 RS with 10 kΩ to ground, See Figure 9 155 185 RS with 100 kΩ to ground, See Figure 9 830 990 UNIT ns ns DEVICE CONTROL-PIN CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER t(WAKE) (1) TEST CONDITIONS SN65HVD230 wake-up time from standby mode with RS SN65HVD231 wake-up time from sleep mode with RS MIN TYP (1) MAX 0.55 1.5 µs 3 5 µs UNIT See Figure 8 All typical values are at 25°C and with a 3.3-V supply. Submit Documentation Feedback 7 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 DEVICE CONTROL-PIN CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER Vref Reference output voltage I(Rs) Input current for high-speed TEST CONDITIONS MIN -5 µA < I(Vref) < 5 µA -50 µA < I(Vref) < 50 µA TYP (1) MAX 0.45 VCC 0.55 VCC 0.4 VCC 0.6 VCC -450 0 V(Rs) < 1 V PARAMETER MEASUREMENT INFORMATION VCC IO II D IO 60 Ω 0 V or 3 V VOD CANH VI CANL Figure 1. Driver Voltage and Current Definitions 167 Ω VOD 0V 60 Ω 167 Ω ± –2 V ≤ VTEST ≤ 7 V Figure 2. Driver VOD Dominant CANH Recessive CANL ≈3V VOH ≈ 2.3 V VOL ≈1V VOH Figure 3. Driver Output Voltage Definitions 8 Submit Documentation Feedback CANH CANL UNIT V µA SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION (continued) RL = 60 Ω Signal Generator (see Note A) CL = 50 pF (see Note B) VO 50 Ω RS = 0 Ω to 100 kΩ for SN65HVD230 and SN65HVD231 N/A for SN65HVD232 3V Input 1.5 V 0V tPLH tPHL VOD(D) 90% 0.9 V Output 0.5 V 10% tr VOD(R) tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, Zo = 50 Ω. B. CL includes probe and jig capacitance. Figure 4. Driver Test Circuit and Voltage Waveforms IO VID V )V CANL VIC + CANH 2 VCANH VO VCANL Figure 5. Receiver Voltage and Current Definitions Submit Documentation Feedback 9 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Output Signal Generator (see Note A) 50 Ω 1.5 V CL = 15 pF (see Note B) 2.9 V Input 2.2 V 1.5 V tPLH tPHL VOH 90% Output 1.3 V 10% tr A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, Zo = 50 Ω. B. CL includes probe and jig capacitance. Figure 6. Receiver Test Circuit and Voltage Waveforms 100 Ω Pulse Generator, 15 µs Duration, 1% Duty Cycle Figure 7. Overvoltage Protection 10 VOL tf Submit Documentation Feedback SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Table 1. Receiver Characteristics Over Common Mode With V(Rs) = 1.2 V VIC VID VCANH VCANL R OUTPUT -2 V 900 mV -1.55 V -2.45 V L 7V 900 mV 8.45 V 6.55 V L 1V 6V 4V -2 V L 4V 6V 7V 1V L -2 V 500 mV -1.75 V -2.25 V H 7V 500 mV 7.25 V 6.75 V H 1V -6 V -2 V 4V H 4V -6 V 1V 7V H X X Open Open H VOL VOH VCC 10 kΩ D R 60 Ω 0V Output CL = 15 pF RS Generator PRR = 150 kHz 50% Duty Cycle tr, tf < 6 ns Zo = 50 Ω Signal Generator 50 Ω + V(Rs) – VCC 1.5 V V(Rs) 0V t(WAKE) 1.3 V R Output Figure 8. t(WAKE) Test Circuit and Voltage Waveforms Submit Documentation Feedback 11 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 0 Ω, 10 kΩ or 100 kΩ ±5% RS DUT CANH VI D 60 Ω ±1% CANL R + 15 pF ±20% VO VCC VI 50% 50% 0V t(LOOP2) t(LOOP1) VOH VO 50% 50% VOL A. All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle. Figure 9. t(LOOP) Test Circuit and Voltage Waveforms TYPICAL CHARACTERISTICS LOGIC INPUT CURRENT (PIN D) vs INPUT VOLTAGE 22 0 21 −2 I I(L) − Logic Input Current − µ A I CC − Supply Current (RMS) − mA SUPPLY CURRENT (RMS) vs FREQUENCY 20 19 18 17 16 15 −4 −6 −8 −10 −12 −14 14 13 −16 0 250 500 750 1000 0 f − Frequency − kbps Figure 10. 12 0.6 1.1 1.6 2.1 2.6 VI − Input Voltage − V Figure 11. Submit Documentation Feedback 3.1 3.6 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) BUS INPUT CURRENT vs BUS INPUT VOLTAGE DRIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 160 I OL− Driver Low-Level Output Current − mA I I − Bus Input Current − µ A 400 300 200 VCC = 0 V 100 VCC = 3.6 V 0 −100 −200 −300 −400 −7 −6 −4 −3 −1 0 140 120 100 80 60 40 20 0 1 3 4 6 7 0 8 10 11 12 VI − Bus Input Voltage − V Figure 12. Figure 13. DRIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE DOMINANT VOLTAGE (VOD) vs FREE-AIR TEMPERATURE 4 3 120 VCC = 3.6 V 2.5 100 VOD− Dominant Voltage − V I OH − Driver High-Level Output Current − mA 1 2 3 VO(CANL)− Low-Level Output Voltage − V 80 60 40 VCC = 3 V 2 1.5 1 0.5 20 0 VCC = 3.3 V 0 0 0.5 1 1.5 2 2.5 3 3.5 VO(CANH) − High-Level Output Voltage − V Figure 14. −55 −40 0 25 70 85 125 TA − Free-Air Temperature − °C Figure 15. Submit Documentation Feedback 13 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) 38 RS = 0 37 36 VCC = 3 V 35 VCC = 3.3 V 34 VCC = 3.6 V 33 32 31 30 −55 −40 0 25 70 85 125 RECEIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL− Receiver High-to-Low Propagation Delay Time − ns t PLH − Receiver Low-to-High Propagation Delay Time − ns RECEIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 40 RS = 0 39 VCC = 3 V 38 VCC = 3.3 V 37 VCC = 3.6 V 36 35 34 −55 0 25 70 85 125 Figure 16. Figure 17. DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 55 RS = 0 VCC = 3 V 50 45 40 VCC = 3.3 V 35 VCC = 3.6 V 30 25 20 15 10 −55 −40 0 25 70 85 125 90 RS = 0 VCC = 3.6 V 85 80 VCC = 3.3 V 75 70 VCC = 3 V 65 60 55 50 −55 TA − Free-Air Temperature − °C Figure 18. 14 −40 TA − Free-Air Temperature − °C t PHL− Driver High-to-Low Propagation Delay Time − ns t PLH − Driver Low-to-High Propagation Delay Time − ns TA − Free-Air Temperature − °C −40 0 25 85 TA − Free-Air Temperature − °C Figure 19. Submit Documentation Feedback 70 125 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) 90 RS = 10 kΩ 80 70 VCC = 3 V VCC = 3.3 V 60 50 VCC = 3.6 V 40 30 20 10 0 −55 −40 0 25 70 85 125 DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL − Driver High-to-Low Propagation Delay Time − ns t PLH − Driver Low-to-High Propagation Delay Time − ns DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 150 140 VCC = 3.3 V 130 VCC = 3 V 120 110 100 90 80 −55 TA − Free-Air Temperature − °C −40 0 25 70 85 125 TA − Free-Air Temperature − °C Figure 20. Figure 21. DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 800 RS = 100 kΩ 700 VCC = 3 V 600 VCC = 3.3 V 500 VCC = 3.6 V 400 300 200 100 0 −55 −40 0 25 70 85 125 t PHL− Driver High-to-Low Propagation Delay Time − ns t PLH − Driver Low-to-High Propagation Delay Time − ns RS = 10 kΩ VCC = 3.6 V 1000 RS = 100 kΩ VCC = 3.6 V 950 VCC = 3.3 V 900 850 VCC = 3 V 800 750 700 TA − Free-Air Temperature − °C Figure 22. −55 −40 0 25 70 85 125 TA − Free-Air Temperature − °C Figure 23. Submit Documentation Feedback 15 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE DIFFERENTIAL DRIVER OUTPUT FALL TIME vs SOURCE RESISTANCE (Rs) µs t f − Differential Driver Output Fall Time − I O − Driver Output Current − mA 50 40 30 20 10 1.50 1.40 1.30 VCC = 3.3 V 1.20 1.10 VCC = 3.6 V 1.00 0.90 0.80 0.70 0.60 VCC = 3 V 0.50 0.40 0.30 0.20 0.10 0 0 1 1.5 2 2.5 3 3.5 4 0 50 VCC − Supply Voltage − V REFERENCE VOLTAGE vs REFERENCE CURRENT HVD230, HVD231 LOW-TO-HIGH PROPAGATION DELAY TIME vs COMMON-MODE INPUT VOLTAGE t PLH − Low-to-High Propagation Delay Time − ns V ref − Reference Voltage − V VCC = 3.6 V 1.5 VCC = 3 V 1 0.5 0 −5 5 50 600 See Figure 30 500 400 Rs = 10 kW 300 Rs = 0 W 200 100 0 −2 Iref − Reference Current − µA Figure 26. 16 200 Figure 25. 2.5 −50 150 Figure 24. 3 2 100 Rs − Source Resistance − kΩ 1 4 VIC − Common-Mode Input Voltage − V Figure 27. Submit Documentation Feedback 7 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) HVD230, HVD231 LOW-TO-HIGH PROPAGATION DELAY TIME vs COMMON-MODE INPUT VOLTAGE 600 See Figure 30 t PLH − Low-to-High Propagation Delay Time − ns t PLH − Low-to-High Propagation Delay Time − ns 1600 1400 1200 1000 Rs = 100 kW 800 600 400 200 0 HVD232 LOW-TO-HIGH PROPAGATION DELAY TIME vs COMMON-MODE INPUT VOLTAGE 0 4 1 VIC − Common-Mode Input Voltage − V 7 See Figure 30 500 400 300 200 100 0 −2 1 7 VIC − Common-Mode Input Voltage − V Figure 28. Figure 29. 375 Ω ± 1% Y D Z Input Generator 4 VOD 60 Ω ± 1% 375 Ω ± 1% ± V 50 Ω −2 V ≤ VIC ≤ 7 V Figure 30. Driver Schematic Submit Documentation Feedback 17 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 APPLICATION INFORMATION This application provides information concerning the implementation of the physical medium attachment layer in a CAN network according to the ISO 11898 standard. It presents a typical application circuit and test results, as well as discussions on slope control, total loop delay, and interoperability in 5-V systems. INTRODUCTION ISO 11898 is the international standard for high-speed serial communication using the controller area network (CAN) bus protocol. It supports multimaster operation, real-time control, programmable data rates up to 1 Mbps, and powerful redundant error checking procedures that provide reliable data transmission. It is suited for networking intelligent devices as well as sensors and actuators within the rugged electrical environment of a machine chassis or factory floor. The SN65HVD230 family of 3.3-V CAN transceivers implement the lowest layers of the ISO/OSI reference model. This is the interface with the physical signaling output of the CAN controller of the Texas Instruments TMS320Lx240x 3.3-V DSPs, as illustrated in Figure 31. ISO 11898 Specification Implementation Application Specific Layer TMS320Lx2403/6/7 3.3-V DSP Logic Link Control Data-Link Layer Medium Access Control Embedded CAN Controller Physical Signaling Physical Layer Physical Medium Attachment SN65HVD230 Medium Dependent Interface CAN Bus-Line Figure 31. The Layered ISO 11898 Standard Architecture The SN65HVD230 family of CAN transceivers are compatible with the ISO 11898 standard; this ensures interoperability with other standard-compliant products. APPLICATION OF THE SN65HVD230 Figure 32 illustrates a typical application of the SN65HVD230 family. The output of a DSP's CAN controller is connected to the serial driver input, pin D, and receiver serial output, pin R, of the transceiver. The transceiver is then attached to the differential bus lines at pins CANH and CANL. Typically, the bus is a twisted pair of wires with a characteristic impedance of 120 Ω, in the standard half-duplex multipoint topology of Figure 33. Each end of the bus is terminated with 120-Ω resistors in compliance with the standard to minimize signal reflections on the bus. 18 Submit Documentation Feedback SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 APPLICATION INFORMATION (continued) Electronic Control Unit (ECU) TMS320Lx2403/6/7 CAN-Controller CANTX/IOPC6 CANRX/IOPC7 D R SN65HVD230 CANH CANL CAN Bus Line Figure 32. Details of a Typical CAN Node ECU 1 ECU 2 ECU n CANH 120 Ω CAN Bus Line 120 Ω CANL Figure 33. Typical CAN Network The SN65HVD230/231/232 3.3-V CAN transceivers provide the interface between the 3.3-V TMS320Lx2403/6/7 CAN DSPs and the differential bus line, and are designed to transmit data at signaling rates up to 1 Mbps as defined by the ISO 11898 standard. FEATURES of the SN65HVD230, SN65HVD231, and SN65HVD232 The SN65HVD230/231/232 are pin-compatible (but not functionally identical) with one another and, depending upon the application, may be used with identical circuit boards. These transceivers feature 3.3-V operation and standard compatibility with signaling rates up to 1 Mbps, and also offer 16-kV HBM ESD protection on the bus pins, thermal shutdown protection, bus fault protection, and open-circuit receiver failsafe. The fail-safe design of the receiver assures a logic high at the receiver output if the bus wires become open circuited. If a high ambient operating environment temperature or excessive output current result in thermal shutdown, the bus pins become high impedance, while the D and R pins default to a logic high. Submit Documentation Feedback 19 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 APPLICATION INFORMATION (continued) The bus pins are also maintained in a high-impedance state during low VCC conditions to ensure glitch-free power-up and power-down bus protection for hot-plugging applications. This high-impedance condition also means that an unpowered node does not disturb the bus. Transceivers without this feature usually have a very low output impedance. This results in a high current demand when the transceiver is unpowered, a condition that could affect the entire bus. OPERATING MODES RS (pin 8) of the SN65HVD230 and SN65HVD231 provides for three different modes of operation: high-speed mode, slope-control mode, and low-power mode. High-Speed The high-speed mode can be selected by applying a logic low to RS (pin 8). The high-speed mode of operation is commonly employed in industrial applications. High-speed allows the output to switch as fast as possible with no internal limitation on the output rise and fall slopes. The only limitations of the high-speed operation are cable length and radiated emission concerns, each of which is addressed by the slope control mode of operation. If the low-power standby mode is to be employed in the circuit, direct connection to a DSP output pin can be used to switch between a logic-low level (< 1 V) for high speed operation, and the logic-high level (> 0.75 VCC) for standby. Figure 34 shows a typical DSP connection, and Figure 35 shows the HVD230 driver output signal in high-speed mode on the CAN bus. D GND VCC R 1 8 2 7 3 6 4 5 RS IOPF6 CANH CANL Vref TMS320LF2406 or TMS320LF2407 Figure 34. RS (Pin 8) Connection to a TMS320LF2406/07 for High Speed/Standby Operation 1 Mbps Driver Output NRZ Data 1 Figure 35. Typical High Speed SN65HVD230 Output Waveform Into a 60-Ω Load 20 Submit Documentation Feedback SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 APPLICATION INFORMATION (continued) Slope Control Electromagnetic compatibility is essential in many applications using unshielded bus cable to reduce system cost. To reduce the electromagnetic interference generated by fast rise times and resulting harmonics, the rise and fall slopes of the SN65HVD230 and SN65HVD231 driver outputs can be adjusted by connecting a resistor from RS (pin 8) to ground or to a logic low voltage, as shown in Figure 36. The slope of the driver output signal is proportional to the pin's output current. This slope control is implemented with an external resistor value of 10 kΩ to achieve a ≈ 15 V/µs slew rate, and up to 100 kΩ to achieve a ≈ 2.0 V/µs slew rate as displayed in Figure 37. Typical driver output waveforms from a pulse input signal with and without slope control are displayed in Figure 38. A pulse input is used rather than NRZ data to clearly display the actual slew rate. D GND VCC R 1 8 2 7 3 6 4 5 10 kΩ to 100 kΩ RS IOPF6 TMS320LF2406 or TMS320LF2407 CANH CANL Vref Figure 36. Slope Control/Standby Connection to a DSP DRIVER OUTPUT SIGNAL SLOPE vs SLOPE CONTROL RESISTANCE Driver Outout Signal Slop – V/ µ s 25 20 15 10 5 0 0 10 4.7 20 30 40 50 33 60 47 70 6.8 10 15 22 Slope Control Resistance – kΩ 80 68 90 100 Figure 37. HVD230 Driver Output Signal Slope vs Slope Control Resistance Value Submit Documentation Feedback 21 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 APPLICATION INFORMATION (continued) RS = 0 Ω RS = 10 kΩ RS = 100 kΩ Figure 38. Typical SN65HVD230 250-kbps Output Pulse Waveforms With Slope Control Standby Mode (Listen Only Mode) of the HVD230 If a logic high (> 0.75 VCC) is applied to RS (pin 8) in Figure 34 and Figure 36, the circuit of the SN65HVD230 enters a low-current, listen only standby mode, during which the driver is switched off and the receiver remains active. In this listen only state, the transceiver is completely passive to the bus. It makes no difference if a slope control resistor is in place as shown in Figure 36. The DSP can reverse this low-power standby mode when the rising edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The DSP, sensing bus activity, reactivates the driver circuit by placing a logic low (< 1.2 V) on RS (pin 8). The Babbling Idiot Protection of the HVD230 Occasionally, a runaway CAN controller unintentionally sends messages that completely tie up the bus (what is referred to in CAN jargon as a babbling idiot). When this occurs, the DSP can engage the listen-only standby mode to disengage the driver and release the bus, even when access to the CAN controller has been lost. When the driver circuit is deactivated, its outputs default to a high-impedance state. Sleep Mode of the HVD231 The unique difference between the SN65HVD230 and the SN65HVD231 is that both driver and receiver are switched off in the SN65HVD231 when a logic high is applied to RS (pin 8). The device remains in a very low power-sleep mode until the circuit is reactivated with a logic low applied to RS (pin 8). While in this sleep mode, the bus-pins are in a high-impedance state, while the D and R pins default to a logic high. LOOP PROPAGATION DELAY Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the driver input to the differential outputs, plus the delay from the receiver inputs to its output. The loop delay of the transceiver displayed in Figure 39 increases accordingly when slope control is being used. This increased loop delay means that the total bus length must be reduced to meet the CAN bit-timing requirements of the overall system. The loop delay becomes ≈ 100 ns when employing slope control with a 22 Submit Documentation Feedback SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 APPLICATION INFORMATION (continued) 10-kΩ resistor, and ≈ 500 ns with a 100-kΩ resistor. Therefore, considering that the rule-of-thumb propagation delay of typical bus cable is 5 ns/m, slope control with the 100-kΩ resistor decreases the allowable bus length by the difference between the 500-ns max loop delay and the loop delay with no slope control, 70.7 ns. This equates to (500-70.7 ns)/5 ns, or approximately 86 m less bus length. This slew-rate/bus length trade-off to reduce electromagnetic interference to adjoining circuits from the bus can also be solved with a quality shielded bus cable. ( ) Figure 39. 70.7-ns Loop Delay Through the HVD230 With RS = 0 INTEROPERABILITY WITH 5-V CAN SYSTEMS It is essential that the 3.3-V HVD230 family performs seamlessly with 5-V transceivers because of the large number of 5-V devices installed. Figure 40 displays a test bus of a 3.3-V node with the HVD230, and three 5-V nodes: one for each of TI's SN65LBC031 and UC5350 transceivers, and one using a competitor X250 transceiver. Submit Documentation Feedback 23 SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 APPLICATION INFORMATION (continued) Tektronix HFS–9003 Pattern Generator Trigger Input Tektronix 784D Oscilloscope Tektronix P6243 Single-Ended Probes One Meter Belden Cable #82841 120 Ω 120 Ω SN65HVD230 SN65LBC031 UC5350 HP E3516A 5-V Power Supply HP E3516A 3.3-V Power Supply Figure 40. 3.3-V/5-V CAN Transceiver Test Bed 24 Competitor X250 Submit Documentation Feedback SN65HVD230 SN65HVD231 SN65HVD232 www.ti.com SLOS346H – MARCH 2001 – REVISED JULY 2006 APPLICATION INFORMATION (continued) Driver Input CAN Bus Receiver Output Figure 41. The HVD230's Input, CAN Bus, and X250's RXD Output Waveforms Figure 41 displays the HVD230's input signal, the CAN bus, and the competitor X250's receiver output waveforms. The input waveform from the Tektronix HFS-9003 Pattern Generator in Figure 40 to the HVD230 is a 250-kbps pulse for this test. The circuit is monitored with Tektronix P6243, 1-GHz single-ended probes in order to display the CAN dominant and recessive bus states. Figure 41 displays the 250-kbps pulse input waveform to the HVD230 on channel 1. Channels 2 and 3 display CANH and CANL respectively, with their recessive bus states overlaying each other to clearly display the dominant and recessive CAN bus states. Channel 4 is the receiver output waveform of the competitor X250. Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65HVD230D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD230DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD230DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD230DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD231D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD231DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD231DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD231DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD232D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD232DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD232DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD232DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2006 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 20-Jun-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65HVD230DR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1 SN65HVD231DR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1 SN65HVD232DR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65HVD230DR D 8 FMX 342.9 336.6 20.64 SN65HVD231DR D 8 FMX 342.9 336.6 20.64 SN65HVD232DR D 8 FMX 342.9 336.6 20.64 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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