SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 D D D SN54ALS374A, SN54AS374 . . . J PACKAGE SN74ALS374A, SN74AS374 . . . DW OR N PACKAGE (TOP VIEW) D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs Full Parallel Access for Loading Buffered Control Inputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 1D 1Q SN54ALS374A, SN54AS374 . . . FK PACKAGE (TOP VIEW) On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. 2D 2Q 3Q 3D 4D 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. 3 OE VCC 8Q D OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 logic symbol† OE CLK 1 logic diagram (positive logic) OE EN 11 CLK C1 1 11 C1 1D 2D 3D 4D 5D 6D 7D 8D 3 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 1D 3 2 1Q 1D 2Q 3Q 4Q To Seven Other Channels 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions SN54ALS374A 2 SN74ALS374A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current –1 –2.6 mA IOL TA Low-level output current 24 mA 70 °C High-level input voltage 2 2 12 Operating free-air temperature –55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 0 V V SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –0.4 mA 5V VCC = 4 4.5 IOH = –1 mA IOH = –2.6 mA VOL VCC = 4 4.5 5V IOL = 12 mA IOL = 24 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VOH ICC SN54ALS374A TYP† MAX TEST CONDITIONS VCC = 5.5 V MIN SN74ALS374A TYP† MAX MIN –1.5 VCC–2 2.4 UNIT –1.5 V VCC–2 V 3.3 2.4 0.25 –20 0.4 3.2 0.25 0.4 0.35 0.5 V 20 20 µA –20 –20 µA 0.1 0.1 mA 20 20 µA –0.2 –0.2 mA –112 mA –112 –30 Outputs high 11 20 11 19 Outputs low 19 28 19 28 mA Outputs disabled 20 31 20 31 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended operating free-air temperature range (unless otherwise noted) SN54ALS374A MIN fclock tw Clock frequency Pulse duration CLK high or low tsu th Setup time Data before CLK↑ Hold time Data after CLK↑ MAX SN74ALS374A MIN 30 MAX 35 UNIT MHz 16.5 14 ns 10 10 ns 4 0 ns switching characteristics over recommended operating conditions (unless otherwise noted (see Figure 3) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) SN54ALS374A MIN MAX 30 CLK Q OE Q OE Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS374A MIN MAX 35 UNIT MHz 3 14 3 12 5 17 5 16 3 18 3 17 5 21 5 18 1 11 1 10 2 19 2 18 ns ns ns 3 SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 recommended operating conditions SN54AS374 SN74AS374 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current –12 –15 mA IOL TA Low-level output current 32 48 mA 70 °C High-level input voltage 2 Operating free-air temperature 2 –55 125 V V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –2 mA VCC = 4 4.5 5V IOH = –12 mA IOH = –15 mA VOL VCC = 4 4.5 5V IOL = 32 mA IOL = 48 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VOH IIL OE, CLK Data IO‡ ICC VCC = 5 5.5 5V V, VI = 0 0.4 4V VCC = 5.5 V, VO = 2.25 V Outputs high VCC = 5.5 V SN54AS374 TYP† MAX MIN SN74AS374 TYP† MAX MIN –1.2 VCC–2 2.4 –1.2 UNIT V VCC–2 V 3.2 2.4 0.29 3.3 0.5 0.34 –30 0.5 V µA 50 50 –50 –50 µA 0.1 0.1 mA µA 20 20 –0.5 –0.5 –3 –2 –112 –30 –112 77 120 77 120 Outputs low 84 128 84 128 Outputs disabled 84 128 84 128 mA mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended operating free-air temperature range (unless otherwise noted) SN54AS374 MIN fclock Clock frequency tw Pulse duration tsu th SN74AS374 MIN 100* CLK high MAX 125 UNIT MHz 5.5* 4 CLK low 3* 3 Setup time Data before CLK↑ 3* 2 ns Hold time Data after CLK↑ 3* 2 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. 4 MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 3) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ FROM (INPUT) TO (OUTPUT) SN54AS374 MIN MAX 100* CLK Q OE Q OE Q tPLZ * On products compliant to MIL-PRF-38535, this parameter is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AS374 MIN MAX 125 UNIT MHz 3 11 3 8 4 11.5 4 9 2 7 2 6 3 11 3 10 2 10 2 6 2 7 2 6 ns ns ns 5 SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 APPLICATION INFORMATION Four SN54ALS374A, SN74ALS374A, or ’AS374 EN C 8 8 ’ALS139 A Output-Enable Select B G X/Y 1 2 0 EN 1 C 2 EN 8 8 3 A Input Clock Select B EN G C 8 Clock 8 EN C 8 8 Input Figure 1. Expandable 4-Word by 8-Bit General File Register 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8 8 Output SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 APPLICATION INFORMATION SN54ALS374A, SN74ALS374A, or ’AS374 Output Enable 1 EN Clock 1 C1 1D Bidirectional Data Bus 1 Bidirectional Data Bus 2 SN54ALS374A, SN74ALS374A, or ’AS374 EN Output Enable 2 Clock 2 C1 1D Clock 1 H Bus-Exchange Clock Clock 2 H Clock Circuit for Bus Exchange Figure 2. Bidirectional Bus Driver POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V VCC S1 500 Ω From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) CL = 50 pF (see Note A) 500 Ω 3.5 V Timing Input 500 Ω 3.5 V High-Level Pulse 1.3 V Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS 500 Ω From Output Under Test CL = 50 pF (see Note A) Test Point 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control 1.3 V 1.3 V 3.5 V 0.3 V tPZL 1.3 V Input tPLZ 1.3 V 0.3 V ≈3.5 V Waveform 1 S1 Closed (see Note B) 1.3 V tPZH Waveform 2 S1 Open (see Note B) tPLH VOL + 0.3 V VOL In-Phase Output tPHZ 1.3 V VOH VOH – 0.3 V ≈0 V 1.3 V tPHL Out-of-Phase Output (see Note C) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS tPHL VOH 1.3 V VOL tPLH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 3. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated