OPA561 SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 High-Current, High-Speed OPERATIONAL AMPLIFIER FEATURES D 1.2A OUTPUT CURRENT D 12Vp-p OUTPUT VOLTAGE D WIDE POWER RANGE: D D D D D D − Single Supply: +7V to +15V − Dual Supply: ±3.5V to ±7.5V FULLY PROTECTED: − Thermal Shutdown − Adjustable Current Limit OUTPUT DISABLE CONTROL 17MHz GAIN-BANDWIDTH PRODUCT 50V/µs SLEW RATE 1MHz FULL-POWER BANDWIDTH THERMALLY ENHANCED HTSSOP-20 PowerPAD PACKAGE APPLICATIONS D D D D D D POWER-LINE COMMUNICATIONS VALVE-ACCUATOR DRIVERS POWER SUPPLIES TEST EQUIPMENT TEC DRIVERS LASER DIODE DRIVERS DESCRIPTION The OPA561 is a low-cost, high-current operational amplifier capable of driving up to 1.2A pulses into reactive loads. This monolithic integrated circuit provides high reliability in demanding line-carrier communications, laser diode drivers, and motor control applications. The high slew rate provides 1MHz full-power bandwidth and excellent linearity. The OPA561 operates from either a single supply in the range of 7V to 15V or dual power supplies of ±3.5V to ±7.5V for design flexibility. In single-supply operation, the input common-mode range extends below ground. At maximum output current, a wide output swing provides a 12Vp-p capability with a nominal 15V supply. The OPA561 is internally protected against overtemperature conditions and current overloads. In addition, the OPA561 is designed to provide an accurate, userselected, current limit. The current limit can be adjusted from 0.2A to 1.2A with a low-power resistor/potentiometer or DAC (Digital-to-Analog Converter). The high-speed characteristics of the current control loop provide accuracy even under pulsed load conditions. The Enable/Status (E/S) pin performs two functions: it can be monitored to determine if the device is in thermal shutdown (active LOW), and it can also be forced LOW to disable the output, disconnecting the load. The OPA561 is available in the miniature, HTSSOP-20 PowerPAD power package. This surface-mount package is thermally enhanced and has a very low thermal resistance. Operation is specified over the extended industrial temperature range, −40_C to +125_C. NOTE: Pins 1, 10, and 11-20 are not connected. PowerPAD must be connected to V−. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas instruments Incorporated. All other trademarks are the property of their respective owners. Copyright 2001-2004, Texas Instruments Incorporated ! ! www.ti.com "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, V− to V+ . . . . . . Input Voltage Range . . . . . . . . . Input Shutdown Voltage . . . . . . . Operating Temperature . . . . . . . Storage Temperature . . . . . . . . Junction Temperature . . . . . . . . Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 16V . . . . . . . (V−) − 0.4V to (V+) + 0.5V . . . . . . . (V−) − 0.4V to (V−) + 5.0V . . . . . . . . . . . . . −40°C to +125°C . . . . . . . . . . . . . −65°C to +150°C . . . . . . . . . . . . . . . . . . . 150°C . . . . . . . . . . . . . . . . . . . 300°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING HTSSOP-20 PWP −40°C to +125°C OPA561 OPA561PWP ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA561PWP Rails, 70 OPA561PWP/2K Tape and Reel, 2000 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. ELECTRICAL CHARACTERISTICS BOLDFACE limits apply over the specified temperature range, TA = −40°C to +125°C. At TCASE = +25°C, VS = 15V, load connected to VS/2, and E/S enabled, unless otherwise noted. OPA561 PARAMETER OFFSET VOLTAGE Input Offset Voltage vs Temperature vs Power Supply TYP MAX UNITS ±20 VCM = 0V, VS = 7V to 16V ±1 ±50 25 150 mV µV/°C µV/V 100 100 pA pA CONDITIONS VOS dVOS/dT PSRR MIN VS = 12V VCM = 0V INPUT BIAS CURRENT(1) Input Bias Current Input Offset Current IB IOS VCM = 0V VCM = 0V 10 10 NOISE Input Voltage Noise Density en f = 1kHz f = 10kHz f = 100kHz f = 1kHz 83 32 14 4 Current Noise INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio in VCM CMRR Linear Operation VS = 15V, VCM = (V−) − 0.1V to (V+) − 3V (V−) − 0.1 70 INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Full-Power Bandwidth Settling Time: ±0.1% Total Harmonic Distortion + Noise AOL VO = 10Vp−p, RL = 5Ω GBW SR RL = 5Ω G = 1, 10V Step, RL = 5Ω G = +2, VOUT = 10Vp-p G = −1, 10V Step f = 1kHz, RL = 5Ω, G = +2, VO = 10Vp-p f = 1MHz THD+N (1) High-speed test at TJ = +25°C. (2) See text for more information on current limit accuracy. (3) Transient load transition time must be ≥ 200ns. (4) 402kΩ pull-up resistor to V+ can be used to permanently enable the OPA561. 2 80 nV/√Hz nV/√Hz nV/√Hz fA/√Hz 80 (V+) − 3 V dB 1.8 S 1011 || 10 1.8 S 1011 || 18.5 Ω || pF Ω || pF 100 dB 17 50 1 1 0.02 3 MHz V/µs MHz µs % % "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range, TA = −40°C to +125°C. At TCASE = +25°C, VS = 15V, load connected to VS/2, and E/S enabled, unless otherwise noted. OPA561 PARAMETER OUTPUT Voltage Output, Positive Negative Positive Negative Maximum Continuous Current Output, dc Output Impedance Ouput Current Limit Range Current Limit Tolerance(2) ZO OUTPUT ENABLE/STATUS AND FLAG PINS Shutdown Input Mode VE/S HIGH (output enabled)(4) VE/S LOW (output disabled) IE/S HIGH (output enabled) IE/S LOW (output disabled) Output Disable Time Output Enable Time Thermal Shutdown Status Normal Operation Thermally Shutdown Current Limit Status Normal Operation Current Limit Flagged Junction Temperature at Shutdown Reset Temperature from Shutdown TEMPERATURE RANGE Specified Junction Temperature Range Storage Range Thermal Resistance HTSSOP-20 PowerPAD qJA qJA MIN TYP IO = 0.5A IO = −0.5A IO = 1A IO = −1A (V+) − 1 (V−) + 1 (V+) − 1.5 (V−) + 1.5 (V+) − 0.7 (V−) + 0.7 (V+) − 1.2 (V−) + 1.2 1.2 0.05 ±0.2 to ±1.2 ±50 10 50 V V V V A Ω A mA % % 10 140 MΩ pF G = +2, f = 100kHz RCL = 2kΩ (ILIM = ±1A) Comparing Positive and Negative Limits V = 5V Pulse (200ns tr), G = +2 Asymmetry Current Limit Overshoot(3) Output Disabled Output Resistance Output Capacitance POWER SUPPLY Specified Voltage Operating Voltage Range, (V+) − (V−) Quiescent Current vs Temperature Quiescent Current in Shutdown Mode CONDITIONS E/S Pin Open or Forced HIGH E/S Pin Forced LOW E/S Pin Indicates HIGH E/S Pin Indicates LOW (V−) + 2 (V−) − 0.4 Sourcing 20µA (V−) + 2 (V−) + 5 (V−) + 0.8 20 0.1 50 3 (V−) + 0.8 Sourcing 20µA (V−) + 0.8 (V−) + 2 +160 +140 VS 15 7 IQ ILIM Connected to V−, IQ = 0 50 60 ILIM Connected to V− −40 −65 qJC MAX 2oz. Trace and 9in2 Copper Pad with Solder Without Heatsink 1.4 32 100 UNITS V V µA µA ns µs V V V V °C °C 16 60 70 V V mA mA 250 µA +125 +150 °C °C °C/W °C/W °C/W (1) High-speed test at TJ = +25°C. (2) See text for more information on current limit accuracy. (3) Transient load transition time must be ≥ 200ns. (4) 402kΩ pull-up resistor to V+ can be used to permanently enable the OPA561. 3 "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS At TCASE = +25°C, VS = 15V, and E/S enabled, unless otherwise noted. 4 "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) At TCASE = +25°C, VS = 15V, and E/S enabled, unless otherwise noted. 5 "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) At TCASE = +25°C, VS = 15V, and enabled, unless otherwise noted. 6 "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 APPLICATIONS INFORMATION Figure 1 shows the OPA561 connected as a basic noninverting amplifier. However, the OPA561 can be used in virtually any op amp configuration. Power-supply terminals should be bypassed with low series impedance capacitors. The technique of using a ceramic and tantalum type in parallel is recommended. Power-supply wiring should have low series impedance. voltage). The OPA561 employs a patented circuit technique to achieve an accurate and stable current limit. The output current limit has an accuracy of up to 5% on the 1A current limit. Due to internal matching limitations, the positive and negative current limits can be slightly different. However, the values are typically within 10% of each other. Setting the Current Limit Leaving the ILIM pin open could damage the part. Connecting ILIM directly to V− programs the maximum output current limit, typically 1.2A. The simplest method for adjusting the current limit (ILIM) uses a resistor or potentiometer connected between the ILIM pin and V− according to Equation 1: I LIM + ǒR CL Ǔ 1.2V ) 10kW 10, 000 (1) This external resistor determines a small internal current which sets the desired output current limit. Alternatively, the output current limit can be set by applying a voltage to the ILIM pin. Figure 2 shows a simplified schematic of the OPA561’s current limit. Figure 1. Basic Circuit Connections POWER SUPPLIES The OPA561 operates from single (+7V to +15V) or dual (±3.5V to ±7.5V) supplies with excellent performance. Power-supply voltages do not need to be equal. For example, the positive supply could be set to 10V with the negative supply at –5V, or vice-versa. Most behaviors remain unchanged throughout the operating voltage range. Parameters that vary significantly with operating voltage are shown in the typical characteristics. ILIM + ǒ 1.2V R CL)10kW Ǔ @ 10, 000 Max IO = ILIM ADJUSTABLE CURRENT LIMIT The OPA561’s accurate, user-defined, current limit can be set from 0.2A to 1.2A by controlling the input to the ILIM pin. Unlike other designs that use a power resistor in series with the output current path, the OPA561 senses the load internally. This allows the current limit to be set with low-power components. In contrast, other designs require one or two expensive power resistors that can handle the full output current (1.2A in this case). Current Limit Accuracy Figure 2. Adjustable Current Limit—Resistor Method Separate circuits monitor the positive and negative currents. Each output is compared to a single internal reference that is set by the external current limit resistor (or 7 "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 ENABLE/STATUS (E/S) PIN The Enable/Status Pin provides two unique functions: 1) output disable by forcing the pin LOW and 2) thermal shutdown indication by monitoring the voltage level at the pin. One or both of these functions can be utilized on the same device. For normal operation (output enabled), the E/S pin must be pulled HIGH (at least 2V above V−). A small value capacitor connected between the E/S pin and V− may be appropriate for noisy applications. To enable the OPA561 permanently, the E/S pin can be tied to V+ through a 402kΩ pull-up resistor. Output Disable The shutdown pin is referenced to the negative supply (V−). Therefore, shutdown operation is slightly different in single-supply and dual-supply applications. In single-supply operation, V− typically equals common ground. Therefore, the shutdown logic signal and the OPA561’s shutdown pin are referenced to the same potential. In this configuration, the logic pin and the OPA561 enable can simply be tied together. Shutdown occurs for voltage levels of < 0.8V. The OPA561 is enabled at logic levels > 2V. In dual-supply operation, the logic pin is still referenced to a logic ground. However, the shutdown pin of the OPA561 is still referenced to V−. To shutdown the OPA561, the voltage level of the logic signal needs to be level shifted using an optocoupler, as shown in Figure 3. (a) +5V (b) HCT or TTL In V+ 402kΩ OPA561 E/S (1) 4N38 V− (b) NOTE: (1) Optional—may be required to limit leakage current of octocoupler at high temperatures. Figure 3. Shutdown Configuration for Dual Supplies To disable the output, the E/S pin is pulled LOW, no greater than 0.8V above V−. This function can be used to conserve power during idle periods. The typical time required to shut 8 Ensuring Microcontroller Compatibility Not all microcontrollers output the same logic state after power-up or reset. 8051-type microcontrollers, for example, output logic HIGH levels on their ports while other models power up with logic LOW levels after reset. In configuration (a) as shown in Figure 3, the shutdown signal is applied on the cathode side of the photodiode within the optocoupler. A high logic level causes the OPA561 to be enabled, and a low logic level shuts the OPA561 down. In configuration (b) of Figure 3, with the logic signal applied on the anode side, a high level causes the OPA561 to shutdown and low level enables the op amp. OVER-CURRENT FLAG The OPA561 features an over-current status flag (CLS, Pin 9) that can be monitored to see if the load exceeds the current limit. The output signal of the over current limit flag is compatible to standard logic. The CLS signal is referenced to V−. A voltage level of less than (V−) + 0.8V indicates normal operation and a level of greater than (V−) + 2 indicates that the OPA561 is in current limit. The flag is HIGH as long as the output of the OPA561 is in current limit. At very low signal frequencies, typically < 1kHz, both the upper (sourcing current) and lower current limit (sinking current) are monitored. At frequencies > 1kHz, due to internal circuit limitations, the flag output signal for the upper current limit becomes delayed and shortened. The flag signal for the lower current limit is unaffected by this behavior. As the signal frequency increases further, only the lower current limit (sinking current) is output on pin 9. OUTPUT STAGE COMPENSATION Optocoupler (a) HCT or TTL In down the output is 50ns. To return the output to an enabled state, the E/S pin should be pulled to at least 2.0V above V−. Typically, the output is enabled within 3µs. It should be noted that pulling the E/S pin HIGH (output enabled) does not disable the internal thermal shutdown. The complex load impedances common in power op amp applications can cause output stage instability. For normal operation, output compensation circuitry is typically not required. However, if the OPA561 is intended to be driven into current limit, an R/C network (snubber) may be required. A snubber circuit may also enhance stability when driving large capacitive loads (> 1000pF) or inductive loads (motors, loads separated from the amplifier by long cables). Typically, 3Ω to 10Ω in series with 0.01µF to 0.1µF is adequate. Some variations in circuit value may be required with certain loads. "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 OUTPUT PROTECTION Reactive and EMF-generation loads can return load current to the amplifier, causing the output voltage to exceed the power-supply voltage. This damaging condition can be avoided with clamp diodes from the output terminal to the power supplies, as shown in Figure 4. Schottky rectifier diodes with a 3A or greater continuous rating are recommended. maximum expected ambient condition of your application. This produces a junction temperature of +125°C at the maximum expected ambient condition. The internal protection circuitry of the OPA561 was designed to protect against overload conditions; it was not intended to replace proper heatsinking. Continuously running the OPA561 into thermal shutdown can degrade reliability. The E/S pin can be monitored to determine if shutdown has occurred. During normal operation the voltage on the E/S pin is typically above (V−) + 2V. During shutdown, the voltage drops to less than (V−) + 0.8V. POWER DISSIPATION Power dissipation depends on power supply, signal, and load conditions. For DC signals, power dissipation is equal to the product of output current times the voltage across the conducting output transistor. Dissipation with ac signals is lower. Application Bulletin AB−039 (SBOA022) explains how to calculate or measure power dissipation with unusual signals and loads, and can be dowloaded from www.ti.com. HEATSINK AREA The relationship between thermal resistance and power dissipation can be expressed as: where: TJ = Junction Temperature (°C) TA = Ambient Temperature (°C) Figure 4. Output Protection Diode THERMAL PROTECTION The OPA561 has thermal sensing circuitry that helps protect the amplifier from exceeding temperature limits. Power dissipated in the OPA561 will cause the junction temperature to rise. Internal thermal shutdown circuitry shuts down the output when the die temperature reaches approximately 160°C, resetting when the die has cooled to 140°C. Depending on load and signal conditions, the thermal protection circuit may cycle on and off. This limits the dissipation of the amplifier, but may have an undesirable effect on the load. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable, long-term, continuous operation, junction temperature should be limited to +125°C, maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered. Use worst-case loading and signal conditions. For good, long-term reliability, thermal protection should trigger more than 35°C above the qJA = Junction-to-Ambient Thermal Resistance (°C/W) PD = Power Dissipation (W) To appropriately determine required heatsink area, required power dissipation should be calculated and the relationship between power dissipation and thermal resistance should be considered to minimize shutdown conditions and allow for proper long-term operation (junction temperature of +125°C). Once the heatsink area has been selected, worst-case load conditions should be tested to ensure proper thermal protection. For applications with limited board size, refer to Figure 5 for the approximate thermal resistance relative to heatsink area. Increasing heatsink area beyond 2in2 provides little improvement in thermal resistance. To achieve the 32°C/W stated in the Electrical Characteristics, a copper plane size of 9in2 was used. The HTSSOP-20 PowerPAD package is well suited for continuous power levels from 2W to 4W, depending on ambient temperature and heatsink area. Higher power levels may be achieved in applications with a low on/off duty cycle, such as remote meter reading. 9 "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 Soldering the PowerPAD to the PCB is always recommended, even with applications that have low power dissipation. It provides the necessary connection between the leadframe die and the PCB. The PowerPAD should be connected to the most negative supply of the device. PowerPAD Assembly Process 1. Prepare the PCB with a top side etch pattern, as shown in Figure 7. There should be etch for the leads as well as etch for the thermal land. 2. Place the recommended number of holes (or thermal vias) in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept small so that solder wicking through the holes is not a problem during reflow. The recommended number of holes for the HTSSOP-20 PowerPAD package is eight, as shown in Figure 7. 3. It is recommended, but not required, to place a small number of the holes under the package and outside the thermal pad area. These holes provide additional heat path between the copper land and ground plane and are 25 mils in diameter. They may be larger because they are not in the area to be soldered, so wicking is not a problem. This is illustrated in Figure 7. Figure 5. Thermal Resistance vs Circuit Board Copper Area AMPLIFIER MOUNTING What is PowerPAD? The OPA561 uses the HTSSOP-20 PowerPAD package, a thermally enhanced, standard size IC package designed to eliminate the use of bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard PCB assembly techniques, and can be removed and replaced using standard repair procedures. The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of the IC, as shown in Figure 6. This provides an extremely low thermal resistance (qJC ) path between the die and the exterior of the package. The thermal pad on the bottom of the IC must be soldered directly to the PCB, using the PCB as a heatsink. In addition, through the use of thermal vias, the thermal pad can be directly connected to a ground plane or special heatsink structure designed into the PCB. Figure 7. PWP-20 PowerPAD PCB Etch and Via Pattern Figure 6. Section View of a PowerPAD Package 10 4. Connect all holes, including those within the thermal pad area and outside the pad area, to the internal ground plane or other internal copper plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology, see Figure 8. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated through hole. Figure 8. Via Connection 6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area. The thermal pad area should leave the 13 mil holes exposed. The larger 25 mil holes outside the thermal pad area should be covered with solder mask. 7. Apply solder paste to the exposed thermal pad area and all of the package terminals. 8. With these preparatory steps in place, the PowerPAD IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For detailed information on the PowerPAD package including thermal modeling considerations and repair procedures, please see Technical Brief SLMA002, PowerPAD Thermally Enhanced Package, available at www.ti.com. LAYOUT GUIDELINES The OPA561 is a high-speed power amplifier that requires proper layout for best performance. Figure 9 shows an example of proper layout. Keep power-supply leads as short as possible. This will keep inductance low and resistive losses at a minimum. A minimum 18 gauge wire thickness is recommended for power-supply leads. The wire length should be < 8 inches. Figure 9. OPA561 Example Layout Proper power-supply bypassing with low ESR capacitors is essential to achieve good performance. A parallel combination of small ceramic (around 100nF) and bigger (47µF) non-ceramic bypass capacitors will provide low impedance over a wide frequency range. Bypass capacitors should be placed as close as practical to the power-supply pins of the OPA561. PCB traces conducting high currents, such as from output to load or from the power-supply connector to the power-supply pins of the OPA561 should be kept as wide and as short as possible. This will keep inductance low and also resistive losses to a minimum. The eight holes in the landing pattern for the OPA561 are for the thermal vias that connect the PowerPAD of the OPA561 to the heatsink area on the printed circuit board. The additional four larger vias further enhance the heat conduction into the heatsink area. All traces conducting high currents are very wide for lowest inductance and minimal resistive losses. Note that the negative supply (−VS) pin on the OPA561 is connected through the PowerPAD. This allows for maximum trace width for VOUT and the positive power supply (+VS). 11 "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 APPLICATIONS CIRCUITS The high output current and low supply of the OPA561 makes it a good candidate for driving laser diodes and thermo electric coolers. Figure 10 shows the OPA561 configured as a laser diode driver. Figure 11. Programmable Power Supply Typically such a system consists of a microcontroller, a modem IC and the power line interface circuitry. See Figure 12 for the half-duplex power line communication system. Figure 10. Laser Diode Driver PROGRAMMABLE POWER SUPPLY Figure 11 shows the OPA561 configured with the MSP430, REF3030, and DAC7513 as a space-saving, low-cost, programmable power-supply solution. This solution features low-voltage operation, small-size packages, (DAC7513 in SOT23-8, REF3030 in SOT23-3) and low cost (under $10 for complete solution). POWER-LINE COMMUNICATION MODEM The OPA561 is well suited to drive AC power lines for low-speed communications applications. It provides an easily implemented, reliable solution that is superior to discrete power transistor circuits. Advantages include: 1. Fully Integrated Solution 2. Integrated Shutdown Circuitry for Send-and-Receive Switching 3. Thermal Shutdown 4. Adjustable Current Limit 5. Shutdown Flag 6. Power Savings 7. Small PowerPAD package 12 It uses a synchronous FSK-modem, capable of 600 and 1200-baud data rates, and supports two different FSK channels in the 60kHz to 80kHz range. A microcontroller such as the MSP430 is used to control the modem IC. The OPA561 analog interface circuitry drives the FSK modem signals on the AC power line. It filters the transmit signal (ATO) from the ST7536 to suppress the 2nd-harmonic distortion of the transmit signal. It also amplifies the ATO signal and provides the very low output impedance necessary to properly drive the line. The impedance of a typical power line at 70kHz ranges from 1Ω to 100Ω. The OPA561 is ideal for this type of load. The transformer provides isolation and additional filtering. C9 prevents 50/60Hz current from flowing in the transformer. This capacitor must be chosen carefully for proper voltage rating and safety characteristics. The receive input signal is amplified (G = 100) and applied to the modem IC. The OPA561 is disabled in receive mode to avoid loading the line. "#$ www.ti.com SBOS206D − DECEMBER 2001 − REVISED OCTOBER 2004 Figure 12. Power Line Communication Driver 13 PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY OPA561PWP ACTIVE HTSSOP PWP 20 78 OPA561PWP/2K ACTIVE HTSSOP PWP 20 2000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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