Revised November 1999 74AC240 • 74ACT240 Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The AC/ACT240 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. ■ ICC and IOZ reduced by 50% ■ Inverting 3-STATE outputs drive bus lines or buffer memory address registers ■ Outputs source/sink 24 mA ■ ACT240 has TTL-compatible inputs Ordering Code: Order Number Package Number 74AC240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC240SJ 74AC240MTC 74AC240PC MTC20 Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACT240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT240MTC 74ACT240PC MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions IEEE/IEC Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs Truth Tables Inputs OE1 Connection Diagram Outputs In (Pins 12, 14, 16, 18) L L H L H L H X Z Inputs Outputs OE2 In (Pins 3, 5, 7, 9) L L H L H L H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009941 www.fairchildsemi.com 74AC240 • 74ACT240 Octal Buffer/Line Driver with 3-STATE Outputs November 1988 74AC240 • 74ACT240 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC ) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V VO = VCC + 0.5V +20 mA AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V ±50 mA ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V ±50 mA −65°C to +150°C Junction Temperature (TJ) PDIP 125 mV/ns Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current Storage Temperature (TSTG) 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) DC Output Source per Output Pin (ICC or IGND) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. 140°C DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH TA = +25°C VCC (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA VI = VCC, GND Leakage Current 5.5 ±0.25 ±2.5 µA VI = VCC, GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC (Note 4) Maximum Quiescent Supply Current 5.5 40.0 µA VIN = VCC or GND V IOUT = 50 µA VIN = VIL or VIH IIN (Note 4) Maximum Input Leakage Current IOZ Maximum 3-STATE IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) VI (OE) = VIL, VIH VO = VCC, GND 4.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com 2 Symbol VIH VIL VOH Parameter Minimum HIGH Level TA = +25°C VCC (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 5) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current ICCT Maximum IOL = 24 mA (Note 5) VI = VCC, GND VI = VIL, VIH VO = VCC, GND 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA ICC Maximum Quiescent ICC/Input Supply Current 5.5 0.6 5.5 4.0 40.0 µA VOHD = 3.85V Min VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74AC240 • 74ACT240 DC Electrical Characteristics for ACT 74AC240 • 74ACT240 AC Electrical Characteristics Symbol tPLH tPHL tPZH tPZL Parameter CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Propagation Delay 3.3 1.5 6.0 8.0 1.0 9.0 Data to Output 5.0 1.5 4.5 6.5 1.0 7.0 Propagation Delay 3.3 1.5 5.5 8.0 1.0 8.5 Data to Output 5.0 1.5 4.5 6.0 1.0 6.5 Output Enable Time 3.3 1.5 6.0 10.5 1.0 11.0 5.0 1.5 5.0 7.0 1.0 8.0 3.3 1.5 7.0 10.0 1.0 11.0 5.0 1.5 5.5 8.0 1.0 8.5 Output Disable Time tPLZ TA = +25°C (V) (Note 7) Output Enable Time tPHZ VCC Output Disable Time Units Max 3.3 1.5 7.0 10.0 1.0 10.5 5.0 1.5 6.5 9.0 1.0 9.5 3.3 1.5 7.5 10.5 1.0 11.5 5.0 1.5 6.5 9.0 1.0 9.5 ns ns ns ns ns ns Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics Symbol tPLH Parameter Propagation Delay Data to Output tPHL Propagation Delay Data to Output VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 8) Min Typ Max Min Max 5.0 1.5 6.0 8.5 1.5 9.5 ns 5.0 1.5 5.5 7.5 1.5 8.5 ns ns tPZH Output Enable Time 5.0 1.5 7.0 8.5 1.0 9.5 tPZL Output Enable Time 5.0 2.0 7.0 9.5 1.5 10.5 ns tPHZ Output Disable Time 5.0 2.0 8.0 9.5 2.0 10.5 ns tPLZ Output Disable Time 5.0 2.5 6.5 10.0 2.0 10.5 ns Note 8: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 45.0 pF VCC = 5.0V www.fairchildsemi.com 4 Conditions 74AC240 • 74ACT240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 5 www.fairchildsemi.com 74AC240 • 74ACT240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74AC240 • 74ACT240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74AC240 • 74ACT240 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8