Revised January 2000 74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The AC/ACT10 contains three, 3-input NAND gates. ■ ICC reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC10SC 74AC10SJ 74AC10MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC10PC N14A 74ACT10SC M14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 74ACT10PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names © 2000 Fairchild Semiconductor Corporation Description A n , B n , Cn Inputs On Outputs DS009915 www.fairchildsemi.com 74AC10 • 74ACT10 Triple 3-Input NAND Gate November 1988 74AC10 • 74ACT10 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) −0.5V to VCC + 0.5V AC Devices VIN from 30% to 70% of VCC ± 50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Source or Sink Current (IO) AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH VIL VOH Parameter TA = +25°C VCC TA = −40°C to +85°C (V) Typ Guaranteed Limits Minimum HIGH Level 3.0 1.5 2.1 2.1 Input Voltage 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 Units Conditions VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V V IOUT = −50 µA VOUT = 0.1V VIN = VILor VIH VOL IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA V IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC IIN Maximum Input (Note 4) Leakage Current IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent (Note 4) Supply Current 20.0 µA 5.5 2.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com 2 or GND VIN = VCC or GND Symbol Minimum HIGH Level VIH VIL VOH TA = +25°C VCC Parameter (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 Units 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VILor VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 V IOH= −24 mA IOH = −24 mA (Note 5) Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA VI = VCC, GND V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current ICCT Maximum IOL = 24 mA (Note 5) 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA ICC Maximum Quiescent 5.5 ICC/Input 0.6 5.5 Supply Current 4.0 40.0 µA VOHD = 3.85V Min VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol tPLH Parameter Propagation Delay tPHL Propagation Delay VCC TA = +25°C TA = −40°C to +85°C (V) CL = 50 pF CL = 50 pF (Note 7) Min Typ Max Min Max 3.3 1.5 6.0 9.5 1.0 10.5 5.0 1.5 4.5 7.0 1.0 8.0 3.3 1.5 5.5 8.5 1.0 10.0 5.0 1.5 4.0 6.0 1.0 6.5 Units ns ns Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol Parameter VCC TA = +25°C TA = −40°C to +85°C (V) CL = 50 pF CL = 50 pF Units (Note 8) Min Typ Max Min Max tPLH Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns tPHL Propagation Delay 5.0 1.0 6.5 9.0 1.0 9.5 ns Note 8: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 25.0 pF VCC = 5.0V 3 Conditions www.fairchildsemi.com 74AC10 • 74ACT10 DC Electrical Characteristics for ACT 74AC10 • 74ACT10 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A www.fairchildsemi.com 4 74AC10 • 74ACT10 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74AC10 • 74ACT10 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 74AC10 • 74ACT10 Triple 3-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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