FAIRCHILD 74LCX821WM

Revised March 2001
74LCX821
Low Voltage 10-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
General Description
Features
The LCX821 consists of ten D-type Flip-Flops with
3-STATE outputs for bus organized system applications.
The device is designed for low voltage (2.5V or 3.3V) VCC
applications with capability of interfacing to a 5V signal
environment.
■ 5V tolerant inputs and outputs
The LCX821 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining
CMOS low power dissipation.
■ Supports live insertion/withdrawal (Note 1)
■ 2.3V–3.6V VCC specifications provided
■ 7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
■ Power-down high impedance inputs and outputs
■ ±24 mA output drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human Body Model > 2000V
Machine Model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package Number
Package Description
74LCX821WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LCX821MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX821MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2001 Fairchild Semiconductor Corporation
DS012635
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74LCX821 Low Voltage 10-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
January 1996
74LCX821
Pin Descriptions
Pin Names
Function Table
Description
Inputs
Internal
Outputs
OE CLK D
Q
On
L
NC
Z
Hold
H
NC
Z
Hold
Load
Function
D0–D9
Data Inputs
CLK
Clock Input
H
H
OE
Output Enable Input
H
H
O0–O9
3-STATE Latch Outputs
H
H
L
L
L
L
Z
H
H
Z
Load
L
L
L
Data Available
H
H
H
Data Available
L
H
L
NC
NC
No Change in Data
L
H
H
NC
NC
No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impendance
= LOW-to-HIGH Transition
NC = No Change
Functional Description
requirements on the LOW-to-HIGH Clock (CLK) transition.
With the Output Enable (OE) LOW, the contents of the ten
flip-flops are available at the outputs. When OE is HIGH,
the outputs go to the high impedance state. Operation of
the OE input does not affect the state of the flip-flops.
The LCX821 consists of ten edge-triggered flip-flops with
individual D-type inputs with 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The ten flip-flops will store the state of their
individual D inputs that meet the setup and hold time
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Symbol
Parameter
Value
VCC
Supply Voltage
−0.5 to +7.0
VI
DC Input Voltage
−0.5 to +7.0
VO
DC Output Voltage
−0.5 to +7.0
Conditions
Units
V
V
Output in 3-STATE
−0.5 to VCC + 0.5
Output in HIGH or LOW State (Note 3)
IIK
DC Input Diode Current
−50
VI < GND
IOK
DC Output Diode Current
−50
VO < GND
+50
VO > VCC
V
mA
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current per Supply Pin
±100
mA
IGND
DC Ground Current per Ground Pin
±100
mA
TSTG
Storage Temperature
−65 to +150
°C
Recommended Operating Conditions (Note 4)
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH/IOL
Output Current
TA
Free-Air Operating Temperature
∆t/∆V
Input Edge Rate, VIN = 0.8V − 2.0V, VCC = 3.0V
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
0
5.5
HIGH or LOW State
0
VCC
3-STATE
0
5.5
VCC = 3.0V − 3.6V
±24
VCC = 2.7V − 3.0V
±12
VCC = 2.3V − 2.7V
±8
Units
V
V
V
mA
−40
85
°C
0
10
ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
IOH = −100 µA
VCC
TA = −40°C to +85°C
(V)
Min
2.3 − 2.7
1.7
2.7 − 3.6
2.0
Max
V
2.3 − 2.7
0.7
2.7 − 3.6
0.8
2.3 − 3.6
VCC − 0.2
IOH = −8 mA
2.3
1.8
IOH = −12 mA
2.7
2.2
IOH = −18 mA
3.0
2.4
IOH = −24 mA
3.0
2.2
IOL = 100 µA
2.3 − 3.6
Units
V
V
0.2
IOL = 8 mA
2.3
0.6
IOL = 12 mA
2.7
0.4
IOL = 16 mA
3.0
0.4
V
IOL = 24 mA
3.0
0.55
II
Input Leakage Current
0 ≤ VI ≤ 5.5V
2.3 − 3.6
±5.0
µA
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 5.5V
2.3 − 3.6
±5.0
µA
0
10
µA
VI = V IH or VIL
IOFF
Power-Off Leakage Current
VI or VO = 5.5V
3
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74LCX821
Absolute Maximum Ratings(Note 2)
74LCX821
DC Electrical Characteristics
Symbol
(Continued)
Parameter
VCC
Conditions
(V)
ICC
∆ICC
Quiescent Supply Current
Increase in ICC per Input
TA = −40°C to +85°C
Min
Units
Max
VI = VCC or GND
2.3 − 3.6
10
3.6V ≤ VI, VO ≤ 5.5V (Note 5)
2.3 − 3.6
±10
VIH = VCC − 0.6V
2.3 − 3.6
500
µA
µA
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V
CL = 50 pF
CL = 50 pF
CL = 30 pF
Min
Max
Min
Max
Min
Max
1.5
7.0
1.5
7.5
1.5
8.4
CLK to On
1.5
7.0
1.5
7.5
1.5
8.4
Output Enable Time
1.5
7.5
1.5
8.0
1.5
9.8
1.5
7.5
1.5
8.0
1.5
9.8
1.5
6.5
1.5
7.0
1.5
7.8
1.5
6.5
1.5
7.0
1.5
7.8
fMAX
Maximum Clock Frequency
150
tPHL
Propagation Delay
tPLH
tPZL
tPZH
tPLZ
Output Disable Time
tPHZ
Units
MHz
tOSHL
Output to Output Skew
1.0
tOSLH
(Note 6)
1.0
ns
ns
ns
ns
tS
Setup Time, Dn to CLK
2.5
2.5
4.0
ns
tH
Hold Time, Dn to CLK
1.5
1.5
2.0
ns
tW
CLK Pulse Width
3.3
3.3
4.0
ns
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VCC
TA = 25°C
(V)
Typical
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
0.8
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
0.6
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
−0.8
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
−0.6
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Conditions
Units
V
V
Capacitance
Typical
Units
CIN
Symbol
Input Capacitance
Parameter
VCC = Open, VI = 0V or VCC
7
pF
CO
Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8
pF
CPD
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
20
pF
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Conditions
4
74LCX821
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Symbol
VCC
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
Vy
VOH − 0.3V
VOH − 0.3V
VOH − 0.15V
5
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74LCX821
Schematic Diagram Generic for LCX Family
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74LCX821
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
7
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74LCX821 Low Voltage 10-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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