MICROCHIP MCP6273T-E/MS

MCP6271/1R/2/3/4/5
170 µA, 2 MHz Rail-to-Rail Op Amp
Features
Description
•
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The Microchip Technology Inc. MCP6271/1R/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 2 MHz
Gain Bandwidth Product (GBWP) and a 65° Phase
Margin. This family also operates from a single supply
voltage as low as 2.0V, while drawing 170 µA (typ.)
quiescent current. The MCP6271/1R/2/3/4/5 supports
rail-to-rail input and output swing, with a common mode
input voltage range of VDD + 300 mV to VSS – 300 mV.
This family of op amps is designed with Microchip’s
advanced CMOS process.
Gain Bandwidth Product: 2 MHz (typ.)
Supply Current: IQ = 170 µA (typ.)
Supply Voltage: 2.0V to 5.5V
Rail-to-Rail Input/Output
Extended Temperature Range: –40°C to +125°C
Available in Single, Dual and Quad Packages
Parts with Chip Select (CS)
- Single (MCP6273)
- Dual (MCP6275)
The MCP6275 has a Chip Select input (CS) for dual op
amps in an 8-pin package and is manufactured by
cascading two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in low power mode.
Applications
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Automotive
Portable Equipment
Photodiode Amplifier
Analog Filters
Notebooks and PDAs
Battery Powered Systems
The MCP6271/1R/2/3/4/5 family operates over the
Extended Temperature Range of –40°C to +125°C,
with a power supply range of 2.0V to 5.5V.
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Package Types
MCP6271
MCP6271
PDIP, SOIC, MSOP
NC 1
+
7 VDD
VSS 2
6 VOUT
VIN+ 3
4 VIN–
PDIP, SOIC, MSOP
5 VSS
8 CS
7 VDD
SOT-23-6
VOUT 1
4 VIN–
8 VDD
7 VOUTB
- +
VINA+ 3
+ -
VSS 2
6 VOUT VIN+ 3
5 NC
-
5 CS
5 VINB+
MCP6275
PDIP, SOIC, TSSOP
PDIP, SOIC, MSOP
VINA– 2
4 VIN– VINA+ 3
VDD 4
VINB+ 5
© 2006 Microchip Technology Inc.
6 VINB–
MCP6274
6 VDD VOUTA 1
+
+
VOUTA 1
VINA– 2
-
VIN+ 3
MCP6273
PDIP, SOIC, MSOP
NC 1
VSS 4
VDD 2
MCP6272
VSS 4
MCP6273
VIN– 2
VOUT 1
5 NC
VSS 4
VIN+ 3
SOT-23-5
5 VDD
+
VIN+ 3
SOT-23-5
VOUT 1
8 NC
+
VIN– 2
MCP6271R
14 VOUTD VOUTA/VINB+ 1
- + + - 13 VIND–
12 VIND+
11 VSS
VINB– 6
10 VINC+
-+ +- 9 V –
INC
VOUTB 7
8 VOUTC
VINA– 2
VINA+ 3
VSS 4
8 VDD
7 VOUTB
- +
+ -
6 VINB–
5 CS
DS21810E-page 1
MCP6271/1R/2/3/4/5
1.0
ELECTRICAL
CHARACTERISTICS
VDD – VSS ........................................................................7.0V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Current at Analog Input Pins (VIN+ and VIN–) ...............±2 mA
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Absolute Maximum Ratings †
Analog Inputs (VIN+ and VIN–) †† .. VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Junction Temperature (TJ) . .........................................+150°C
ESD Protection On All Pins (HBM/MM) ................ ≥ 4 kV/400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset Voltage
VOS
–3.0
—
+3.0
mV
VCM = VSS
Input Offset Voltage
(Extended Temperature)
VOS
–5.0
—
+5.0
mV
TA = –40°C to +125°C, VCM = VSS
Input Offset (Note 1)
Input Offset Temperature Drift
ΔVOS/ΔTA
—
±1.7
—
Power Supply Rejection Ratio
PSRR
70
90
—
IB
—
±1.0
—
pA
Note 2
IB
—
50
200
pA
TA= +85°C (Note 2)
IB
—
2
5
nA
TA= +125°C (Note 2)
IOS
—
±1.0
—
pA
Note 3
13
µV/°C TA = –40°C to +125°C, VCM = VSS
dB
VCM = VSS
Input Bias Current and Impedance
Input Bias Current
At Temperature
At Temperature
Input Offset Current
Common Mode Input Impedance
ZCM
—
10 ||6
—
Ω||pF Note 3
Differential Input Impedance
ZDIFF
—
1013||3
—
Ω||pF Note 3
Common Mode Input Voltage Range
VCMR
VSS − 0.15
—
VDD + 0.15
VCMR
VSS − 0.30
—
VDD + 0.30
V
VDD = 5.5V (Note 5)
Common Mode Rejection Ratio
CMRR
70
85
—
dB
VCM = –0.3V to 2.5V, VDD = 5V
(Note 6)
Common Mode Rejection Ratio
CMRR
65
80
—
dB
VCM = –0.3V to 5.3V, VDD = 5V
(Note 6)
AOL
90
110
—
dB
VOUT = 0.2V to VDD – 0.2V,
VCM = VSS (Note 1)
Common Mode (Note 4)
V
VDD = 2.0V (Note 5)
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
Note 1:
2:
3:
4:
5:
6:
The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
The current at the MCP6275’s VINB– pin is specified by IB only.
This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
The MCP6275’s VINB– pin (op amp B) has a common mode input voltage range (VCMR) of VSS + 100 mV to
VDD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B)
has a voltage range specified by VOH and VOL.
Set by design and characterization.
Does not apply to op amp B of the MCP6275.
DS21810E-page 2
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
VOL, VOH
VSS + 15
—
VDD − 15
mV
ISC
—
±25
—
mA
Conditions
Output
Maximum Output Voltage Swing
Output Short Circuit Current
0.5V output overdrive (Note 4)
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
2:
3:
4:
5:
6:
VDD
2.0
—
5.5
V
IQ
100
170
240
µA
IO = 0
The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
The current at the MCP6275’s VINB– pin is specified by IB only.
This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
The MCP6275’s VINB– pin (op amp B) has a common mode input voltage range (VCMR) of VSS + 100 mV to
VDD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B)
has a voltage range specified by VOH and VOL.
Set by design and characterization.
Does not apply to op amp B of the MCP6275.
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2, CL = 60 pF and and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
2.0
—
MHz
Phase Margin
PM
—
65
—
°
Slew Rate
SR
—
0.9
—
V/µs
G = +1
Noise
Input Noise Voltage
Eni
—
4.6
—
µVP-P
Input Noise Voltage Density
eni
—
20
—
nV/√Hz
f = 1 kHz
Input Noise Current Density
ini
—
3
—
fA/√Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
–40
—
+125
°C
Operating Temperature Range
TA
–40
—
+125
°C
Storage Temperature Range
TA
–65
—
+150
°C
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Thermal Resistance, 6L-SOT-23
θJA
—
230
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Conditions
Temperature Ranges
Note
Thermal Package Resistances
Note:
The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
© 2006 Microchip Technology Inc.
DS21810E-page 3
MCP6271/1R/2/3/4/5
MCP6273/MCP6275 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2, CL = 60 pF and and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
0.2VDD
V
CS Input Current, Low
ICSL
—
0.01
—
µA
CS Logic Threshold, High
VIH
0.8VDD
—
VDD
V
CS Input Current, High
ICSH
—
0.7
2
µA
CS = VDD
GND Current per Amplifier
ISS
—
–0.7
—
µA
CS = VDD
Amplifier Output Leakage
—
—
0.01
—
µA
CS = VDD
CS Low to Valid Amplifier
Output, Turn on Time
tON
—
4
10
µs
CS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output
High-Z
tOFF
—
0.01
—
µs
CS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
VHYST
—
0.6
—
V
VDD = 5V
CS Low Specifications
CS = VSS
CS High Specifications
Dynamic Specifications (Note 1)
Hysteresis
Note 1:
The input condition (VIN) specified applies to both op amp A and B of the MCP6275. The dynamic
specification is tested at the output of op amp B (VOUTB).
CS
VIL
VIH
tOFF
tON
VOUT
High-Z
High-Z
-0.7 µA (typ.)
ISS
-0.7 µA (typ.)
-170 µA (typ.)
0.7 µA (typ.)
ICS
0.7 µA (typ.)
10 nA (typ.)
FIGURE 1-1:
Timing Diagram for the
Chip Select (CS) pin on the MCP6273 and
MCP6275.
DS21810E-page 4
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
14%
2%
Input Offset Voltage (mV)
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage, with VDD = 2.0V.
© 2006 Microchip Technology Inc.
10
8
3.0
2.6
2.4
6.0
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
Common Mode Input Voltage (V)
TA = +125°C
100
50
TA = +85°C
TA = +25°C
TA = -40°C
0
-50
-100
5.0
-50
-100
150
4.5
0
200
4.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 5.5V
250
3.5
150
Input Bias Current at
3.0
200
50
2.8
300
VDD = 2.0V
100
5.5
FIGURE 2-5:
TA = +125°C.
Input Bias Current at
2.5
250
Input Bias Current (nA)
2.0
Input Offset Voltage (µV)
300
90 100
1.5
FIGURE 2-2:
TA = +85°C.
30 40 50 60 70 80
Input Bias Current (pA)
1.0
20
0.5
10
-0.5
0
2.2
0%
2.0
4%
1.8
8%
1.6
12%
1.4
16%
1.2
20%
422 Samples
TA = +125°C
1.0
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
Input Offset Voltage Drift.
0.8
422 Samples
TA = 85°C
Percentage of Occurrences
28%
FIGURE 2-4:
Input Offset Voltage.
Input Offset Voltage (µV)
Percentage of Occurrences
32%
Input Offset Voltage Drift (µV/°C)
0.6
FIGURE 2-1:
6
0%
4
3.0
2.4
1.8
1.2
0.6
0.0
-0.6
-1.2
-1.8
-2.4
0%
2
2%
4%
0
4%
6%
-2
6%
8%
-4
8%
10%
-6
10%
-8
12%
832 Samples
VCM = VSS
TA = -40°C to +125°C
12%
-10
14%
Percentage of Occurrences
832 Samples
VCM = VSS
16%
0.0
18%
-3.0
Percentage of Occurrences
RL = 10 kΩ to VDD/2, CL = 60 pF and CS is tied low.
Common Mode Input Voltage (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage, with VDD = 5.5V.
DS21810E-page 5
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
Common Mode Input Voltage
Range Limit (V)
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
-0.50
Typical lower (VCM – VSS) limit
VDD = 2.0V
VDD = 5.5V
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-7:
Common Mode Input
Voltage Range Lower Limit vs. Temperature.
Input Offset Voltage (µV)
300
VCM = VSS
Representative Part
250
200
150
100
50
0
VDD = 2.0V
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
125
VDD = 5.5V
-50
-100
Input Offset Voltage vs.
PSRR–
PSRR+
40
30
20
1
10 1.E+02
100 1.E+03
1k
10k 1.E+05
100k 1.E+06
1M
1.E+00
1.E+01
1.E+04
Frequency (Hz)
DS21810E-page 6
125
1,000
VCM = VDD
VDD = 5.5V
Input Bias Current
100
10
Input Offset Current
1
55
65 75 85 95 105 115 125
Ambient Temperature (°C)
FIGURE 2-11:
Input Bias, Input Offset
Currents vs. Temperature.
CMRR, PSRR vs.
PSRR, CMRR (dB)
CMRR, PSRR (dB)
70
FIGURE 2-9:
Frequency.
0
25
50
75
100
Ambient Temperature (°C)
120
80
50
-25
45
CMRR
90
60
Typical upper (VCM – VDD) limit
10,000
110
100
VDD = 2.0V
FIGURE 2-10:
Common Mode Input
Voltage Range Upper Limit vs. Temperature.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-8:
Output Voltage.
VDD = 5.5V
-50
Input Bias, Offset Currents
(pA)
Common Mode Input Voltage
Range Limit (V)
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
110
100
CMRR
90
PSRR
(VCM = VSS)
80
70
60
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-12:
Temperature.
CMRR, PSRR vs.
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
2.5
Input Bias, Offset Currents
(nA)
45
Input Bias Current
35
25
15
5
Input Offset Current
-5
TA = 85°C
VDD = 5.5V
-15
-25
2.0
1.5
0.5
0.0
-1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-16:
Input Bias, Offset Currents
vs. Common Mode Input Voltage, with
TA = +125°C.
Ouput Voltage Headroom
(mV)
Quiescent Current
(µA/amplifier)
Input Offset Current
1000
250
200
150
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
100
50
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current vs.
0
100
-30
Gain
80
60
-60
-90
Phase
FIGURE 2-15:
Frequency.
1.E+08
1.E+07
1
1.E+06
0.1
1.E+05
-210
1.E+04
-180
1.E+03
0
-20
1.E+02
-150
1.E+01
20
1.E+00
-120
1.E-01
40
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
Open-Loop Gain, Phase vs.
© 2006 Microchip Technology Inc.
10
VOL – VSS
VDD – VOH
1
0.01
0.1
1
Output Current Magnitude (mA)
3.0
Gain Bandwidth Product
(MHz)
120
100
10
FIGURE 2-17:
Output Voltage Headroom
vs. Output Current Magnitude.
Open-Loop Phase (°)
FIGURE 2-14:
Supply Voltage.
Open-Loop Gain (dB)
TA = 125°C
VDD = 5.5V
-0.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias, Offset Currents
vs. Common Mode Input Voltage, with
TA = +85°C.
Input Bias Current
1.0
80
2.5
75
GBWP, VDD = 5.5V
VDD = 2.0V
2.0
1.5
70
65
1.0
60
PM, VDD = 5.5V
VDD = 2.0V
0.5
55
0.0
-50
Phase Margin (°)
Input Bias, Offset Currents
(pA)
55
-25
0
25
50
75 100
Ambient Temperature (°C)
50
125
FIGURE 2-18:
Gain Bandwidth Product,
Phase Margin vs. Temperature.
DS21810E-page 7
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
1.8
1.6
VDD = 5.5V
Slew Rate (V/µs)
VDD = 2.0V
1
Frequency (Hz)
1M
1.E+07
100k
1.E+06
10k
1.E+05
1.2
1.0
0.8
VDD = 2.0V
0.6
Rising Edge
0.4
10M
FIGURE 2-19:
Maximum Output Voltage
Swing vs. Frequency.
0.0
-50
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-22:
100
125
Slew Rate vs. Temperature.
25
Input Noise Voltage Density
(nV/¥Hz)
10
5
f = 1 kHz
VDD = 5.0V
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
0
10
0.1
1
10
100 1k
10k 100k 1M
1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+
01
00
01 Frequency
02
03(Hz) 04
05
06
Input Noise Voltage Density
15
1.0
100
20
0.5
1,000
FIGURE 2-20:
vs. Frequency.
-25
0.0
1.E+04
1.E+03
1k
Input Noise Voltage Density
(nV/—Hz)
Falling Edge
0.2
0.1
Common Mode Input Voltage (V)
FIGURE 2-23:
Input Noise Voltage Density
vs. Common Mode Input Voltage, with f = 1 kHz.
140
30
25
20
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
15
10
5
Channel-to-Channel
Separation (dB)
35
Ouptut Short-Circuit Current
(mA)
VDD = 5.5V
1.4
-0.5
Maximum Output Voltage
Swing (V P-P )
10
130
120
110
100
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-21:
Output Short Circuit Current
vs. Supply Voltage.
DS21810E-page 8
1
10
Frequency (kHz)
100
FIGURE 2-24:
Channel-to-Channel
Separation vs. Frequency (MCP6272 and
MCP6274).
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
700
200
Op Amp turns Off
Op Amp turns On
150
Hysteresis
100
50
CS swept
High-to-Low
CS swept
Low-to-High
600
Quiescent Current
(µA/amplifier)
Quiescent Current
(µA/amplifier)
VDD = 2.0V
Hysteresis
500
CS swept
Low-to-High
400
300
200
100
0
Op Amp
turns
On/Off
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Chip Select Voltage (V)
FIGURE 2-25:
Quiescent Current vs. Chip
Select (CS) Voltage, with VDD = 2.0V (MCP6273
and MCP6275 only).
FIGURE 2-28:
Quiescent Current vs. Chip
Select (CS) Voltage, with VDD = 5.5V (MCP6273
and MCP6275 only).
5.0
5.0
G = +1 V/V
VDD = 5.0V
4.5
4.0
4.5
Output Voltage (V)
Output Voltage (V)
VDD = 5.5V
CS swept
High-to-Low
250
3.5
3.0
2.5
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
Time (5 µs/div)
Time (5 µs/div)
FIGURE 2-26:
Pulse Response.
Large Signal Non-inverting
FIGURE 2-29:
Response.
Large Signal Inverting Pulse
G = -1 V/V
Output Voltage (10 mV/div)
Output Voltage (10 mV/div)
G = +1 V/V
Time (2 µs/div)
Time (2 µs/div)
FIGURE 2-27:
Pulse Response.
G = -1 V/V
VDD = 5.0V
Small Signal Non-inverting
© 2006 Microchip Technology Inc.
FIGURE 2-30:
Response.
Small Signal Inverting Pulse
DS21810E-page 9
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
2.0
CS
1.5
1.0
0.5
VOUT
VDD = 2.0V
G = +1 V/V
VIN = VSS
Output On
Output High-Z
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Chip Select, Output Voltages
(V)
Chip Select, Output Voltages
(V)
2.5
0.0
Time (5 µs/div)
FIGURE 2-31:
Chip Select (CS) to
Amplifier Output Response Time, with
VDD = 2.0V (MCP6273 and MCP6275 only).
+125°C
+85°C
+25°C
-40°C
Input Voltage (V)
DS21810E-page 10
Output High-Z
Input Current vs. Input
Output On
FIGURE 2-33:
Chip Select (CS) to
Amplifier Output Response Time, with
VDD = 5,5V (MCP6273 and MCP6275 only).
6
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
FIGURE 2-32:
Voltage.
VOUT
Time (5 µs/div)
Input, Output Voltage (V)
Input Current Magnitude (A)
1.E-02
10m
1.E-03
1m
1.E-04
100µ
1.E-05
10µ
1.E-06
1µ
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
VDD = 5.5V
G = +1 V/V
VIN = VSS
CS
VDD = 5.0V
G = +2 V/V
5
4
3
2
1
0
VIN
VOUT
-1
Time (1 ms/div)
FIGURE 2-34:
The MCP6271/1R/2/3/4/5
Show no Phase Reversal.
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6271
(PDIP, SOIC, MSOP)
MCP6271
(SOT-23-5)
MCP6271R
(SOT-23-5)
MCP6273
(PDIP, SOIC, MSOP)
MCP6273
(SOT-23-6)
2
4
4
2
4
VIN–
Inverting Input
3
3
3
3
3
VIN+
Non-inverting Input
4
2
5
4
2
VSS
Negative Power Supply
6
1
1
6
1
VOUT
Analog Output
7
5
2
7
6
VDD
Positive Power Supply
—
—
8
5
CS
Chip Select
1,5,8
—
—
1,5
—
NC
No Internal Connection
MCP6272
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6274
MCP6275
Symbol
1
1
—
VOUTA
Analog Output (op amp A)
2
2
2
VINA–
Inverting Input (op amp A)
Non-inverting Input (op amp A)
3
3
3
VINA+
8
4
8
VDD
Description
Positive Power Supply
5
5
—
VINB+
Non-inverting Input (op amp B)
6
6
6
VINB–
Inverting Input (op amp B)
7
7
7
VOUTB
Analog Output (op amp B)
—
8
—
VOUTC
Analog Output (op amp C)
—
9
—
VINC–
Inverting Input (op amp C)
—
10
—
VINC+
Non-inverting Input (op amp C)
Negative Power Supply
4
11
4
VSS
—
12
—
VIND+
Non-inverting Input (op amp D)
—
13
—
VIND–
Inverting Input (op amp D)
—
14
—
VOUTD
Analog Output (op amp D)
—
—
1
VOUTA / VINB+
—
—
5
CS
Analog Output (op amp A)/Non-inverting Input (op amp B)
Chip Select
Analog Outputs
The output pins are low impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs are high
impedance CMOS inputs with low bias currents.
3.3
Description
—
TABLE 3-2:
3.1
Symbol
MCP6275’s VOUTA/VINB+ Pin
For the MCP6275 only, the output of op amp A is
connected directly to the non-inverting input of op amp
B; this is the VOUTA/VINB+ pin. This connection makes
it possible to provide a CS pin for duals in 8-pin
packages.
© 2006 Microchip Technology Inc.
3.4
CS Digital Input
This is a CMOS, Schmitt triggered input that places the
part into a low power mode of operation.
3.5
Power Supply (VSS and VDD)
The positive power supply (VDD) is 2.0V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need
to use a bulk capacitor (within 100 mm), which can be
shared with nearby analog parts.
DS21810E-page 11
MCP6271/1R/2/3/4/5
4.0
APPLICATION INFORMATION
The MCP6271/1R/2/3/4/5 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low cost, low power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
make the MCP6271/1R/2/3/4/5 ideal for battery
powered applications.
4.1
Rail-to-Rail Inputs
The input stage of the MCP6271/1R/2/3/4/5 op amps
uses two differential CMOS input stages in parallel.
One operates at low common mode input voltage (VCM,
which is aproximately equal to VIN+ and VIN– in normal
operation) and the other at high VCM. With this topology, the input operates with VCM up to 0.3V past either
supply rail (see Figure 2-7 and Figure 2-10). The input
offset voltage (VOS) is measured at VCM = VSS – 0.3V
and VDD + 0.3V to ensure proper operation.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute Maximum Ratings † at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-2 shows the
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
VDD
D1
V1
R1
The transition between the two input stage occurs
when VCM ≈ VDD – 1.1V (see Figure 2-3 and Figure 26). For the best distortion and gain linearity, with noninverting gains, avoid this region of operation.
4.1.1
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
VDD Bond
Pad
R2
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
FIGURE 4-2:
Inputs.
Bond V –
IN
Pad
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-32. Applications that are high impedance may
need to limit the useable voltage range.
4.2
Input
Stage
VOUT
R1 >
INPUT VOLTAGE AND CURRENT
LIMITS
VIN+ Bond
Pad
MCP627X
V2
PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-34 shows an input voltage
exceeding both supplies with no phase inversion.
4.1.2
D2
Rail-to-Rail Output
The output voltage range of the MCP6271/1R/2/3/4/5
op amps is VDD – 15 mV (min.) and VSS + 15 mV
(max.) when RL = 10 kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-17 for more information.
VSS Bond
Pad
FIGURE 4-1:
Structures.
DS21810E-page 12
Simplified Analog Input ESD
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
4.3
Capacitive Loads
4.4
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
–
RISO
VOUT
MCP627X
+
VIN
CL
MCP6273/5 Chip Select (CS)
The MCP6273 and MCP6275 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typ.)
and flows through the CS pin to VSS. When this
happens, the amplifier output is put into a high
impedance state. By pulling CS low, the amplifier is
enabled. The CS pin has a 5 MΩ (typ.) pull-down
resistor connected to VSS, so it will go low if the CS pin
is left floating. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
4.5
Cascaded Dual Op Amps
(MCP6275)
The MCP6275 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in low power mode. Refer to Section 4.4
“MCP6273/5 Chip Select (CS)”.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).
VINB–
VOUTA/VINB+
FIGURE 4-3:
Output Resistor, RISO
stabilizes large capacitive loads.
1
VINA–
VINA+
6
2
3
B
A
7
VOUTB
MCP6275
5
CS
Recommended RISO (:)
1,000
FIGURE 4-5:
The output of op amp A is loaded by the input
impedance of op amp B, which is typically
1013Ω⎟⎟6 pF, as specified in the DC specification table
(Refer to Section 4.3 “Capacitive Loads” for further
details regarding capacitive loads).
100
GN = 1 V/V
GN = 2 V/V
GN t 4 V/V
10
10
100
1,000
Cascaded Gain Amplifier.
10,000
Normalized Load Capacitance; CL / GN (pF)
FIGURE 4-4:
Recommended RISO Values
for Capacitive Loads.
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD – 20 mV.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6271/1R/2/3/4/5 SPICE
macro model are helpful.
© 2006 Microchip Technology Inc.
DS21810E-page 13
MCP6271/1R/2/3/4/5
4.6
Unused Amplifiers
VIN–
An unused op amp in a quad package (MCP6274)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. In Circuit A, R1 and R2 produce a voltage
within its output voltage range (VOH, VOL). The op amp
buffers this voltage, which can be used elsewhere in
the circuit. Circuit B uses the minimum number of
components and operates as a comparator.
VIN+
VSS
Guard Ring
¼ MCP6274 (A)
¼ MCP6274 (B)
VDD
VDD
R1
FIGURE 4-7:
for Inverting Gain.
1.
VDD
R2
FIGURE 4-6:
4.7
Unused Op Amps.
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.8
2.
Example Guard Ring Layout
For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
Non-inverting Gain and Unity Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6271/1R/2/3/4/5 family’s bias current at 25°C
(1 pA, typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is illustrated in
Figure 4-7.
DS21810E-page 14
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
4.9
Application Circuits
4.9.1
4.9.2
ACTIVE FULL-WAVE RECTIFIER
The MCP6271/1R/2/3/4/5 family of amplifiers can be
used in applications such as an Active Full-Wave
Rectifier or an Absolute Value circuit, as shown in
Figure 4-8. The amplifier and feedback loops in this
active voltage rectifier circuit eliminate the diode drop
problem that exists in a passive voltage rectifier. This
circuit behaves as a follower (the output follows the
input) as long as the input signal is more positive than
the reference voltage. If the input signal is more
negative than the reference voltage, however, the
circuit behaves as an inverting amplifier. Therefore, the
output voltage will always be above the reference
voltage, regardless of the input signal.
LOSSY NON-INVERTING
INTEGRATOR
The non-inverting integrator shown in Figure 4-9 is
easy to build. It saves one op amp over the typical
Miller integrator plus inverting amplifier configuration.
The phase accuracy of this integrator depends on the
matching of the input and feedback resistor-capacitor
time constants. RF makes this a lossy integrator (it has
finite gain at DC), and makes this integrator stable by
itself.
VIN
R1
+
C1
MCP6271
_
RF
R2
C2
R1
VIN
–
R3
R4
Op Amp B
VOUT
+
1/2
MCP6272
R5
VREF
D2
D1
RF ≈ R2
R2
R 1 C 1 = ( R 2 ||R F )C 2
V OUT
1 ------------- ≈ ------------------,
V IN
s ( R1 C1 )
FIGURE 4-9:
1
f ≈ --------------------------------------------------2πR 1 C 1 ( 1 + R F ⁄ R 2 )
Non-Inverting Integrator.
R1 = R2 = R3
–
VREF
VOUT
Op Amp A
+
1/2
MCP6272
V D1 ⎞
R 4 < R 3 ⎛ 1 – --------------------------⎝
V REF – V SS⎠
R2 R4
R 5 = -----------2R 3
Input
Output
VREF
VREF
time
FIGURE 4-8:
time
Active Full-wave Rectifier.
The design equations give a gain of ±1 from VIN to
VOUT, and produce rail-to-rail outputs.
© 2006 Microchip Technology Inc.
DS21810E-page 15
MCP6271/1R/2/3/4/5
4.9.3
CASCADED OP AMP
APPLICATIONS
R4
The MCP6275 provides the flexibility of Low power
mode for dual op amps in an 8-pin package. The
MCP6275 eliminates the added cost and space in a
battery powered application by using two single op
amps with Chip Select (CS) lines or a 10-pin device
with one CS line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with a CS
line becomes suitable. The circuits below show
possible applications for this device.
4.9.3.1
R3
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In
applications where op amp A is driving capacitive or
low resistive loads in the feedback loop (such as an
integrator or filter circuit) the op amp may not have
sufficient source current to drive the load. In this case,
op amp B can be used as a buffer.
VIN
MCP6275
CS
FIGURE 4-11:
Configuration.
MCP6275
Cascaded Gain Circuit
Difference Amplifier
Figure 4-12 shows op amp A configured as a difference
amplifier with Chip Select. In this configuration, it is
recommended that well matched resistors (e.g., 0.1%)
be used to increase the Common Mode Rejection Ratio
(CMRR). Op amp B can be used to provide additional
gain and isolate the load from the difference amplifier.
R2
R1
R2
A
R4
R3
VOUTB
B
Load
VOUT
B
VIN2
A
R1
A
4.9.3.3
Load Isolation
R2
VIN1
B
VOUT
MCP6275
R1
CS
FIGURE 4-10:
Buffer.
4.9.3.2
Isolating the Load with a
Cascaded Gain
Figure 4-11 shows a cascaded gain circuit configuration with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this
configuration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of op amp
A and B, as shown below:
V OUT = V IN G A G B + V OSA G A G B + V OSB G B
Where:
GA
=
CS
FIGURE 4-12:
4.9.3.4
=
op amp B gain
VOSA
=
op amp A input offset voltage
VOSB
=
op amp B input offset voltage
Inverting Integrator with Active
Compensation and Chip Select
Figure 4-13 uses an active compensator (op amp B) to
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a unity gain buffer to isolate the
integration capacitor C1 from op amp A and drives the
capacitor with a low impedance source. Since both op
amps are matched very well, they provide a high quality
integrator.
op amp A gain
GB
VIN
C1
R1
B
VOUT
A
MCP6275
Therefore, it is recommended that you set most of the
gain with op amp A and use op amp B with relatively
small gain (e.g., a unity gain buffer).
CS
FIGURE 4-13:
Compensation.
DS21810E-page 16
Difference Amplifier Circuit.
Integrator Circuit with Active
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
4.9.3.5
Second Order MFB with an Extra
Pole-Zero Pair
Figure 4-14 is a second order multiple feedback lowpass filter with Chip Select. Use the FilterLab® software
from Microchip Technology Inc. to determine the R and
C values for op amp A’s second order filter. Op amp B
can be used to add a pole-zero pair using C3, R6 and
R7.
C3
R6
R7
R1
VIN
R3
VDD
R2
C1
R5
A
VOUT
B
Capacitorless Second Order
Low-Pass filter with Chip Select
The low-pass filter shown in Figure 4-16 does not
require external capacitors and uses only three
external resistors; the op amp’s GBWP sets the corner
frequency. R1 and R2 are used to set the circuit gain. R3
is used to set the Q. To avoid gain peaking in the
frequency response, Q needs to be low (lower values
need to be selected for R3). Note that the amplifier
bandwidth varies greatly over temperature and
process. This configuration, however, provides a low
cost solution for applications with high bandwidth
requirements.
VIN
R1
R2
R3
A
MCP6275
B
VREF
R4
VOUT
MCP6275
CS
FIGURE 4-14:
Second Order Multiple
Feedback Low-Pass Filter with an Extra PoleZero Pair.
4.9.3.6
4.9.3.7
Second Order Sallen-Key with an
Extra Pole-Zero Pair
CS
FIGURE 4-16:
Capacitorless Second Order
Low-Pass Filter with Chip Select.
Figure 4-15 is a second order Sallen-Key low-pass
filter with Chip Select. Use the Filterlab® software from
Microchip to determine the R and C values for
op amp A’s second order filter. Op amp B can be used
to add a pole-zero pair using C3, R5 and R6.
R5
R2
VIN R4
R3
C2
C3
R6
R1
B
VOUT
A
MCP6275
C1
CS
FIGURE 4-15:
Second Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
© 2006 Microchip Technology Inc.
DS21810E-page 17
MCP6271/1R/2/3/4/5
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6271/1R/2/3/4/5 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP6271/1R/2/3/4/5 op amps is available on our web
site at www.microchip.com. This model is intended to
be an initial design tool that works well in the op amp’s
linear region of operation at room temperature. See the
macro model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab software is an innovative tool that
simplifies analog active filter (using op amps) design. It
is available free of charge from our web site at
www.microchip.com. The FilterLab software tool
provides full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
DS21810E-page 18
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
5-Lead SOT-23 (MCP6271 and MCP6271R)
Device
XXNN
Code
MCP6271
CGNN
MCP6271R
ETNN
CG25
Note: Applies to 5-Lead SOT-23
Example:
6-Lead SOT-23 (MCP6273)
XXNN
CK25
8-Lead MSOP
Example:
XXXXXX
6271E
YWWNNN
644256
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
Example:
MCP6271
E/P256
0437
OR
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
e3
*
Note:
Example:
MCP6271
E/SN0437
256
Legend: XX...X
Y
YY
WW
NNN
MCP6271
e3
E/P^^256
0644
OR
MCP6271E
e3
SN^^0644
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS21810E-page 19
MCP6271/1R/2/3/4/5
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6274)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
Example:
MCP6274-E/P
0437256
OR
MCP6274
e3
E/P^^
0644256
14-Lead SOIC (150 mil) (MCP6274)
Example:
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
MCP6274ESL
0437256
OR
MCP6274
e3
E/SL^^
0644256
14-Lead TSSOP (MCP6274)
XXXXXX
YYWW
NNN
DS21810E-page 20
Example:
6274EST
0437
256
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
B
p1
n
D
1
α
c
A
φ
L
β
A1
INCHES*
Units
Dimension Limits
A2
MIN
MILLIMETERS
NOM
MAX
MIN
NOM
Pitch
n
p
.038
0.95
Outside lead pitch (basic)
p1
.075
1.90
Number of Pins
Overall Height
5
MAX
5
A
.035
.046
.057
0.90
1.18
1.45
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
.014
.018
.022
0.35
0.45
0.55
Foot Angle
L
f
Lead Thickness
c
.004
Lead Width
B
a
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
b
0
5
.006
.017
10
0
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
© 2006 Microchip Technology Inc.
DS21810E-page 21
MCP6271/1R/2/3/4/5
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
B
p1
n
D
1
α
c
A
φ
β
A1
L
INCHES*
Units
Dimension Limits
MIN
Pitch
.038 BSC
Outside lead pitch
p1
.075 BSC
Overall Height
MILLIMETERS
NOM
n
p
Number of Pins
A2
MAX
MIN
NOM
6
MAX
6
0.95 BSC
1.90 BSC
A
.035
.046
.057
0.90
1.18
1.45
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
L
φ
.014
.022
0.35
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
β
.018
0
5
.006
.017
10
0.45
0
0.55
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
DS21810E-page 22
Revised 09-12-05
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
ϕ
c
L1
A1
Number of Pins
Pitch
Overall Height
Molded Package
Standoff
Overall Width
Molded Package
Overall Length
Foot Length
Footprint
Foot Angle
Lead Thickness
Lead Width
Units
Dimension Limits
N
e
A
Thickness
A2
A1
E
Width
E1
D
L
L1
ϕ
c
b
MIN
—
0.75
0.00
0.40
0°
0.08
0.22
MILLIMETERS
NOM
8
0.65 BSC
—
0.85
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
—
—
—
L
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
© 2006 Microchip Technology Inc.
DS21810E-page 23
MCP6271/1R/2/3/4/5
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21810E-page 24
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
© 2006 Microchip Technology Inc.
DS21810E-page 25
MCP6271/1R/2/3/4/5
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
eB
B1
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
.015
A1
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
eB
Overall Row Spacing
§
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21810E-page 26
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
L
β
Units
Dimension Limits
n
p
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
A2
.052
.061
1.55
Standoff
§
A1
.004
.010
0.25
Overall Width
E
.228
.244
6.20
Molded Package Width
E1
.150
.157
3.99
Overall Length
D
.337
.347
8.81
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.016
.050
1.27
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.014
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
Revised 7-20-06
© 2006 Microchip Technology Inc.
MIN
A1
MIN
DS21810E-page 27
MCP6271/1R/2/3/4/5
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
Units
Dimension Limits
A1
A2
MILLIMETERS*
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Overall Height
A
.039
.041
.043
1.00
1.05
1.10
Molded Package Thickness
A2
.033
.035
.037
0.85
0.90
0.95
Number of Pins
14
14
.026 BSC
0.65 BSC
Standoff
A1
.002
.004
.006
0.05
0.10
0.15
Overall Width
E
.246
.251
.256
6.25
6.38
6.50
Molded Package Width
E1
.169
.173
.177
4.30
4.40
4.50
Molded Package Length
D
.193
.197
.201
4.90
5.00
5.10
Foot Length
L
φ
.020
.024
.028
0.50
0.60
0.70
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.007
Mold Draft Angle Top
Mold Draft Angle Bottom
β
4°
0°
8°
0°
.006
.008
0.09
.010
.012
0.19
4°
8°
0.15
0.20
0.25
0.30
12° REF
12° REF
12° REF
12° REF
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
DS21810E-page 28
Revised: 08-17-05
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
APPENDIX A:
REVISION HISTORY
Revision E (December 2006)
The following is the list of modifications:
1.
2.
3.
4.
Updated specifications (Section 1.0 “Electrical
Characteristics”):
a) Clarified Absolute Maximum Analog Input
Voltage and Current specifications.
b) Clarified VCMR, VOL, VOH, and PM
specifications.
c) Corrected the typical Eni.
Added plots on Common Mode Input Range
behavior vs. temperature and supply voltage
(Section 2.0 “Typical Performance Curves”).
Added applications writeup on unused op amps
and corrected description of floating CS pin
behavior (Section 4.0 “Application Information”).
Updated package information (Section 6.0
“Packaging Information”):
a) Corrected package markings.
b) Added disclaimer to package outline
drawings.
Revision D (December 2004)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
Added SOT-23-5 packages for the DSTEMP
and MCP6271R single op amps.
Added SOT-23-6 packages for the DSTEMP
single op amp.
Added Section 3.0 “Pin Descriptions”.
Corrected application circuits
(Section 4.9 “Application Circuits”).
Added SOT-23-5 and SOT-23-6 packages and
corrected
package
marking
information
(Section 6.0 “Packaging Information”).
Added Appendix A: Revision History.
Revision C (June 2004)
Revision B (October 2003)
Revision A (June 2003)
• Original data sheet release.
© 2006 Microchip Technology Inc.
DS21810E-page 29
MCP6271/1R/2/3/4/5
NOTES:
DS21810E-page 30
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
–
X
/XX
Temperature
Range
Package
Device:
MCP6271:
MCP6271T:
MCP6271RT:
MCP6272:
MCP6272T:
MCP6273:
MCP6273T:
MCP6274:
MCP6274T:
MCP6275:
MCP6275T:
Single Op Amp
Single Op Amp
(Tape and Reel)
(SOIC, MSOP, SOT-23-5)
Single Op Amp
(Tape and Reel) (SOT-23-5)
Dual Op Amp
Dual Op Amp
(Tape and Reel) (SOIC, MSOP)
Single Op Amp with Chip Select
Single Op Amp with Chip Select
(Tape and Reel)
(SOIC, MSOP, SOT-23-6)
Quad Op Amp
Quad Op Amp
(Tape and Reel) (SOIC, TSSOP)
Dual Op Amp with Chip Select
Dual Op Amp with Chip Select
(Tape and Reel) (SOIC, MSOP)
Temperature Range:
E
= -40°C to +125°C
Package:
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6271, MCP6271R)
CH = Plastic Small Outline Transistor (SOT-23), 6-lead
(MCP6273)
MS = Plastic MSOP, 8-lead
P
= Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4.4 mm Body), 14-lead
© 2006 Microchip Technology Inc.
Examples:
a)
MCP6271-E/SN:
b)
MCP6271-E/MS:
c)
MCP6271-E/P:
d)
MCP6271T-E/OT:
a)
MCP6271RT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
a)
MCP6272-E/SN:
b)
MCP6272-E/MS:
c)
MCP6272-E/P:
d)
MCP6272T-E/SN:
a)
MCP6273-E/SN:
b)
c)
d)
Extended Temperature,
8LD SOIC package.
Extended Temperature,
8LD MSOP package.
Extended Temperature,
8LD PDIP package.
Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
Extended Temperature,
8LD SOIC package.
Extended Temperature,
8LD MSOP package.
Extended Temperature,
8LD PDIP package.
Tape and Reel,
Extended Temperature,
8LD SOIC package.
Extended Temperature,
8LD SOIC package.
MCP6273-E/MS: Extended Temperature,
8LD MSOP package.
MCP6273-E/P:
Extended Temperature,
8LD PDIP package.
MCP6273T-E/CH: Extended Temperature,
6LD SOT-23 package.
a)
MCP6274-E/P:
b)
MCP6274T-E/SL:
c)
MCP6274-E/SL:
d)
MCP6274-E/ST:
a)
MCP6275-E/SN:
b)
MCP6275-E/MS:
c)
MCP6275-E/P:
d)
MCP6275T-E/SN:
Extended Temperature,
14LD PDIP package.
Tape and Reel,
Extended Temperature,
14LD SOIC package.
Extended Temperature,
14LD SOIC package.
Extended Temperature,
14LD TSSOP package.
Extended Temperature,
8LD SOIC package.
Extended Temperature,
8LD MSOP package.
Extended Temperature,
8LD PDIP package.
Tape and Reel,
Extended Temperature,
8LD SOIC package.
DS21810E-page 31
MCP6271/1R/2/3/4/5
NOTES:
DS21810E-page 32
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21810E-page 33
WORLDWIDE SALES AND SERVICE
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12/08/06
DS21810E-page 34
© 2006 Microchip Technology Inc.