Not recommended for new designs – Please use 93LC46C, 93LC56C or 93LC66C. 93LC46/56/66 1K/2K/4K 2.5V Microwire Serial EEPROM Features: Package Types CS CLK 1 2 DI DO 3 8 7 VCC NU 6 4 5 ORG VSS NU VCC 1 2 8 7 ORG VSS CS CLK 3 6 DO DI ROTATED SOIC 93LC46X 93LC56X 93LC66X - Industrial (I): PDIP/SOIC 93LC46 93LC56 93LC66 • Single supply with programming operation down to 2.5V • Low-power CMOS technology • 100 µA typical active read current at 2.5V • 3 µA typical standby current at 2.5V • ORG pin selectable memory configuration • 128 x 8- or 64 x 16-bit organization (93LC46) • 256 x 8- or 128 x 16-bit organization (93LC56) • 512 x 8 or 256 x 16 bit organization (93LC66) • Self-timed erase and write cycles (including auto-erase) • Automatic ERAL before WRAL • Power on/off data protection circuitry • Industry standard 3-wire serial I/O • Device status signal during erase/write cycles • Sequential read function • 1,000,000 E/W cycles ensured • Data retention > 200 years • 8-pin PDIP/SOIC (SOIC in JEDEC standards) • Temperature ranges supported: 4 5 Block Diagram VCC VSS Memory Array -40°C to +85°C Address Decoder Address Counter Description: The Microchip Technology Inc. 93LC46/56/66 are 1K, 2K and 4K low voltage serial Electrically Erasable PROMs (EEPROM). The device memory is configured as x8 or x16 bits depending on the external logic of levels of the ORG pin. Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC Series is available in standard 8-pin PDIP and surface mount SOIC packages. The rotated pin-out 93LC46X/56X/66X are offered in the “SN” package only. 2004 Microchip Technology Inc. Data Register Output Buffer DO DI ORG CS Mode Decode Logic CLK Clock Register DS21712B-page 1 93LC46/56/66 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS DC CHARACTERISTICS Param. No. D1 Sym VIH1 Characteristic High-level input voltage VIH2 D2 VIL1 Low-level input voltage VIL2 D3 VOL1 Low-level output voltage VOL2 D4 VOH1 High-level output voltage VOH2 VCC = +2.5V to +5.5V Industrial (I): TA = -40°C to +85°C Min Typ Max Units Conditions 2.0 — VCC +1 V VCC ≥ 2.7V 0.7 VCC — VCC +1 V VCC ≥ 2.7V -0.3 — 0.8 V VCC ≥ 2.7V -0.3 — 0.2 VCC V VCC ≥ 2.7V — — 0.4 V IOL = 2.1 mA, VCC = 4.5V — — 0.3 V IOL = 100 µA, VCC = 2.5V 2.4 — — V IOL = 400 µA, VCC = 4.5V VCC -0.2 — — V IOL = 100 µA, VCC = 2.5V D5 ILI Input leakage current — — ±10 µA VIN = 0.1V to VCC D6 ILO Output leakage current — — ±10 µA VOUT = 0.1V to VCC D7 CIN, COUT Pin capacitance (all inputs/outputs) — — 7 pF VIN/VOUT = 0V (Note 1 & 2) TA = 25°C, FCLK = 1 MHz D8 ICC write Operating current — — 3 mA FCLK = 2 MHz, VCC = 5.5V (Note 2) D9 ICC read — — — — — 100 1 500 — mA µA µA FCLK = 2 MHz, VCC = 5.5V FCLK = 1 MHz, VCC = 3.0V FCLK = 1 MHz, VCC = 2.5V D10 ICCS — — — — — 3 100 30 — µA µA µA CLK = CS = 0V; VCC = 5.5V CLK = CS = 0V; VCC = 3.0V CLK = CS = 0V; VCC = 2.5V ORG, DI = VSS or VCC Note 1: 2: Standby current This parameter is tested at TA = 25°C and FCLK = 1 MHz. This parameter is periodically sampled and not 100% tested. DS21712B-page 2 2004 Microchip Technology Inc. 93LC46/56/66 AC CHARACTERISTICS VCC = +2.5V to +5.5V Industrial (I): TA = -40°C to +85°C AC CHARACTERISTICS Param. No. 1 Sym Characteristic Min Typ Max Units FCLK Clock frequency — — — — 2 1 MHz MHz Conditions VCC ≥ 4.5V VCC < 4.5V 2 TCKH Clock high time 250 — — ns 3 TCKL Clock low time 250 — — ns 4 TCSS Chip select setup time 50 — — ns Relative to CLK 5 TCSH Chip select hold time 0 — — ns Relative to CLK 6 TCSL Chip select low time 250 — — ns 7 TDIS Data input setup time 100 — — ns Relative to CLK 8 TDIH Data input hold time 100 — — ns Relative to CLK 9 TPD Data output delay time — — 400 ns CL = 100 pF 10 TCZ Data output disable time — — 100 ns CL = 100 pf (Note 2) 11 TSV Status valid time — — 500 ns CL = 100 pF 12 TWC Program cycle time — 4 10 ms Erase/Write mode 13 TEC — 8 15 ms ERAL mode (VCC=5V ±10%) 14 TWL — 16 30 ms WRAL mode (VCC=5V ±10%) 15 — 1M — 1M Note 1: 2: 3: Endurance cycles 25°C, VCC = 5.0V, Block mode (Note 3) This parameter is tested at TA = 25°C and FCLK = 1 MHz. This parameter is periodically sampled and not 100% tested. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com. FIGURE 1-1: CS SYNCHRONOUS DATA TIMING VIH VIL 4 2 3 5 VIH CLK VIL 7 8 VIH DI VIL 9 DO VOH (Read) VOL 9 10 11 DO VOH (Write) VOL 2004 Microchip Technology Inc. 10 Status Valid DS21712B-page 3 93LC46/56/66 TABLE 1-1: Instruction INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION) Data Out Req. CLK Cycles — D15 - D0 25 Opcode READ 1 10 EWEN 1 00 1 1 XXXX — High-Z 9 ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 9 ERAL 1 00 1 0 XXXX — (RDY/BSY) 9 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 25 WRAL 1 00 0 1 XXXX D15 - D0 (RDY/BSY) 25 EWDS 1 00 0 0 XXXX — High-Z 9 TABLE 1-2: Instruction Address Data In SB A5 A4 A3 A2 A1 A0 INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION) SB Opcode Address READ 1 10 EWEN 1 00 11XXXXX ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 Data In Data Out Req. CLK Cycles — D7 - D0 18 — High-Z 10 — (RDY/BSY) 10 ERAL 1 00 10XXXXX — (RDY/BSY) 10 WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 18 WRAL 1 00 01XXXXX D7 - D0 (RDY/BSY) 18 EWDS 1 00 00XXXXX — High-Z 10 TABLE 1-3: Instruction INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION) SB Opcode Address READ 1 10 EWEN 1 00 11XXXXXX — High-Z 11 ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 11 X A6 A5 A4 A3 A2 A1 A0 Data In Data Out Req. CLK Cycles — D15 - D0 27 ERAL 1 00 10XXXXXX — (RDY/BSY) 11 WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 27 WRAL 1 00 01XXXXXX D15 - D0 (RDY/BSY) 27 EWDS 1 00 00XXXXXX — High-Z 11 TABLE 1-4: INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION) Data In Data Out Req. CLK Cycles X A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20 00 11XXXXXXX — High-Z 12 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 12 1 00 10XXXXXXX — (RDY/BSY) 12 WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 20 WRAL 1 00 01XXXXXXX D7 - D0 (RDY/BSY) 20 EWDS 1 00 00XXXXXXX — High-Z 12 Instruction SB Opcode READ 1 10 EWEN 1 ERASE 1 ERAL DS21712B-page 4 Address 2004 Microchip Technology Inc. 93LC46/56/66 TABLE 1-5: Instruction INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION) Data Out Req. CLK Cycles — D15 - D0 27 Opcode READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 EWEN 1 00 11XXXXXX — High-Z 11 ERASE 1 11 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 11 ERAL 1 00 10XXXXXX — (RDY/BSY) 11 WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 27 WRAL 1 00 01XXXXXX D15 - D0 (RDY/BSY) 27 EWDS 1 00 00XXXXXX — High-Z 11 TABLE 1-6: Address Data In SB INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION) Data In Data Out Req. CLK Cycles A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20 00 11XXXXXXX — High-Z 12 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 12 1 00 10XXXXXXX — (RDY/BSY) 12 WRITE 1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 20 WRAL 1 00 01XXXXXXX D7 - D0 (RDY/BSY) 20 EWDS 1 00 00XXXXXXX — High-Z 12 Instruction SB Opcode READ 1 10 EWEN 1 ERASE 1 ERAL 2004 Microchip Technology Inc. Address DS21712B-page 5 93LC46/56/66 2.0 FUNCTIONAL DESCRIPTION When the ORG pin is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the Ready/Busy status during a programming operation. The Ready/Busy status can be verified during an erase/write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-Z state on the falling edge of the CS. 2.1 Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (Read, Write, Erase, EWEN, EWDS, ERAL and WRAL). As soon as CS is high, the device is no longer in the Standby mode. An instruction following a Start condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become “don't care” bits until a new Start condition is detected. Data In/Data Out (DI/DO) It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. 2.3 2.4 Read The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16-bit (x16 organization) or 8-bit (x8 organization) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. Start Condition The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. 2.2 After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. 2.5 Erase/Write Enable and Disable (EWEN, EWDS) The 93LC46/56/66 power up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all erase/write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. 2.6 Erase The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction. The erase cycle takes 4 ms per word typical. Data Protection During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V at nominal conditions. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. DS21712B-page 6 2004 Microchip Technology Inc. 93LC46/56/66 2.7 Write The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. The WRITE instruction is followed by 16 bits (or by 8 bits) of data which are written into the specified address. After the last data bit is put on the DI pin, CS must be brought low before the next rising edge of the CLK clock. This falling edge of CS initiates the self-timed auto-erase and programming cycle. The ERAL cycle takes (8 ms typical). 2.9 The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is ensured at 5V ±10%. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. The write cycle takes 4 ms per word typical. 2.8 The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (Tcsl). Erase All (ERAL) The ERAL instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is ensured at 5V ±10%. FIGURE 2-1: Write All (WRAL) The WRAL cycle takes 16 ms typical. READ TIMING CS CLK DI DO 1 1 High-Z 2004 Microchip Technology Inc. 0 An ••• A0 0 Dx ••• D0 Dx ••• D0 Dx ••• D0 DS21712B-page 7 93LC46/56/66 FIGURE 2-2: EWEN TIMING 6 CS 1 DI FIGURE 2-3: 0 0 1 1 ••• X X EWDS TIMING 6 CS CLK 1 DI FIGURE 2-4: 0 0 0 ••• X 0 X WRITE TIMING 6 CS CLK DI 1 0 1 An ••• A0 Dx ••• D0 11 DO High-Z Busy Ready 12 DS21712B-page 8 2004 Microchip Technology Inc. 93LC46/56/66 FIGURE 2-5: WRAL TIMING 6 CS CLK DI 1 0 0 X 1 0 ••• X Dx ••• D0 10 11 High-Z DO Busy Ready High-Z 14 Ensured by Characterization at VCC = 4.5V to +5.5V. FIGURE 2-6: ERASE TIMING 6 CS Check Status CLK 1 DI 1 1 An An-1 An-2 ••• A0 11 DO 10 High-Z Busy Ready High-Z 12 FIGURE 2-7: ERAL TIMING 6 CS Check Status CLK DI 1 0 0 1 0 X ••• X 11 DO High-Z 10 Busy Ready High-Z Ensured by Characterization at Vcc = 4.5V to +5.5V. 2004 Microchip Technology Inc. 13 DS21712B-page 9 93LC46/56/66 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Name CS PIN FUNCTION TABLE PDIP SOIC ROTATED TSSOP 1 1 3 Description Chip Select CLK 2 2 4 Serial Data Clock DI 3 3 5 Serial Data Input DO 4 4 6 Serial Data Output VSS 5 5 7 Ground ORG 6 6 8 Memory Configuration NU 7 7 1 Not Utilized Vcc 8 8 2 +1.8V to 5.5V Power Supply 3.1 Chip Select (CS) A high level selects the device. A low level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. 3.2 Serial Clock (CLK) The serial clock is used to synchronize the communication between a master device and the 93LC46/56/66. Opcode, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “don't care” if CS is low (device deselected). If CS is high, but Start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for Start condition). CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle. Note: 3.3 CS must go low between consecutive instructions. Data In (DI) Data In is used to clock in a Start bit, opcode, address and data synchronously with the CLK input. 3.4 Data Out (DO) Data Out is used in the Read mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an erase or write operation has been initiated. The Status signal is not available on DO, if CS is held low or high during the entire write or erase cycle. In all other cases DO is in the High-Z mode. If status is checked after the write/erase cycle, a pull-up resistor on DO is required to read the Ready signal. 3.5 Organization (ORG) When ORG is connected to VCC, the (x16) memory organization is selected. When ORG is tied to VSS, the (x8) memory organization is selected. ORG can only be floated for clock speeds of 1 MHz or less for the (x16) memory organization. For clock speeds greater than 1 MHz, ORG must be tied to VCC or VSS. After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed (see instruction set truth table). CLK and DI then become “don't care” inputs waiting for a new Start condition to be detected. DS21712B-page 10 2004 Microchip Technology Inc. 93LC46/56/66 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN XXXXXXXX XXXXYYWW NNN Note: * XX...X YY WW NNN 93LC46 I/PNNN YYWW Example: 93LC46 I/SNYYWW NNN 8-Lead Rotated SOIC (150 mil) Legend: Example: Example: 93LC46X I/SNYYWW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. 2004 Microchip Technology Inc. DS21712B-page 11 93LC46/56/66 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21712B-page 12 2004 Microchip Technology Inc. 93LC46/56/66 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45× c A2 A f β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L f c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2004 Microchip Technology Inc. DS21712B-page 13 93LC46/56/66 APPENDIX A: REVISION HISTORY Revision B Added note to page 1 header (Not recommended for new designs). Updated document format. DS21712B-page 14 2004 Microchip Technology Inc. 93LC46/56/66 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2004 Microchip Technology Inc. DS21712B-page 15 93LC46/56/66 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: 93LC46/56/66 Y N Literature Number: DS21712B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21712B-page 16 2004 Microchip Technology Inc. 93LC46/56/66 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device 93LC46: 1K 2.5V Microwire Serial EEPROM 93LC46X: 1K 2.5V Microwire Serial EEPROM in alternate pinouts (SN package only) 93LC46T: 1K 2.5V Microwire Serial EEPROM (Tape and Reel) 93LC46XT: 1K 2.5V Microwire Serial EEPROM (Tape and Reel) 93LC56: 2K 2.5V Microwire Serial EEPROM 93LC56X: 2K 2.5V Microwire Serial EEPROM in alternate pinouts (SN package only) 93LC56T: 2K 2.5V Microwire Serial EEPROM (Tape and Reel) 93LC56XT:2K 2.5V Microwire Serial EEPROM (Tape and Reel) 93LC66: 4K 2.5V Microwire Serial EEPROM 93LC66X: 4K 2.5V Microwire Serial EEPROM in alternate pinouts (SN package only) 93LC66T: 4K 2.5V Microwire Serial EEPROM (Tape and Reel) 93LC66XT: 4K 2.5V Microwire Serial EEPROM (Tape and Reel) Temperature Range I = -40°C to +85°C Package P SN = = Examples: a) 93LC46-I/P: 1K, 128x8 or 64x16 Serial EEPROM, PDIP package b) 93LC46-I/SN: 1K, 128x8 or 64x16 Serial EEPROM, SOIC package 93LC46T-I/SN: 1K, 128x8 or 64x16 Serial EEPROM, SOIC package, tape and reel 93LC46X-I/SN: 1K, 128x8 or 64x16 Serial EEPROM, Rotated SOIC package c) d) e) 93LC56-I/P: 2K, 256x8 or 128x16 Serial EEPROM, PDIP package f) 93LC56-I/SN: 2K, 256x8 or 128x16 Serial EEPROM, SOIC package 93LC56T-I/SN: 2K, 256x8 or 128x16 Serial EEPROM, SOIC package, tape and reel 93LC56X-I/SN: 2K, 256x8 or 128x16 Serial EEPROM, Rotated SOIC package g) h) i) 93LC66-I/P: 4K, 512x8 or 256x16 Serial EEPROM, PDIP package j) 93LC66-I/SN: 4K, 512x8 or 256x16 Serial EEPROM, SOIC package 93LC66T-I/SN: 4K, 512x8 or 256x16 Serial EEPROM, SOIC package, tape and reel 93LC66X-I/SN: 4K, 512x8 or 256x16 Serial EEPROM, Rotated SOIC package k) l) Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. DS21712B-page 17 93LC46/56/66 NOTES: DS21712B-page 18 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS21712B-page 19 WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Singapore Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. 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