M 93LC56A/B 2K 2.5V Microwire Serial EEPROM FEATURES BLOCK DIAGRAM • Single supply with operation down to 2.5V • Low power CMOS technology - 1 mA active current (typical) - 1 µA standby current (maximum) • 256 x 8 bit organization (93LC56A) • 128 x 16 bit organization (93LC56B) • Self-timed ERASE and WRITE cycles (including auto-erase) • Automatic ERAL before WRAL • Power on/off data protection circuitry • Industry standard 3-wire serial interface • Device status signal during ERASE/WRITE cycles • Sequential READ function • 1,000,000 E/W cycles guaranteed • Data retention > 200 years • 8-pin PDIP/SOIC and 8-pin TSSOP packages • Available for the following temperature ranges: - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C ADDRESS DECODER MEMORY ARRAY ADDRESS COUNTER DATA REGISTER OUTPUT BUFFER DO DI MODE DECODE LOGIC CS CLK Vcc Vss CLOCK GENERATOR DESCRIPTION The Microchip Technology Inc. 93LC56A/B are 2K-bit, low-voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC56A) or x16 bits (93LC56B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC56A/B is available in standard 8-pin DIP, surface mount SOIC, and TSSOP packages. The 93LC56AX/BX are only offered in a 150-mil SOIC package. PACKAGE TYPE DIP 3 DO 4 CS 7 NC CLK 6 NC 5 Vss 1 2 DI 3 DO 4 8 VCC NU 1 7 NC Vcc 2 NC CS 3 CLK 4 6 5 Vss 93LC56A/BX DI Vcc 93LC56A/B 2 8 93LC56A/B CLK 1 SOIC TSSOP 8 NC 7 Vss 6 DO 5 DI CS CLK DI DO 1 2 3 4 93LC56A/B CS SOIC 8 7 6 5 Vcc NC NC Vss Microwire is a registered trademark of National Semiconductor. 1997 Microchip Technology Inc. Preliminary DS21208A-page 1 93LC56A/B 1.0 1.1 ELECTRICAL CHARACTERISTICS TABLE 1-1 Name CS Maximum Ratings* VCC...................................................................................7.0V All inputs and outputs w.r.t. Vss ................ -0.6V to Vcc +1.0V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied.................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD protection on all pins................................................4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2 PIN FUNCTION TABLE Function Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output VSS Ground NC No Connect VCC Power Supply DC AND AC ELECTRICAL CHARACTERISTICS All parameters apply over the specified operating ranges unless otherwise noted Parameter High level input voltage Low level input voltage Low level output voltage Commercial (C): Industrial (I): VCC = +2.5V to +6.0V VCC = +2.5V to +6.0V Tamb = 0°C to +70°C Tamb = -40°C to +85°C Symbol Min. Max. Units VIH1 2.0 Vcc +1 V Conditions VIH2 0.7 Vcc Vcc +1 V VCC < 2.7V VIL1 -0.3 0.8 V VCC > 2.7V (Note 2) VIL2 -0.3 0.2 Vcc V VCC < 2.7V VOL1 — 0.4 V IOL = 2.1 mA; Vcc = 4.5V 2.7V ≤ VCC ≤ 5.5V (Note 2) VOL2 — 0.2 V IOL =100 µA; Vcc = Vcc Min. VOH1 2.4 — V IOH = -400 µA; Vcc = 4.5V VOH2 Vcc-0.2 — V IOH = -100 µA; Vcc = Vcc Min. Input leakage current ILI -10 10 µA VIN = VSS Output leakage current ILO -10 10 µA VOUT = VSS High level output voltage Pin capacitance (all inputs/outputs) Operating current Standby current CIN, COUT — 7 pF VIN/VOUT = 0 V (Notes 1 & 2) Tamb = +25°C, Fclk = 1 MHz ICC read — 1 500 mA µA FCLK = 2 MHz; VCC = 6.0V FCLK = 1 MHz; VCC = 3.0V ICC write — 1.5 mA ICCS — 1 µA MHz MHz ns CS = VSS VCC > 4.5V VCC < 4.5V Clock frequency FCLK — 2 1 Clock high time TCKH 250 — Clock low time TCKL 250 — ns Chip select setup time TCSS 50 — ns Relative to CLK Chip select hold time TCSH 0 — ns Relative to CLK Chip select low time TCSL 250 — ns Data input setup time TDIS 100 — ns Data input hold time TDIH 100 — ns Relative to CLK Data output delay time TPD — 400 ns Cl = 100 pF Data output disable time TCZ — 100 ns Cl = 100 pF (Note 2) Status valid time TSV — 500 ns Cl = 100 pF TWC — 6 ms ERASE/WRITE mode Program cycle time Endurance Relative to CLK TEC — 6 ms ERAL mode TWL — 15 ms WRAL mode — 1M — cycles 25°C, VCC = 5.0V, Block Mode (Note 3) Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. 3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or website. DS21208A-page 2 Preliminary 1997 Microchip Technology Inc. 93LC56A/B 2.0 PIN DESCRIPTION CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. 2.1 Chip Select (CS) After detection of a START condition the specified number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected. A high level selects the device; a low level deselects the device and forces it into standby mode. However, a programming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. 2.3 CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a RESET status. 2.2 Data In (DI) Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. Serial Clock (CLK) 2.4 The Serial Clock is used to synchronize the communication between a master device and the 93LC56A/B. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. Data Out (DO) Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. CLK is a “Don't Care” if CS is low (device deselected). If CS is high, but START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition). The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready. TABLE 2-1 INSTRUCTION SET FOR 93LC56A Instruction SB Opcode Address ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 Data In Data Out Req. CLK Cycles — (RDY/BSY) 12 ERAL 1 00 1 0 X X X X X X X — (RDY/BSY) 12 EWDS 1 00 0 0 X X X X X X X — HIGH-Z 12 EWEN 1 00 1 1 X X X X X X X — HIGH-Z 12 READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20 WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 WRAL 1 00 0 TABLE 2-2 1 X X X X X X X D7 - D0 (RDY/BSY) 20 D7 - D0 (RDY/BSY) 20 Data In Data Out Req. CLK Cycles INSTRUCTION SET FOR 93LC56B Instruction SB Opcode Address ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 11 ERAL 1 00 1 0 X X X X X X — (RDY/BSY) 11 EWDS 1 00 0 0 X X X X X X — HIGH-Z 11 EWEN 1 00 1 1 X X X X X X — HIGH-Z 11 READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27 WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 27 WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY) 27 1997 Microchip Technology Inc. Preliminary DS21208A-page 3 93LC56A/B 3.0 FUNCTIONAL DESCRIPTION 3.2 Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS. 3.1 DATA IN (DI) AND DATA OUT (DO) It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation. Under such a condition, the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin. 3.3 START Condition The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. Data Protection During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions. The EWDS and EWEN commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected. FIGURE 3-1: SYNCHRONOUS DATA TIMING VIH CS TCSS VIL TCKH TCKL TCSH VIH CLK VIL TDIS TDIH VIH DI VIL TPD TPD DO VOH (READ) VOL TCZ TSV DO VOH (PROGRAM) VOL Note: TCZ STATUS VALID AC Test Conditions: VIL = 0.4V, VIH - 2.4V. DS21208A-page 4 Preliminary 1997 Microchip Technology Inc. 93LC56A/B 3.4 ERASE 3.5 The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The ERAL instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction. FIGURE 3-2: Erase All (ERAL) The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire ERAL cycle is complete. ERASE TIMING TCSL CS CHECK STATUS CLK 1 DI 1 1 AN AN-1 AN-2 ••• A0 TCZ TSV DO HIGH-Z BUSY READY HIGH-Z TWC FIGURE 3-3: ERAL TIMING TCSL CS CHECK STATUS CLK 1 DI 0 0 1 0 X ••• X TCZ TSV DO HIGH-Z BUSY READY HIGH-Z TEC Guaranteed at Vcc = 4.5V to +6.0V. 1997 Microchip Technology Inc. Preliminary DS21208A-page 5 93LC56A/B 3.6 ERASE/WRITE Disable and Enable (EWDS/EWEN) 3.7 The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (93LC56A) or 16-bit (93LC56B) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. The 93LC56A/B powers up in the ERASE/WRITE Disable (EWDS) state. All programming modes must be preceded by an ERASE/WRITE Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWDS and EWEN instructions. FIGURE 3-4: READ EWDS TIMING TCSL CS CLK 1 DI FIGURE 3-5: 0 0 0 0 ••• X X EWEN TIMING TCSL CS CLK FIGURE 3-6: 0 1 DI 0 1 1 ••• X X READ TIMING CS CLK DI DO DS21208A-page 6 1 HIGH-Z 1 0 An ••• A0 0 Dx ••• D0 Preliminary Dx ••• D0 Dx ••• D0 1997 Microchip Technology Inc. 93LC56A/B 3.8 WRITE 3.9 The WRITE instruction is followed by 8 bits (93LC56A) or 16 bits (93LC56B) of data which are written into the specified address. After the last data bit is put on the DI pin, the falling edge of CS initiates the self-timed autoerase and programming cycle. The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. FIGURE 3-7: Write All (WRAL) The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). WRITE TIMING TCSL CS CLK DI 1 0 1 An ••• A0 Dx ••• D0 TSV HIGH-Z DO TCZ BUSY READY HIGH-Z Twc FIGURE 3-8: WRAL TIMING TCSL CS CLK DI 1 0 0 0 1 X ••• X Dx ••• D0 TSV DO HIGH-Z BUSY TCZ READY HIGH-Z TWL Guaranteed at Vcc = 4.5V to +6.0V. 1997 Microchip Technology Inc. Preliminary DS21208A-page 7 93LC56A/B NOTES: DS21208A-page 8 Preliminary 1997 Microchip Technology Inc. 93LC56A/B NOTES: 1997 Microchip Technology Inc. Preliminary DS21208A-page 9 93LC56A/B NOTES: DS21208A-page 10 Preliminary 1997 Microchip Technology Inc. 93LC56A/B 93LC56A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 93LC56A/B — /P Package: Temperature Range: Device: P SN SM ST = = = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (208 mil Body), 8-lead TSSOP, 8-lead Blank = 0 °C to +70°C I = -40°C to +85°C 93LC56A 93LC56AT 93LC56AX 93LC56AXT 93LC56B 93LC56BT 93LC56BX 93LC56BXT 2K Microwire Serial EEPROM (x8) 2K Microwire Serial EEPROM (x8) Tape and Reel 2K Microwire Serial EEPROM (x8) in alternate pinout (SN only) 2K Microwire Serial EEPROM (x8) in alternate pinout, Tape and Reel (SN only) 2K Microwire Serial EEPROM (x16) 2K Microwire Serial EEPROM (x16) Tape and Reel 2K Microwire Serial EEPROM (x16) in alternate pinout (SN only) 2K Microwire Serial EEPROM (x16) in alternate pinout, Tape and Reel (SN only) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. 3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). 1997 Microchip Technology Inc. Preliminary DS21208A-page 11 WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Hong Kong United Kingdom Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44-1628-851077 Fax: 44-1628-850259 Atlanta India Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Microchip Technology India No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Boston Korea Germany Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Müchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Shanghai Arizona Microchip Technology SRL Centro Direzionale Colleone Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hongiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Singapore Microchip Technology Taiwan Singapore Branch 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 Dayton Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Taiwan, R.O.C Los Angeles France Italy JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122 Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2-717-7175 Fax: 886-2-545-0139 Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338 New York 5/8/97 Microchip Technology Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 M All rights reserved. © 1997, Microchip Technology Incorporated, USA. 6/97 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21208A-page 12 Preliminary 1997 Microchip Technology Inc.