FDB045AN08A0
N-Channel UltraFET® Trench MOSFET
75V, 80A, 4.5mΩ
Features
Applications
• r DS(ON) = 3.9mΩ (Typ.), V GS = 10V, ID = 80A
• 42V Automotive Load Control
• Qg(tot) = 92nC (Typ.), VGS = 10V
• Starter / Alternator Systems
• Low Miller Charge
• Electronic Power Steering Systems
• Low Qrr Body Diode
• Electronic Valve Train Systems
• UIS Capability (Single Pulse and Repetitive Pulse)
• DC-DC converters and Off-line UPS
• Qualified to AEC Q101
• Distributed Power Architectures and VRMs
Formerly developmental type 82684
• Primary Switch for 24V and 48V systems
D
GATE
G
SOURCE
TO-263AB
FDB SERIES
DRAIN
(FLANGE)
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
75
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TC < 145oC, VGS = 10V)
80
A
Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 43oC/W)
19
A
Drain Current
ID
Pulsed
E AS
PD
TJ, TSTG
Figure 4
A
Single Pulse Avalanche Energy (Note 1)
600
mJ
Power dissipation
310
W
Derate above 25oC
2.0
W/oC
Operating and Storage Temperature
o
-55 to 175
C
Thermal Characteristics
0.48
o
C/W
Thermal Resistance Junction to Ambient TO-263 (Note 2)
62
o
C/W
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
43
o
C/W
RθJC
Thermal Resistance Junction to Case TO-263
RθJA
RθJA
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
FDB045AN08A0 Rev. A
FDB045AN08A0
April 2002
Device Marking
FDB045AN08A0
Device
FDB045AN08A0
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
75
-
-
V
-
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
-
4
V
VDS = 60V
VGS = 0V
TC = 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
2
ID = 80A, VGS = 10V
-
0.0039 0.0045
ID = 37A, VGS = 6V
-
0.0056 0.0084
ID = 80A, VGS = 10V,
TJ = 175oC
-
0.008
0.011
-
6600
-
-
1000
-
pF
-
240
-
pF
nC
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 25V, VGS = 0V,
f = 1MHz
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
VDD = 40V
ID = 80A
Ig = 1.0mA
pF
92
138
-
11
17
nC
-
27
-
nC
-
16
-
nC
-
21
-
nC
ns
Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
160
td(ON)
Turn-On Delay Time
-
18
-
ns
tr
Rise Time
-
88
-
ns
td(OFF)
Turn-Off Delay Time
-
40
-
ns
tf
Fall Time
-
45
-
ns
tOFF
Turn-Off Time
-
-
128
ns
V
VDD = 40V, ID = 80A
VGS = 10V, RGS = 3.3Ω
Drain-Source Diode Characteristics
ISD = 80A
-
-
1.25
ISD = 40A
-
-
1.0
V
Reverse Recovery Time
ISD = 75A, dISD/dt = 100A/µs
-
-
53
ns
Reverse Recovered Charge
ISD = 75A, dISD/dt = 100A/µs
-
-
54
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 0.48mH, IAS = 50A.
2: Pulse Width = 100s
©2002 Fairchild Semiconductor Corporation
FDB045AN08A0 Rev. A
FDB045AN08A0
Package Marking and Ordering Information
FDB045AN08A0
Typical Characteristics TC = 25°C unless otherwise noted
1.2
200
CURRENT LIMITED
BY PACKAGE
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
160
120
80
40
0.2
0
0
25
50
75
100
150
125
0
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (o C)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)
1000
CURRENT AS FOLLOWS:
100
175 - TC
I = I25
VGS = 10V
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
FDB045AN08A0 Rev. A
FDB045AN08A0
Typical Characteristics TC = 25°C unless otherwise noted
500
2000
10µs
1000
100
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100µs
1ms
10ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
DC
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
0.1
0.1
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
.01
100
Figure 6. Unclamped Inductive Switching
Capability
150
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VGS = 10V
90
TJ = 175oC
60
TJ = -55oC
TJ = 25oC
VGS = 6V
90
60
VGS = 5V
TC = 25o C
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
30
30
0
4.0
VGS = 7V
120
ID, DRAIN CURRENT (A)
120
0
4.5
5.0
5.5
VGS , GATE TO SOURCE VOLTAGE (V)
0
6.0
Figure 7. Transfer Characteristics
0.5
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
1.5
Figure 8. Saturation Characteristics
7
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE(mΩ)
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Forward Bias Safe Operating Area
ID , DRAIN CURRENT (A)
If R = 0
tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
VGS = 6V
6
5
VGS = 10V
4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
VGS = 10V, ID =80A
3
0
20
40
ID, DRAIN CURRENT (A)
60
80
Figure 9. Drain to Source On Resistance vs Drain
Current
©2002 Fairchild Semiconductor Corporation
0.5
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDB045AN08A0 Rev. A
FDB045AN08A0
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.15
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
1.05
1.00
0.95
0.90
-80
200
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (o C)
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10
VGS , GATE TO SOURCE VOLTAGE (V)
10000
CISS = CGS + CGD
C, CAPACITANCE (pF)
1.10
COSS ≅ CDS + C GD
1000
CRSS = CGD
VDD = 40V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 80A
ID = 10A
2
VGS = 0V, f = 1MHz
0
100
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2002 Fairchild Semiconductor Corporation
75
0
25
50
Qg , GATE CHARGE (nC)
75
100
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
FDB045AN08A0 Rev. A
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
IAS
+
RG
REQUIRED PEAK IAS
VDD
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
VGS
VGS = 10V
+
Qgs2
VDD
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
FDB045AN08A0 Rev. A
FDB045AN08A0
Test Circuits and Waveforms
FDB045AN08A0
Thermal Resistance vs. Mounting Pad Area
(T
–T )
JM
A
P D M = ----------------------------R θ JA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P DM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
RθJA = 26.51+ 19.84/(0.262+Area)
60
RθJA (o C/W)
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
R
θ JA
19.84
( 0.262 + Area )
= 26.51 + -------------------------------------
©2002 Fairchild Semiconductor Corporation
(EQ. 2)
FDB045AN08A0 Rev. A
.SUBCKT FDB045AN08A0 2 1 3 ;
CA 12 8 1.5e-9
CB 15 14 1.5e-9
CIN 6 8 6.4e-9
rev March 2002
LDRAIN
DPLCAP
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
RSLC1
51
5
51
EVTHRES
+ 19 8
+
LGATE
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 4.81e-9
LSOURCE 3 7 4.63e-9
ESLC
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
EBREAK 11 7 17 18 82.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
DRAIN
2
5
EVTEMP
RGATE +
18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9e-4
RGATE 9 20 1.36
RLDRAIN 2 5 10
RLGATE 1 9 48.1
RLSOURCE 3 7 46.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.3e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
S1A
12
S2A
13
8
14
13
S1B
CA
15
17
18
RVTEMP
CB
6
8
5
8
EDS
-
19
VBAT
+
IT
14
+
+
EGS
RLSOURCE
RBREAK
S2B
13
SOURCE
3
-
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))}
.MODEL DBODYMOD D (IS = 2.4e-11 N = 1.04 RS = 1.76e-3 TRS1 = 2.7e-3 TRS2 = 2e-7 XTI=3.9 CJO = 4.35e-9 TT = 1e-8
M = 5.4e-1)
.MODEL DBREAKMOD D (RS = 1.5e-1 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 1.35e-9 IS = 1e-30 N = 10 M = 0.53)
.MODEL MMEDMOD NMOS (VTO = 3.7 KP = 9 IS =1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36)
.MODEL MSTROMOD NMOS (VTO = 4.4 KP = 250 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 3.05 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36e1 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = -9e-7)
.MODEL RDRAINMOD RES (TC1 = 1.9e-2 TC2 = 4e-5)
.MODEL RSLCMOD RES (TC1 = 1.3e-3 TC2 = 1e-5)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -6e-3 TC2 = -1.9e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.4e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.0 VOFF= -1.5)
VON = -1.5 VOFF= -4.0)
VON = -1.0 VOFF= 0.5)
VON = 0.5 VOFF= -1.0)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
FDB045AN08A0 Rev. A
FDB045AN08A0
PSPICE Electrical Model
REV March 2002
template FDB045AN08A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.4e-11, n1 = 1.04, rs = 1.76e-3, trs1 = 2.7e-3, trs2 = 2e-7, xti = 3.9, cjo = 4.35e-9, tt = 1e-8, m = 5.4e-1)
dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 1.35e-9, isl =10e-30, nl =10, m = 0.53)
m..model mmedmod = (type=_n, vto = 3.7, kp = 9, is =1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 4.4, kp = 250, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 3.05, kp = 0.03, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -1.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)
LDRAIN
DPLCAP
10
c.ca n12 n8 = 1.5e-9
c.cb n15 n14 = 1.5e-9
c.cin n6 n8 = 6.4e-9
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
MWEAK
EBREAK
+
17
18
-
MMED
MSTRO
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
CIN
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
RBREAK
15
14
13
S1B
CA
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -9e-7
res.rdrain n50 n16 = 9e-4, tc1 = 1.9e-2, tc2 = 4e-5
res.rgate n9 n20 = 1.36
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 48.1
res.rlsource n3 n7 = 46.3
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.3e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -6e-3, tc2 = -1.9e-5
DBREAK
50
-
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.81e-9
l.lsource n3 n7 = 4.63e-9
DRAIN
2
5
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 82.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10))
}
}
©2002 Fairchild Semiconductor Corporation
FDB045AN08A0 Rev. A
FDB045AN08A0
SABER Electrical Model
th
JUNCTION
REV 23 March 2002
FFDB045AN08A0T
CTHERM1 th 6 6.45e-3
CTHERM2 6 5 3e-2
CTHERM3 5 4 1.4e-2
CTHERM4 4 3 1.65e-2
CTHERM5 3 2 4.85e-2
CTHERM6 2 tl 1e-1
RTHERM1
CTHERM1
6
RTHERM1 th 6 3.24e-3
RTHERM2 6 5 8.08e-3
RTHERM3 5 4 2.28e-2
RTHERM4 4 3 1e-1
RTHERM5 3 2 1.1e-1
RTHERM6 2 tl 1.4e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDB045AN08A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.45e-3
ctherm.ctherm2 6 5 = 3e-2
ctherm.ctherm3 5 4 = 1.4e-2
ctherm.ctherm4 4 3 = 1.65e-2
ctherm.ctherm5 3 2 = 4.85e-2
ctherm.ctherm6 2 tl = 1e-1
rtherm.rtherm1 th 6 = 3.24e-3
rtherm.rtherm2 6 5 = 8.08e-3
rtherm.rtherm3 5 4 = 2.28e-2
rtherm.rtherm4 4 3 = 1e-1
rtherm.rtherm5 3 2 = 1.1e-1
rtherm.rtherm6 2 tl = 1.4e-1
}
CTHERM3
RTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2002 Fairchild Semiconductor Corporation
CASE
FDB045AN08A0 Rev. A
FDB045AN08A0
SPICE Thermal Model
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS™
EnSigna™
FACT™
FACT Quiet Series™
FAST®
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER ®
SMART START™
SPM™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET®
VCX™
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
2. A critical component is any component of a life support
As used herein:
device or system whose failure to perform can be
1. Life support devices or systems are devices or systems
reasonably expected to cause the failure of the life support
which, (a) are intended for surgical implant into the body,
device or system, or to affect its safety or effectiveness.
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
FDB045AN08A0 Rev. H5