TI SN65LVDS179D

SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
D
D
D
D
D
D
D
D
D
D
D
Meets or Exceeds the Requirements of
ANSI TIA/EIA-644-1995 Standard
Signaling Rates up to 400 Mbit/s
Bus-Terminal ESD Exceeds 12 kV
Operates from a Single 3.3-V Supply
Low-Voltage Differential Signaling With
Typical Output Voltages of 350 mV and a
100 Ω Load
Propagation Delay Times
– Driver: 1.7 ns Typ
– Receiver: 3.7 ns Typ
Power Dissipation at 200 MHz
– Driver: 25 mW Typical
– Receiver: 60 mW Typical
LVTTL Input Levels are 5 V Tolerant
Driver is High Impedance When Disabled or
With VCC < 1.5 V
Receiver has Open-Circuit Fail Safe
Surface-Mount Packaging
– D Package (SOIC)
– DGK Package (MSOP) (’LVDS79 Only)
description
The
SN65LVDS179,
SN65LVDS180,
SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage
differential signaling (LVDS) to achieve signaling
rates as high as 400 Mbps. The TIA/EIA-644
standard compliant electrical interface provides a
minimum differential output voltage magnitude of
247 mV into a 100 Ω load and receipt of 100 mV
signals with up to 1 V of ground potential
difference between a transmitter and receiver.
The intended application of this device and
signaling technique is for point-to-point baseband
data transmission over controlled impedance
media of approximately 100 Ω characteristic
impedance. The transmission media may be
printed-circuit board traces, backplanes, or
cables. (Note: The ultimate rate and distance of
data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to
the environment, and other application specific
characteristics).
SN65LVDS179D (Marked as DL179 or LVD179)
SN65LVDS179DGK (Marked as S79)
(TOP VIEW)
3
VCC
R
D
GND
1
8
2
7
3
6
4
5
D
A
B
Z
Y
5
6
8
2
R
7
Y
Z
A
B
SN65LVDS180D (Marked as LVDS180)
(TOP VIEW)
NC
R
RE
DE
D
GND
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
5
4
DE
4
13
5
12
6
11
7
10
8
9
1Z
DE
2Z
2Y
2D
12
2
R
3
1R
4
13
5
12
6
11
7
10
8
9
1Z
2DE
2Z
2Y
2D
11
14
13
10
11
2
1
4
RE
6
5
2R
SN65LVDS051D (Marked as LVDS051)
(TOP VIEW)
15
1D
1B 1
16 VCC
4
1DE
1A 2
15 1D
3
1R 3
1R
14 1Y
1DE
2R
2A
2B
GND
9
2D
7
14
13
2
1
10
11
12
2DE
6
5
2R
Y
Z
3
RE
SN65LVDS050D (Marked as LVDS050)
15
(TOP VIEW)
1D
12
1B 1
16 VCC
DE
9
1A 2
15 1D
2D
1R 3
14 1Y
RE
2R
2A
2B
GND
9
10
D
7
A
B
1Y
1Z
2Y
2Z
1A
1B
2A
2B
1Y
1Z
1A
1B
2Y
2Z
2A
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
description (continued)
AVAILABLE OPTIONS
PACKAGE
TA
– 40°C to 85°C
SMALL OUTLINE
(D)
SMALL OUTLINE
(DGK)
SN65LVDS050D
—
SN65LVDS051D
—
SN65LVDS179D
SN65LVDS179DGK
SN65LVDS180D
—
NOTE:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics
of the media, the noise coupling to the environment, and other application specific characteristics.
The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are characterized for operation from
–40°C to 85°C.
Function Tables
SN65LVDS179 RECEIVER
INPUTS
OUTPUT
VID = VA – VB
VID ≥ 100 mV
R
–100 MV < VID < 100 mV
?
VID ≤ –100 mV
Open
H
H
L
H = high level, L = low level, ? = indeterminate
SN65LVDS179 DRIVER
INPUT
OUTPUTS
D
Y
Z
L
L
H
H
H
L
Open
L
H
H = high level, L = low level
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 RECEIVER
OUTPUT
INPUTS
VID = VA – VB
VID ≥ 100 mV
RE
R
L
H
–100 MV < VID < 100 mV
L
?
VID ≤ –100 mV
Open
L
L
L
H
X
H
Z
H = high level, L = low level, Z = high impedance,
X = don’t care
2
POST OFFICE BOX 655303
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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 DRIVER
INPUTS
OUTPUTS
D
DE
Y
Z
L
H
L
H
H
H
H
L
Open
H
L
H
X
L
Z
Z
H = high level, L = low level, Z = high impedance,
X = don’t care
equivalent input and output schematic diagrams
VCC
VCC
VCC
300 kΩ
50 Ω
5Ω
10 kΩ
D or RE
Input
Y or Z
Output
50 Ω
DE
Input
7V
7V
7V
300 kΩ
VCC
VCC
300 kΩ
300 kΩ
5Ω
A Input
R Output
B Input
7V
7V
7V
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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Voltage range (D, R, DE, RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Electrostatic discharge: Y, Z, A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . . CLass 3, A:12 kV, B:600 V
All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B:500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see dissipation rating table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C†
TA = 85°C
POWER RATING
D8
725 mW
5.8 mW/°C
377 mW
D14 or D16
950 mW
7.8 mW/°C
494 mW
DGK
424 mW
3.4 mW/°C
220 mW
† This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
Low-level input voltage, VIL
MAX
UNIT
3.6
V
V
0.8
Ť Ť
Magnitude of differential input voltage, VID
0.1
V
ID
2
Common–mode input voltage, VIC (see Figure 6)
Operating free–air temperature, TA
2.4
V
Ť Ť
0.6
V
* V2ID
V
VCC–0.8
85
–40
°C
device electrical characteristics over recommended operating conditions (unless otherwise
noted)
TYP†
MAX
No receiver load, Driver RL = 100 Ω
9
12
Driver and receiver enabled, No receiver load, Driver RL = 100 Ω
9
12
PARAMETER
SN65LVDS179
SN65LVDS180
ICC
Supply
current
SN65LVDS050
SN65LVDS051
TEST CONDITIONS
Driver enabled, Receiver disabled, RL = 100 Ω
5
7
Driver disabled, Receiver enabled, No load
1.5
2
Disabled
0.5
1
Drivers and receivers enabled, No receiver loads, Driver RL = 100 Ω
12
20
Drivers enabled, Receivers disabled, RL = 100 Ω
10
16
3
6
Drivers disabled, Receivers enabled, No loads
Disabled
0.5
1
Drivers enabled, No receiver loads, Driver RL = 100 Ω
12
20
3
6
Drivers disabled, No loads
† All typical values are at 25°C and with a 3.3-V supply.
4
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
mA
mA
mA
mA
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude between logic
states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage between
logic states
VOC(PP)
Peak-to-peak common-mode output voltage
RL = 100Ω,
100Ω
See Figure 1 and Figure 2
MIN
TYP
MAX
247
340
454
–50
1.125
DE
See Figure 3
IIH
High level input current
High-level
IIL
Low level input current
Low-level
IOS
Short circuit output current
Short-circuit
VOY or VOZ = 0 V
VOD = 0 V
IOZ
High impedance output current
High-impedance
VOD = 600 mV
VO = 0 V or VCC
IO(OFF)
CIN
Power-off output current
VCC = 0 V, VO = 3.6 V
D
DE
D
50
1.2
–50
VIH = 5 V
VIL = 0
0.8
8V
1.375
mV
V
50
mV
mV
50
150
– 0.5
– 20
2
20
– 0.5
–10
2
10
3
10
3
10
±1
±1
±1
Input capacitance
UNIT
3
µA
µA
mA
µA
µA
pF
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VITH+
VITH–
Positive-going differential input voltage threshold
VOH
VOL
High-level output voltage
Negative-going differential input voltage threshold
Low-level output voltage
II
Input current (A or B inputs)
II(OFF)
IIH
Power-off input current (A or B inputs)
IIL
IOZ
Low-level input current (enables)
High-level input current (enables)
High-impedance output current
See Figure 5 and Table 1
TYP†
MAX
100
–100
IOH = –8 mA
IOL = 8 mA
2.4
VI = 0
VI = 2.4 V
–2
–11
–1.2
–3
UNIT
mV
V
0.4
–20
V
µA
VCC = 0
VIH = 5 V
±20
µA
±10
µA
VIL = 0.8 V
VO = 0 or 5 V
±10
µA
±10
µA
CI
Input capacitance
† All typical values are at 25°C and with a 3.3-V supply.
POST OFFICE BOX 655303
MIN
5
• DALLAS, TEXAS 75265
pF
5
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low-to-high-level output
tr
tf
Differential output signal rise time
tsk(p)
tsk(o)
MIN
Propagation delay time, high-to-low-level output
RL = 100Ω,
CL = 10 pF
pF,
See Figure 6
Differential output signal fall time
Pulse skew (|tpHL – tpLH|)‡
TYP†
MAX
1.7
2.7
ns
1.7
2.7
ns
0.8
1
ns
0.8
1
ns
300
UNIT
ps
Channel-to-channel output skew§
150
tPZH
tPZL
Propagation delay time, high-impedance-to-high-level output
4.3
10
ns
4.6
10
ns
tPHZ
tpLZ
Propagation delay time, high-level-to-high-impedance output
3.1
10
ns
3.4
10
ns
Propagation delay time, high-impedance-to-low-level output
See Figure 7
Propagation delay time, low-level-to-high-impedance output
ps
† All typical values are at 25°C and with a 3.3-V.
‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
§ tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
¶ tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
tPLH
tPHL
tsk(p)
tr
TEST CONDITIONS
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew (|tpHL – tpLH|)‡
CL = 10 pF, See Figure 6
MIN
TYP†
MAX
3.7
4.5
ns
3.7
4.5
ns
0.3
UNIT
ns
Output signal rise time
0.7
1.5
ns
tf
tPZH
Output signal fall time
0.9
1.5
ns
Propagation delay time, high-level-to-high-impedance output
2.5
ns
tPZL
tPHZ
Propagation delay time, low-level-to-low-impedance output
2.5
ns
7
ns
Propagation delay time, high-impedance-to-high-level output
See Figure 7
tPLZ
Propagation delay time, low-impedance-to-high-level output
4
ns
† All typical values are at 25°C and with a 3.3-V.
‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
§ tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
¶ tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
driver
IOY
Driver Enable
Y
II
A
IOZ
VOD
V
VOY
Z
VI
OY
) VOZ
2
VOC
VOZ
Figure 1. Driver Voltage and Current Definitions
Driver Enable
Y
VOD
Input
100 Ω
±1%
Z
CL = 10 pF
(2 Places)
2V
1.4 V
0.8 V
Input
tPHL
tPLH
100%
80%
Output
VOD(H)
0V
VOD(L)
20%
0%
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
49.9 Ω, ±1% (2 Places)
Driver Enable
3V
Y
Input
0V
Z
VOC
VOC(PP)
CL = 10 pF
(2 Places)
VOC(SS)
VOC
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
49.9 Ω, ±1% (2 Places)
Y
0.8 V or 2 V
Z
DE
1.2 V
CL = 10 pF
(2 Places)
VOY
VOZ
2V
1.4 V
0.8 V
DE
VOY or VOZ
tPZH
~1.4 V
1.25 V
1.2 V
D at 2 V and input to DE
1.2 V
1.15 V
~1 V
D at 0.8 V and input to DE
tPHZ
VOZ or VOY
tPZL
tPLZ
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver
A
V
IA
) VIB
R
VID
2
VIA
B
VIC
VO
VIB
Figure 5. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
(V)
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMONMODE INPUT VOLTAGE
(V)
VIA
1.25
VIB
1.15
VID
100
VIC
1.2
1.15
1.25
– 100
1.2
2.4
2.3
100
2.35
2.3
2.4
– 100
2.35
0.1
0
100
0.05
0
0.1
– 100
0.05
1.5
0.9
600
1.2
0.9
1.5
– 600
1.2
2.4
1.8
600
2.1
1.8
2.4
– 600
2.1
0.6
0
600
0.3
0
0.6
– 600
0.3
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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
VID
VIA
VIB
CL
10 pF
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
– 0.4 V
tPHL
VO
tPLH
VOH
2.4 V
1.4 V
0.4 V
VOL
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 6. Timing Test Circuit and Waveforms
10
POST OFFICE BOX 655303
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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
1.2 V
B
500 Ω
A
Inputs
RE
CL
10 pF
+
–
VO
VTEST
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
2.5 V
VTEST
A
1V
2V
1.4 V
RE
0.8 V
tPZL
tPZL
tPLZ
2.5 V
1.4 V
R
VOL +0.5 V
VOL
0V
VTEST
A
1.4 V
2V
RE
1.4 V
0.8 V
tPZH
R
tPZH
tPHZ
VOH
1.4 V
VOH –0.5 V
0V
Figure 7. Enable/Disable Time Test Circuit and Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
VIC – Common-Mode Input Voltage – V
VCC > 3.15 V
VCC = 3 V
2
1.5
1
0.5
MIN
0
0
0.1
0.2
0.5
0.4
0.3
0.6
|VID|– Differential Input Voltage – V
Figure 8
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
VCC = 3.3 V
TA = 25°C
VOH – High-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
4
3
2
1
0
0
2
4
6
IOL – Low-Level Output Current – mA
VCC = 3.3 V
TA = 25°C
3
2.5
2
1.5
1
0.5
0
–4
–3
Figure 9
12
–2
Figure 10
POST OFFICE BOX 655303
–1
IOH – High-Level Output Current – mA
• DALLAS, TEXAS 75265
0
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
TA = 25°C
VOH – High-Level Output Voltage – V
VOL – Low-Level Output Votlage – V
5
4
3
2
1
10
20
30
40
50
IOL – Low-Level Output Current – mA
2
1
0
–80
0
0
3
60
–60
–40
–20
IOH – High-Level Output Current – mA
Figure 12
Figure 11
DRIVER
DRIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2
t PLH – Low-To-High Propagation Delay Time – ns
2.5
t PHL – High-To-Low Propagation Delay Time – ns
0
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
1.5
–50
–30
–10
10
50
30
70
TA – Free-Air Temperature – °C
90
2.5
2
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
1.5
–50
–30
Figure 13
10
–10
50
30
70
TA – Free-Air Temperature – °C
90
Figure 14
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13
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
RECEIVER
RECEIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE–AIR TEMPERATURE
4.5
VCC = 3.3 V
4
VCC = 3 V
3.5
VCC = 3.6 V
3
2.5
–50
–30
–10
10
50
30
70
TA – Free–Air Temperature – °C
90
t PLH – Low-To-High Level Propagation Delay Time – ns
t PLH – High-To-Low Level Propagation Dealy Time – ns
TYPICAL CHARACTERISTICS
4.5
VCC = 3 V
4
VCC = 3.3 V
3.5
VCC = 3.6 V
3
2.5
–50
–30
Figure 15
14
10
–10
50
30
70
TA – Free-Air Temperature – °C
Figure 16
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90
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the
power and dual supply requirements.
Transmission Distance – m
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
100M
Data Rate – Hz
Figure 17. Data Transmission Distance Versus Rate
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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and
100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt
100 Ω Typ
Y
B
VIT ≈ 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
16
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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°– 6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15 MIN
0,10
4073329/A 02/97
NOTES: A.
B.
C.
D.
18
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-187
POST OFFICE BOX 655303
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