SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134B – DECEMBER 1982 – REVISED MAY 1997 D D D D D D 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active-High Decoder Enable Input Simplifies Expansion Expandable for n-Bit Applications Four Distinct Functional Modes Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54HC259 . . . J OR W PACKAGE SN74HC259 . . . D, N, OR PW PACKAGE (TOP VIEW) S0 S1 S2 Q0 Q1 Q2 Q3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLR G D Q7 Q6 Q5 Q4 SN54HC259 . . . FK PACKAGE (TOP VIEW) S1 S0 NC VCC CLR D description Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. S2 Q0 NC Q1 Q2 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 G D NC Q7 Q6 Q3 GND NC Q4 Q5 These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs. NC – No internal connection The SN54HC259 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC259 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134B – DECEMBER 1982 – REVISED MAY 1997 Function Tables FUNCTION CLR G OUTPUT OF ADDRESSED LATCH H L D QiO H H QiO QiO Memory L L D L 8-line demultiplexer L H L L Clear INPUTS EACH OTHER OUTPUT FUNCTION Addressable latch LATCH SELECTION SELECT INPUTS 2 S2 S1 S0 LATCH ADDRESSED L L L 0 L L H 1 L H L 2 L H H 3 H L L 4 H L H 5 H H L 6 H H H 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134B – DECEMBER 1982 – REVISED MAY 1997 logic symbol† S0 S1 S2 G D CLR 1 0 2 3 14 13 15 8M 0 7 2 G8 Z9 Z10 4 9, 0D 10, 0R 5 9, 1D 10, 1R 6 9, 2D 10, 2R 7 9, 3D 10, 3R 9 9, 4D 10, 4R 10 9, 5D 10, 5R 11 9, 6D 10, 6R 12 9, 7D 10, 7R Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134B – DECEMBER 1982 – REVISED MAY 1997 logic diagram (positive logic) S0 1D C1 1 4 Q0 1R 1D C1 5 Q1 1R S1 1D C1 2 6 Q2 1R 1D C1 7 Q3 1R S2 3 1D C1 9 Q4 1R 1D C1 10 Q5 1R G 14 1D C1 11 Q6 1R D 13 1D C1 1R CLR 15 Pin numbers shown are for the D, J, N, PW, and W packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 Q7 SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134B – DECEMBER 1982 – REVISED MAY 1997 logic symbol, each internal latch D 1D C C1 R 1R Q logic diagram, each internal latch (positive logic) C TG D C C Q C C C TG R C absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134B – DECEMBER 1982 – REVISED MAY 1997 recommended operating conditions SN54HC259 VCC Supply voltage VIH VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage Input transition (rise and fall) time TA Operating free-air temperature NOM MAX 2 5 6 VCC = 2 V VCC = 4.5 V VCC = 6 V MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 VCC = 4.5 V VCC = 6 V tt SN74HC259 MIN UNIT V V 4.2 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC 0 1000 0 1000 0 500 0 500 0 400 0 400 –55 125 –40 85 V V V ns °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS Ci 6 TA = 25°C TYP MAX SN54HC259 MIN MAX SN74HC259 MIN MAX UNIT 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = –4 mA IOH = –5.2 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 3 10 10 10 pF VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, MIN IOH = –20 µA IOL = 4 mA IOL = 5.2 mA II ICC VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134B – DECEMBER 1982 – REVISED MAY 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC CLR low tw Pulse duration G low Setup time, data or address before G↑ ↑ tsu Hold time, data or address after G↑ ↑ th TA = 25°C MIN MAX SN54HC259 MIN MAX SN74HC259 MIN 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 75 115 95 4.5 V 15 23 19 6V 13 20 16 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 MAX UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25°C MIN TYP MAX SN54HC259 SN74HC259 PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 60 150 225 190 tPHL CLR Any Q 4.5 V 18 30 45 38 6V 14 26 38 32 2V 56 130 195 165 4.5 V 17 26 39 33 6V 13 22 33 28 2V 74 200 300 250 4.5 V 21 40 60 50 6V 17 34 51 43 2V 66 170 255 215 4.5 V 20 34 51 43 6V 16 29 43 37 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 Data tpd Address G Any Q Any Q Any Q tt Any MIN MAX MIN MAX UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per latch POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 33 UNIT pF 7 SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134B – DECEMBER 1982 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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