SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 FEATURES D Replaces OR-ing Diodes D Operating Supply Range of −12 V to −80 V D Withstands Transients to –100 V D Programmable Current Limit D Programmable Linear Inrush Slew Rate D Programmable UV/OV Thresholds D Programmable UV and OV Hysteresis D Fault Timer to Eliminate Nuisance Trips D Power Good and Fault Outputs D 14-Pin SOIC and TSSOP Package DESCRIPTION The TPS2350 is a hot swap power manager optimized for replacing OR-ing diodes in redundant power −48-V systems. The TPS2350 operates with supply voltages from −12 V to −80 V, and withstands spikes to −100 V. The TPS2350 uses two power FETs as low voltage drop diodes to efficiently select between two redundant power supplies. This minimizes system power dissipation and also minimizes voltage drop through the power management chain. The TPS2350 also uses a third power FET to provide load current slew rate control and peak current limiting that is programmed by one resistor and one capacitor. The device also provides a power good output to enable down-stream power converters and a fault output to indicate load problems. APPLICATIONS D −48-V Distributed Power Systems D Central Office Switching D ONET D Base Stations TYPICAL APPLICATION DIAGRAM RLOAD 1 Power Good Fault 3 UV 12 PG 2 FLT 4 CLOAD RTN GAT 11 TPS2350 Q1 RSENSE 0.01 Ω SENSE 10 SOURCE 7 GATA 9 GATB 8 OV FLTTIM RAMP 5 6 −VINA −VINB 14 13 −VINB CFLT CRAMP !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- −VINA UDG−03125 Copyright 2003, Texas Instruments Incorporated www.ti.com 1 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted)(1) PARAMETER TPS2350 UNIT Input voltage range, RTN (2) −0.3 to 100 Input voltage range, −VINA to –VINB −100 to 100 Input voltage range, FLTTIM, RAMP, SENSE, OV, UV (2) −0.3 to 15 Output voltage range, FLT, PG (2)(3) −0.3 to 100 Continuous output current, FLT, PG 10 Continuous total power dissipation V mA TBD Operating junction temperature range, TJ −55 to 125 Storage temperature range, Tstg −65 to 150 °C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the more negative of –VINA and −VINB (unless otherwise noted). (3) With 10 kΩ minimum series resistance. Range limited to –0.3V to 80V from low impedance source. SOIC/TSSOP-14 PACKAGE (TOP VIEW) RTN FLT UV OV FLTTIM RAMP SOURCE 1 2 3 4 5 6 7 ELECTROSTATIC DISCHARGE (ESD) PROTECTION Human body model (HBM) Charged device model (CDM) −VINA −VINB PG GAT SENSE GATA GATB 14 13 12 11 10 9 8 AVAILABLE OPTIONS MIN UNIT 2 kV (4) 1.5 TA PACKAGE SOIC−14(4) PART NUMBER −40°C to 85°C TSSOP−14(4) TPS2350PW TPS2350D The D and PW packages are also available taped and reeled. Add an R suffix to the device type (i.e. TPS2350DR). RECOMMENDED OPERATING CONDITIONS MIN NOM MAX Input supply, −VINA, −VINB to RTN −80 −48 −12 V Operating junction temperature range −40 85 _C DISSIPATION RATING TABLE 2 PACKAGE TA < 25 _C POWER RATING DERATING FACTOR ABOVE TA = 25 _C TA = 85 _C POWER RATING SOIC−14 750 mW 7.5 mW/C 300 mW TSSOP−14 750 mW 7.5 mW/C 300 mW www.ti.com UNIT SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS −VINA = −48 V, −VINB = 0 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, SOURCE = more negative of –VINA and –VINB, all outputs unloaded, TA = −40 _C to 85 _C (unless otherwise noted)†‡ Input Supply PARAMETER TEST CONDITIONS ICC1A ICC2A Supply current −VINA = −48 V, −VINB = 0 V Supply current −VINA = −80 V, −VINB = 0 V ICC1B ICC2B Supply current −VINB = −48 V, −VINA = 0 V Supply current −VINB = −80 V, −VINA = 0 V VUVLO_I VHYST Internal UVLO threshold voltage To GAT pull up Internal UVLO hysteresis voltage MIN TYP MAX 1000 1500 2000 1000 1500 UNIT µA A 2000 −11.8 −10 −8.0 V 50 240 500 mV UNIT Overvoltage and Undervoltage Inputs (OV and UV) PARAMETER VTHUV UV threshold voltage, UV rising, to –VINA MIN TYP MAX To GAT pull up, 25 _C TEST CONDITIONS 1.391 1.400 1.409 To GAT pull up, 0 to 70 _C 1.387 1.400 1.413 To GAT pull up, −40 to 85 _C 1.384 1.400 1.419 −10 −9 IHYSUV IILUV UV hysteresis UV = −45.5 V −11 UV low−level input current UV = −47 V −1 VTHOV IHYSOV OV threshold voltage, OV rising, to −VINA To GAT pull up 1.376 1.400 1.426 OV hysteresis OV = −45.5 V −11.1 −10 −8.6 IILOV OV low−level input current OV = −47 V 1 −1 1 V µA A V A µA Linear Curent Amplifier (LCA) PARAMETER VOH TEST CONDITIONS MIN TYP MAX UNIT 17 V High level output, GAT−SOURCE SENSE = SOURCE 11 14 ISINK_f GAT sink current in fault SENSE – SOURCE = 80 mV, GAT = −43 V, FLTTIME = 5 V 30 75 ISINK_l GAT sink current in linear mode SENSE – SOURCE = 80 mV, GAT = −43 V, FLTTIME = 2 V IIN SENSE input current 0.0 V < SENSE – SOURCE < 0.2 V −1 Reference clamp voltage, SENSE − VREF_K SOURCE RAMP – SOURCE = 6 V 34 VIO RAMP – SOURCE = 0 V −7 Input offset voltage, SENSE − SOURCE mA 5 10 1 42 50 µA mV 9 Ramp Generator PARAMETER ISRC1 ISRC2 MIN TYP MAX UNIT RAMP source current, slow turn-on rate RAMP − SOURCE = 0.25 V TEST CONDITIONS −800 −550 −300 nA RAMP source current, normal rate RAMP − SOURCE = 1 V and 3 V −11.3 −10 −8.5 µA 5 mV 10.7 mV/V VOL Low-level output voltage UV = SOURCE AV Voltage gain, relative to SENSE 0 V < RAMP − SOURCE < 5 V † All voltages are with respect to RTN unless otherwise stated. ‡ Currents are positive into and negative out of the specified terminal. www.ti.com 9.5 10 3 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS −VINA = −48 V, −VINB = 0 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, SOURCE = more negative of –VINA and –VINB, all outputs unloaded, TA = −40 _C to 85 _C (unless otherwise noted)†‡ Overload Comparator PARAMETER VTH_OL tRSP TEST CONDITIONS SENSE current overload threshold Response time MIN TYP MAX UNIT 100 120 140 mV 2 4 7 µs SENSE – SOURCE = 200 mV Fault Timer PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5 mV µA VOL ICHG FLTTIM low−level output voltage, to −VINA UV = −48 V FLTTIM charging current, current limit mode FLTTIM − SOURCE = 2 V VFLT VRST FLTTIM fault threshold voltage to SOURCE IDSG FLTTIM Discharge current, retry mode FLTTIM – SOURCE = 2 V 0.38 0.75 D Output duty cycle during retry cycles SENSE − SOURCE = 80 mV, FLTTIM − SOURCE = 2 V 1.0% 1.5% IRST FLTTIM discharge current, timer reset mode FLTTIM − SOURCE = 2 V, SENSE = V −54 −50 −41 3.75 4.00 4.25 Fault reset threshold to SOURCE V 0.5 1 µA mA Logic Outputs (FLT, PG) PARAMETER TEST CONDITIONS MIN TYP MAX IOHFLT IOHPG FLT high-level output leakage current UV = −48 V, FLT – SOURCE = 80 V −10 10 PG high-level output leakage current UV = −45 V, PG – SOURCE = 80 V −10 10 RDS(on) FLT ON resistance SENSE−SOURCE = 80 mV, FLTTIM−SOURCE = 5 V, I(FLT) = 1 mA 50 80 RDS(on) PG ON resistance UV = −48 V, IO(PG) = 1 mA 50 80 UNIT µA A Ω Supply Selector MIN TYP MAX VTHA VTHB Threshold voltage, −VINA falling PARAMETER −VINB = −48 V, −VINA falling TEST CONDITIONS −48.45 −48.40 −48.35 Threshold voltage, −VINB falling −VINA = −48 V, −VINB falling −48.45 −48.40 −48.35 ISINK GATA sink current −VINA = 0 V, −VINB = −48 V, GATA = −41 V 30 80 ISOURCE GATA source current −VINA = −48 V, −VINB = −0 V, GATA = −41 V ISINK GATB sink current −VINA = −48 V, −VINB = −0 V, GATB = −41 V ISOURCE GATB source current −VINA = 0 V, −VINB = −48 V, GATB = −41 V VOLA VOLA GATA low voltage to –VINA −VINA = 0 V, −VINB = −48 V GATA high voltage to –VINA −VINA = −48 V, −VINB = 0 V VOLB GATB low voltage to –VINB −VINA = −48 V, −VINB = 0 V VOLB GATB high voltage to −VINB −VINA = 0 V, −VINB = −48 V † All voltages are with respect to RTN unless otherwise stated. ‡ Currents are positive into and negative out of the specified terminal. 4 www.ti.com −50 30 V mA −20 80 −50 UNIT µA mA −20 µA 0.1 11 14 17 0.1 11 14 17 V SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION FLT 2 O Open-drain, active-low indication that the part is in fault. FLTTIM 5 I/O Connection for user programming of the fault timeout period. GAT 11 O Gate drive for external N-channel FET that ramps load current and disconnects in the event of a fault. GATA 9 O Gate drive for external N-channel FET that selects –VINA. GATB 8 O Gate drive for external N-channel FET that selects –VINB. OV 4 I Over voltage sense input. PG 12 O Open-drain, active-high indication that the power FET is fully enhanced. RAMP 6 I/O Programming input for setting the inrush current slew rate. RTN 1 I Supply return (ground). SENSE 10 I Positive current sense input. SOURCE 7 I/O Negative current sense input. UV 3 I Under voltage sense input. −VINA 14 I Negative supply input A. −VINB 13 I Negative supply input B. PIN DESCRIPTIONS FLT: Open-drain, active-low indication that TPS2350 has shut down due to a faulted load. This happens if the load current stays limited by the linear current amplifier for more than the fault time (time to charge the FLTTIM capacitor). FLT is cleared when both supplies drop below the UV-comparator threshold or one supply exceeds the OV-comparator threshold. The FLT output is pulled to the lower of –VINA and –VINB. The FLT output is able to sink 10 mA when in fault, withstand 80 V without leakage when not faulted, and withstand transients as high as 100 V when limited by a series resistor of at least 10 kΩ. FLTTIM: Connection for user programming of the fault timeout period. An external capacitor connected from FLTTIM to SOURCE establishes the timeout period to declare a fault condition. This timeout protects against indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary current spikes or surges. TPS2350 define a fault condition as voltage at the SENSE pin at or greater than the 42-mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by charging the external capacitor to the 4-V fault threshold, then subsequently discharging it at approximately 1% the charge rate to establish the duty cycle for retrying the load. Whenever the fault latch is set (timer expired), GAT and FLT are pulled low. GAT: Gate drive for an external N-channel protection power MOSFET. When either input supply is above the UV threshold and both are below the OV threshold, gate drive is enabled and the device begins charging the external capacitor connected to RAMP. RAMP develops the reference voltage at the non-inverting input of the internal LCA. The inverting input is connected to the current sense node, SENSE. The LCA acts to slew the pass FET gate to force the SENSE voltage to track the reference. The reference is internally clamped to 42 mV, so the maximum current that can be sourced to the load is determined by the sense resistor value as IMAX ≤ 42 mV/RSENSE. Once the load voltage has ramped up to the input dc potential and current demand drops off, the LCA drives GAT 14 V above SOURCE to fully enhance the pass FET, completing the low-impedance supply return path for the load. GATA: Gate drive for an external N-channel power MOSFET to select −VINA. When –VINA is more negative than –VINB, GATA is pulled 14 V above –VINA, turning on the –VINA power FET. When –VINB is more negative than –VINA, GATA is pulled down to –VINB, turning off the –VINA power FET. www.ti.com 5 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 PIN DESCRIPTIONS (cont.) GATB: Gate drive for an external N-channel power MOSFET to select −VINB. When –VINB is more negative than –VINA, GATB is pulled 14 V above –VINB, turning on the –VINB power FET. When –VINA is more negative than –VINB, GATB is pulled down to –VINA, turning off the –VINB power FET. PG: Open-drain, active-high indication that load current is below the commanded current and the power FET is fully enhanced. When commanded load current is more than the actual load current, the linear current amplifier (LCA) will raise the power MOSFET gate voltage to fully enhance the power MOSFET. At this time, the PG output will go high. This output can be used to enable a down-stream dc-to-dc converter. The PG output is pulled to the lower of –VINA and –VINB. The PG output is able to sink 10 mA when in fault, withstand 80 V without leakage when power is not good, and withstand transients as high as 100 V when limited by a series resistor of at least 10 kΩ. OV: Over voltage comparator input. This input is typically connected to a voltage divider between RTN and SOURCE to sense the magnitude of the more negative input supply. If OV is less than 1.4 V above SOURCE, UV is more than 1.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event of a fault, pulling OV high or UV low will reset the fault latch and allow restarting. OV can also be used as an active-low logic enable input. The over-voltage comparator hysteresis is programmed by the equivalent resistance seen looking into the divider at the OV input. RAMP: Programming input for setting inrush current and current slew rate. An external capacitor connected between RAMP and SOURCE establishes turn-on current slew rate. During turn-on, TPS2350 charges this capacitor to establish the reference input to the LCA at 1% of the voltage from RAMP to SOURCE. The closed-loop control of the LCA and the pass FET maintains the current-sense voltage from SENSE to SOURCE at the reference potential, so the load current slew rate is directly set by the voltage ramp rate at the RAMP pin. When fully charged, RAMP can exceed SOURCE by 6 V, but the reference is internally clamped to 42 mV, limiting load current to 42 mV/RSENSE. When the output is disabled via OV, UV, or due to a load fault, the RAMP capacitor is discharged and held low to initialize for the next turn on. RTN: Positive supply input. For negative voltage systems, this pin connects directly to the return node of the input power bus. SENSE: Current sense input. An external low-value resistor connected between SENSE and SOURCE is used to monitor current magnitude. There are two internal device thresholds associated with the voltage at the SENSE pin. During ramp-up of the load capacitance or during other periods of excessive demand, the linear current amp (LCA) will regulate this voltage to 42 mV. Whenever the LCA is in current regulation mode, the capacitor at FLTTIM is charging and the timer is running. If the LCA is saturated, GAT is pulled 14 V above SOURCE. At this time, a fast fault such as a short circuit can cause the SENSE voltage to rapidly exceed 120 mV (the overload threshold). In this case, the GAT pin is pulled low rapidly, bypassing the fault timer. SOURCE: Connection to the sources of the input supply negative rail selector FETs and the negative terminal of the current sense resistor. The supply select comparator will turn on the appropriate power FET to connect SOURCE to the more negative of –VINA and –VINB. UV: Under voltage comparator input. This input is typically connected to a voltage divider between RTN and SOURCE to sense the magnitude of the more negative input supply. If UV is more than 1.4 V above SOURCE, OV is less than 1.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event of a fault, pulling UV low or OV high will reset the fault latch and allow restarting. UV can also be used as an active high logic enable input. The under-voltage comparator hysteresis is programmed by the equivalent resistance seen looking into the divider at the UV input. −VINA: Negative supply input A. This pin connects directly to the first input supply negative rail. −VINB: Negative supply input B. This pin connects directly to the second input supply negative rail. 6 www.ti.com SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS SUPPLY SELECTOR THRESHOLD VOLTAGE vs AMBIENT TEMPERATURE, −VINA FALLING SUPPLY SELECTOR THRESHOLD VOLTAGE vs AMBIENT TEMPERATURE, −VINB FALLING −0.350 −0.350 V(RTN) = 0 V Relative to −VINA VTHB − Threshold Voltage − V VTHA − Threshold Voltage − V V(RTN) = 0 V Relative to −VINB V(−VINB) = −48 V −0.375 V(−VINB) = −20 V −0.400 V(−VINB) = −80 V −0.425 −0.450 −40 −15 10 35 60 85 −0.375 V(−VINA) = −48 V V(−VINA) = −20 V −0.400 V(−VINA) = −80 V −0.425 −0.450 −40 TA − Ambient Temperature − °C −15 35 60 85 TA − Ambient Temperature − °C Figure 1 Figure 2 GATA HIGH-LEVEL OUTPUT VOLTAGE vs AMBIENT TEMPERATURE GATB HIGH-LEVEL OUTPUT VOLTAGE vs AMBIENT TEMPERATURE 16 16 V(−VINA) = −20 V V(−VINA) = −48 V 12 VOHB − Output Voltage − V VOHA − Output Voltage − V 10 8 V(−VINA) = −12 V 4 12 8 V(−VINB) = −12 V 4 V(RTN) = V(−VINB) = 0 V Relative to −VINA 0 −40 −15 10 35 60 TA − Ambient Temperature − °C V(−VINB) = −48 V V(−VINB) = −20 V V(RTN) = V(−VINA) = 0 V Relative to −VINB 85 Figure. 3 0 −40 −15 10 35 60 TA − Ambient Temperature − °C 85 Figure 4 www.ti.com 7 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS GATx SINK CURRENT vs AMBIENT TEMPERATURE SUPPLY CURRENT vs AMBIENT TEMPERATURE 100 1500 60 1200 GATA Output V(RTN) = V(−VINA) = 0 V V(−VINB) = −48 V VOUT(GATA) = −41 V GATB Output V(RTN) = V(−VINB) = 0 V V(−VINA) = −48 V VOUT(GATB) = −41 V 40 V(−VINA) = −80 V ICC − Supply Current − µA ISINK − Sink Current − mA 80 900 600 V(−VINA) = −48 V V(−VINA) = −20 V 20 0 −40 V(RTN) = V(−VINB) = 0 V V(−VINA) = −12 V 300 −15 10 35 60 0 −40 85 TA − Ambient Temperature − °C −15 10 35 60 85 TA − Ambient Temperature − °C Figure 5 Figure 6 UNDERVOLTAGE PULL-UP CURRENT vs AMBIENT TEMPERATURE VOLTAGE COMPARATOR THRESHOLDS vs AMBIENT TEMPERATURE 1.42 −9.0 V(RTN) = V(−VINB) = 0 V Relative to −VINA V(RTN) = V(−VINB) = 0 V −48 V ≤ V(−VINA) ≤ −20 V VIN(UV) −VIN(SOURCE) =2.5V IHYS_UV − Source Current − µA VTH − Threshold Voltage − V −9.4 1.41 OV Comparator V(−VINA) = −80 V 1.40 UV Comparator −48 V ≤ V(−VINA) ≤ −20 V 1.39 −9.8 −10.2 −−10.6 1.38 −40 −15 10 35 60 85 −11.0 −40 TA − Ambient Temperature − °C 10 35 60 TA − Ambient Temperature − °C Figure 8 Figure 7 8 −15 www.ti.com 85 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS RAMP OUTPUT CURRENT vs AMBIENT TEMPERATURE, REDUCED RATE MODE GAT HIGH-LEVEL OUTPUT VOLTAGE vs AMBIENT TEMPERATURE −460 V(RTN) = V(−VINB) = 0 V VOUT(RAMP) −VIN(SOURCE) =0.25V V(−VINA) = −48 V 12 ISRC1 − RAMP Output Current − nA VOH − Output Voltage − V 16 V(−VINA) = −20 V 8 V(−VINA) = −12 V 4 V(RTN) = V(−VINB) = 0 V VIN(SENSE) −VIN(SOURCE) = 0 V IOUT(GAT) = −10 µA 0 −40 −15 10 35 60 −480 −500 V(−VINA) = −12 V −520 −540 V(−VINA) = −48 V V(−VINA) = −36 V −560 −580 −40 85 −15 Figure 9 35 60 85 Figure 10 TIMER CHARGING CURRENT vs AMBIENT TEMPERATURE RAMP OUTPUT CURRENT vs AMBIENT TEMPERATURE, NORMAL RATE MODE −8.5 −46 Average for VOUT(RAMP) −VIN(SOURCE) = 1 V, 3 V V(RTN) = V(−VINB) = 0 V −80 V ≤ V(−VINA) ≤ −12 V −9.1 ICHG − Charging Current − µA ISRC2 − RAMP Output Current − µA 10 TA − Ambient Temperature − °C TA − Ambient Temperature − °C −9.7 −10.3 V(RTN) = V(−VINB) = 0 V VOUT(FLTTIM) − VIN(SOURCE) = 2 V −80 V ≤ V(−VINA) ≤ −20 V −48 −52 −54 −10.9 −11.5 −40 −15 10 35 60 85 TA − Ambient Temperature − °C 0 −40 −15 10 35 60 85 TA − Ambient Temperature − °C Figure 11 Figure 12 www.ti.com 9 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS TIMER DISCHARGE CURRENT vs AMBIENT TEMPERATURE FAULT LATCH THRESHOLD VOLTAGE vs AMBIENT TEMPERATURE 0.50 V(RTN) = V(−VINB) = 0 V V(−VINA) = −48 V Relative to SOURCE VFLT − Fault Latch Threshold − V IDSG − Discharge Current − µA 0.45 4.25 V(RTN) = V(−VINB) = 0 V −80 V ≤ V(−VINA) ≤ −20 V VOUT(FLTTIM) −VIN(SOURCE) =2V 0.40 0.35 0.30 0.25 0.20 −40 −15 10 35 60 85 4.15 4.05 3.95 3.85 3.75 −40 TA − Ambient Temperature − °C 10 35 60 TA − Ambient Temperature − °C Figure 14 Figure 13 10 −15 www.ti.com 85 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 FUNCTIONAL BLOCK DIAGRAM RTN 1 UV Input UV Comparator + 3 1.4 V Input OV Comparator OV Disable 4 1.4 V + 2 FLT Fault Latch 120 mV 4 µs Filter + Fault Timer Retry Timer S Q R Q Overload Comparator FLTTIM 5 SENSE 10 + Linear Current Amp 99R RAMP 11 GAT 6 Disable Power Good Detection 42 mV R 12 PG + 7 SOURCE Supply Select Comparator + 9 GATA 400 mV Hysteresis 14 13 −VINA −VINB www.ti.com 8 GATB 11 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION SUPPLY SECTION The supply selection comparator selects between –VINA and –VINB based on which supply has a larger magnitude. To prevent chattering between two nearly identical supplies, the supply selection comparator has 400 mV of hysteresis. This prevents supply noise or ripple from tripping the comparator and should be adequate for most systems. Hysteresis is set to 400 mV to give the highest noise margin without allowing conduction in the body diodes of the supply selection FETs. For systems with many cards, high current cards, or long cables between the power and the load, the voltage loss in the cable can be significant. If the supplies are close to the same magnitude, then the voltage loss in the cable could cause enough drop to exceed the supply selection comparator hysteresis. In this case, the supply selection comparator hysteresis must be increased. TPS2350 allows you to increase the hysteresis of the supply selection comparator with external resistors, limited to the threshold of the external FETs. Figure 15 shows shows a system with higher hysteresis, set by R4, R5, R6 and R7. The resistors act as a simple multiplier to increase the voltage differential required to switch the comparator. For example, for R4 = R5 = 40 kΩ, and R6 = R7 = 20 kΩ, the hysteresis is approximately 1.2 V. Because of the large hysteresis, the supply selection power FETs are replaced with dual power FETs, configured so that the body diodes can never conduct. The GATA and GATB outputs are able to switch dual FETs, so no additional drive or logic circuits are required. RTN CLOAD R1 RLOAD 1 RTN 12 PG POWER GOOD 2 FAULT 3 Q1 GAT 11 SENSE 10 FLT TPS2350 UV RSENSE SOURCE 7 R2 4 Q2 GATA 9 OV Q3 GATB 8 FLTTIM RAMP R3 5 6 CFLT −VINA −VINB 14 13 CRAMP Q4 Q5 R6 R4 R7 R5 −VINB −VINA Figure 15. Typical Application to Develop Higher Supply Comparator Hysteresis 12 www.ti.com UDG−03121 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION Setting the Sense Resistor Value Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage VSENSE to its internal reference. Once the voltage at the RAMP pin exceeds approximately 4 V, this limit is the clamp voltage, VREF_K. Therefore, a maximum sense resistor value can be determined from equation (1). R SENSE v 34 mV I IMAX (1) where D RSENSE is the resistor value D IIMAX is the desired current limit When setting the sense resistor value, it is important to consider two factors, the minimum current that may be imposed by the TPS2350, and the maximum load under normal operation of the module. For the first factor, the specification minimum clamp value is used, as seen in equation (1). This method accounts for the tolerance in the sourced current limit below the typical level expected (42 mV/RSENSE). (The clamp measurement includes LCA input offset voltage; therefore, this offset does not have to be factored into the current limit again.) Second, if the load current varies over a range of values under normal operating conditions, then the maximum load level must be allowed for by the value of RSENSE. One example of this is when the load is a switching converter, or brick, which draws higher input current, for a given power output, when the distribution bus is at the low end of its voltage range, with decreasing draw at higher supply voltages. To avoid current limit operation under normal loading, some margin should be designed in between this maximum anticipated load and the minimum current limit level, or IIMAX > ILOAD(max), for equation (1). For example, using a 10-mΩ sense resistor for a nominal 2-A load application provides a minimum of 1.4 A of overhead for load variance/margin. Typical bulk capacitor charging current during turn-on is 4.2 A (42 mV/10 mΩ). Setting the Inrush Slew Rate The TPS2350 device enables user-programming of the maximum current slew rate during load start-up events. A capacitor tied to the RAMP pin (CRAMP in the typical application diagram) controls the di/dt rate. Once the sense resistor value has been established, a value for CRAMP, in microfarads, can be determined from equation (2). C RAMP + 11.3 100 R SENSE ǒdtdiǓ (2) (max) where D RSENSE is the sense resistor value in Ω D (di/dt)(max) is the desired maximum slew rate in A/s For example, if the desired slew rate for the typical application shown is 1500 mA/ms, the calculated value for CRAMP is about 7500 pF. Selecting the next larger standard value of 8200 pF provides some margin for capacitor and sense resistor tolerances. The TPS2350 initiates ramp capacitor charging, and consequently load current slewing, at a reduced rate. This reduced rate applies until the voltage on the RAMP pin is about 0.5 V. The maximum di/dt rate, as set by equation (2), is effective once the device switches to a 10-µA charging source. www.ti.com 13 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION Setting the Fault Timing Capacitor The fault timeout period is established by the value of the capacitor connected to the FLTTIM pin, CFLT. The timeout period permits riding out spurious current glitches and surges that may occur during operation of the system, and prevents indefinite sourcing into faulted loads. However, to ensure smooth voltage ramping under all conditions of load capacitance and input supply potential, the minimum timeout should be set to accommodate these system variables. To do this, a rough estimate of the maximum voltage ramp time for a completely discharged plug-in card provides a good basis for setting the minimum timer delay. This section presents a quick procedure for calculating the timing capacitance requirement. However, for proper operation of the TPS2350, there is an absolute minimum value of 0.01-µF for CFLT. This minimum requirement overrides any smaller results of equations (7) and (8) below. Due to the three-phase nature of the load current at turn-on, the load voltage ramp has potentially three distinct phases. This profile depends on the relative values of load capacitance, input DC potential, maximum current limit and other factors. The first two phases are characterized by the two different slopes of the current ramp; the third phase, if required to complete load charging, is the constant-current charging at IMAX. Considering the two current ramp phases to be one period at an average di/dt simplifies calculation of the required timing capacitor. For the TPS2350, the typical duration of the soft-start period, tSS, is given by equation (3) t SS + 1260 C RAMP (3) where D tSS is the soft-start period in ms D CRAMP is given in µF During this current ramp period, the load voltage magnitude which is attained is estimated by equation (4). V LSS + i AVG 2 C LOAD C RAMP 100 R SENSE ǒtSSǓ 2 (4) where D D D D VLSS is the load voltage reached during soft-start i AVG is 3.18 µA for the TPS2350 CLOAD is the load capacitance in Farads tSS is the soft-start period in s The quantity iAVG in equation (4) is a weighted average of the two charge currents applied to CRAMP during turn-on, considering the typical output values. 14 www.ti.com SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION If the result of equation (4) is larger than the maximum input supply value, then the load can be expected to charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than the maximum supply input, VIN(MAX), the HSPM transitions to the constant-current charging of the load. The remaining amount of time required at IMAX is determined from equation (5). t CC + ǒVIN(MAX) * VLSSǓ C LOAD V REF_K(MIN) R SENSE (5) where D tCC is the constant-current voltage ramp time, in seconds D VREF_K(MIN) is the minimum clamp voltage, 34 mV With this information, the minimum recommended value timing capacitor CFLT can be determined. The delay time needed will be either a time tSS2 or the sum of tSS2 and tCC, according to the estimated time to charge the load. The quantity tSS2 is the duration of the normal rate current ramp period, and is given by equation (6). t SS2 + 0.35 C RAMP (6) where D CRAMP is given in µF Since fault timing is generated by the constant-current charging of CFLT, the capacitor value is determined from either equation (7) or (8), as appropriate. C FLT(MIN) + C FLT(MIN) + 54 54 t SS2 3.75 (7) ǒt SS2 ) t CCǓ 3.75 (8) where D CFLT(MIN) is the recommended capacitor value, in µ-Farads D tSS2 is the result of equation (6), in seconds D tCC is the result of equation (5), in seconds Continuing this calculation example, using a 220-µF input capacitor (CLOAD), equations (3) and (4) estimate the load voltage ramping to approximately −45 V during the soft-start period. If the module should operate down to −72-V input supply, approximately another 1.4 ms of constant-current charging may be required. Therefore, equations (6) and (8) are used to determine CFLT(MIN), and the result is approximately 0.039-µF. www.ti.com 15 SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION Setting the Undervoltage and Overvoltage Thresholds The UV and OV pins can be used to set the undervoltage (VUV) and overvoltage (VOV) thresholds of the hot swap circuit. When the input supply is below VUV or above VOV, the GAT pin is held low, disconnecting power from the load, and the PG output is deasserted. When input voltage is within the UV/OV window, the GAT pin drive is enabled, assuming all other input conditions are valid for turn-on. Threshold hysteresis is provided via two internal sources which are switched to either pin whenever the corresponding input level exceeds the internal 1.4-V reference. The additional bias shifts the pin voltage in proportion to the external resistance connected to it. This small voltage shift at the device pin is gained up by the external divider to input supply levels. (a) (b) GND GND R1 200 kΩ 1% 1 R1 1 R8 RTN RTN 3 UV R2 4.99 kΩ 1% 3 UV TPS2350* TPS2350* 4 OV R3 3.92 kΩ 1% 4 OV R2 SOURCE SOURCE R9 7 −48V 7 −48V V UV_L + R1 ) R2 ) R3 R2 ) R3 V THUV V OV_L + R1 ) R2 ) R3 R3 V THOV * I HYSUV R1 V UV_L + R1 ) R2 R2 V THUV V OV_L + R8 ) R9 R9 V THOV UDG−03121 *Additional details omitted for clarity Figure 16. Programming the Undervoltage and Overvoltage Thresholds The UV and OV thresholds can be individually programmed with a three-resistor divider connected to the TPS2350 as shown in the typical application diagram, and again in Figure 16a. When the desired trip voltages and undervoltage hysteresis have been established for the protected board, the resistor values needed can be determined from the following equations. Generally, the process is simplest by first selecting the top leg of the divider (R1 in the diagram) needed to obtain the threshold hysteresis. This value is calculated from equation (9). R1 + V HYS_UV 10 mA (9) where D VHYS_UV is the undervoltage hysteresis value 16 www.ti.com SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION For example, assume the typical application design targets have been set to undervoltage turn-on at 33 V (input supply rising), turn-off at 31 V (input voltage falling), and overvoltage shutdown at 72 V. Then equation (9) yields R1 = 200 kΩ for the 2-V hysteresis. Once the value of R1 is selected, it is used to calculate resistors R2 and R3. R2 + R3 + ȱ V UV_L 1* ȧ ǒVUV_L * 1.4Ǔ Ȳ ǒVOV_L ) 10*5 1.4 ȳ ȧ R1Ǔȴ R1 1.4 R1 V UV_L ǒVUV_L * 1.4Ǔ ǒVOV_L ) 10*5 Ǔ R1 (10) (11) where D VUV_L is the UVLO threshold when the input supply is low; i.e., less than VUV, and D VOV_L is the OVLO threshold when the input supply is low; i.e., less than VOV Again referring to the Figure 17a schematic, equations (10) and (11) produce R2 = 4.909 kΩ (4.99 kΩ selected) and R3 = 3.951 kΩ (3.92 kΩ selected), as shown. For the selected values, the expected nominal supply thresholds are VUV_L = 32.8 V, VUV_H = 30.8 V, and VOV_L = 72.6 V. The hysteresis of the overvoltage threshold, as seen at the supply inputs, is given by the quantity (10 µA) × (R1 + R2). For the majority of applications, this value is very nearly the same as the UV hysteresis, since typically R1 >> R2. If more independent control is needed for the OVLO hysteresis, there are several options. One option is to use separate dividers for both the UV and OV pins, as shown in Figure 16b. In this case, once R1 and R8 have been selected for the required hysteresis per equation (9), and values for the bottom resistors in the divider (R2 and R9 in Figure 16b) can be calculated using equation (12). R XVLO + V REF ǒVXV_L * VREFǓ R (TOP) (12) where D D D D RXVLO is R2 or R9 R(TOP) is R1 or R8 as appropriate for the threshold being set VXV_L is the under (VUV_L) or overvoltage (VOV_L) threshold at the supply input, and VREF is either VTHUV or VTHOV from the specification table, as required for the resistor being calculated. www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2350D ACTIVE SOIC D 14 TPS2350DR ACTIVE SOIC D 14 TPS2350PW ACTIVE TSSOP PW 14 TPS2350PWR ACTIVE TSSOP PW 14 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 90 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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