SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 FEATURES D BiCMOS Version of UC3846 Family D 1.4-mA Maximum Operating Current D 100-µA Maximum Startup Current D ±0.5-A Peak Output Current D 125-ns Circuit Delay D Easier Parallelability D Improved Benefits of Current Mode Control for applications ranging from off-line power supplies to battery operated portable equipment. Dual high-current, MOSFET driving outputs and a fast current sense loop further enhance device versatility. DESCRIPTION These devices are available in multiple package options for both through-hole and surface mount applications; and in commercial, industrial, and military temperature ranges. The UCC3806 family of BiCMOS PWM controllers offers exceptionally improved performance with a familiar architecture. With the same block diagram and pinout of the popular UC3846 series, the UCC3806 line features increased switching frequency capability while greatly reducing the bias current used within the device. With a typical startup current of 50 µA and a well defined voltage threshold for turn-on, these devices are favored All the benefits of current mode control including simpler loop closing, voltage feed-forward, parallelability with current sharing, pulse-by-pulse current limiting, and push/pull symmetry correction are readily achievable with the UCC3806 series. The UCC3806 is specified for operation from −55°C to 125°C, the UCC2806 is specified for operation from −40°C to 85°C, and the UCC3806 is specified for operation from 0°C to 70°C. SIMPLIFIED APPLICATION DIAGRAM +VOUT +VIN 15 UC39431 13 VIN VC UCC3612 UCC3806 2 VREF INV 6 COMP 7 8 CT 5 NI AOUT 11 1 CURLIM BOUT 14 10 SYNC SHUT 15 DOWN 9 RT CS+ 4 CS− GND 3 12 ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) Copyright 1999 − 2003, Texas Instruments Incorporated www.ti.com 1 SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UCx806 UNIT Supply voltage, VIN VIN, low impedance 15 V Supply current, IIN VIN, high impedance 25 mA Output supply voltage VC 18 V Output current Analog input voltage range Continuous source or sink ± 200 Gate drive ± 500 SYNC ± 30 COMP ± 10 to −(self-limiting) CS−, CS+, NI, INV, SHUTDOWN mA −0.3 to (VIN + 0.3) V Storage temperature, Tstg −65 to 150 °C Operating temperature, TJ −55 to 150 °C Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds 300 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of, the specified terminal. RECOMMENDED OPERATING CONDITIONS MIN Input voltage, VIN Operating junction temperature, TJ NOM 14.5 125 UCC2806 −40 85 UCC3806 0 70 Q OR L PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 9 SHUTDOWN VIN BOUT VC GND AOUT SYNC RT VREF CURLIM NC SHUTDOWN VIN 1 2 3 4 5 6 7 8 CS− CS+ N/C NI INV 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 N/C − No connection 2 www.ti.com V 8.0 −55 COMP CT N/C RT SYNC CURLIM VREF CS− CS+ NI INV COMP CT UNIT UCC1806 PACKAGE DESCRIPTION D, DW, J, M, N OR PW PACKAGE (TOP VIEW) MAX BOUT VC N/C GND AOUT °C C SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 ORDERING INFORMATION PACKAGED DEVICES DESIGNATOR TYPE D SOIC−16 DW SOICW−16 OPTION QUANTITY − 55°C to 125°C TA = TJ − 40°C to 85°C Tube 40 – UCC2806D – Reeled 2,500 – UCC2806DTR – 0°C to 70°C Tube 40 – UCC2806DW UCC3806DW Reeled 2,000 – UCC2806DWTR UCC3806DWTR J CDIP−16 Tube 25 UCC1806J UCC2806J UCC3806J L CLCC−20 Tube 55 UCC1806L – – M SSOP−16 Reeled 2,500 – UCC2806MTR – N PDIP−16 Tube 25 – UCC2806N UCC3806N Tube 90 – UCC2806PW UCC3806PW Reeled 2,000 – UCC2806PWTR UCC3806PWTR Tube 46 – UCC2806Q UCC3806Q Reeled 1,000 – UCC2806QTR UCC3806QTR PW TSSOP−16 Q PLCC−20 ELECTRICAL CHARACTERISTICS VIN = 12 V, RT = 33 kΩ, CT = 330 pF, CBYPASS on VREF = 0.01 µF, −55°C < TA < 125°C for the UCC1806, −40°C < TA < 85°C for the UCC2806, 0°C < TA < 70°C for the UCC3806, and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UCC1806 UCC2806 5.02 5.10 5.17 UCC3806 5.00 5.10 5.20 UNIT REFERENCE VREF Supply, UVLO, turn-on Load regulation 0.2 mA ≤ IOUT ≤ 5 mA Total output variation (1)(2) Output noise voltage (2) Line, load, temperature Long term stability (2) TA = 125°C, 3 −150 10 Hz ≤ fOSC ≤ 10 kHz, TJ = 25°C 1000 hours Output short circuit 25 150 5 mV µV 70 −10 V 25 mV −30 mA 52 kHz OSCILLATOR Initial accuracy TJ = 25°C T(min) ≤ TA ≤ T(max) Temperature stability (2) Amplitude tDELAY 42 47 2% 2.35 V UCC1806 UCC2806 VCT = 0 V, VRT = VREF 0.8 V ≤ VSYNC ≤ 2.0 V 50 125 UCC3806 VCT = 0 V, VRT = VREF 0.8 V ≤ VSYNC ≤ 2.0 V 50 100 Delay-to-output time, SYNC www.ti.com ns 3 SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 ELECTRICAL CHARACTERISTICS VIN = 12 V, RT = 33 kΩ, CT = 330 pF, CBYPASS on VREF = 0.01 µF, −55°C < TA < 125°C for the UCC1806, −40°C < TA < 85°C for the UCC2806, 0°C < TA < 70°C for the UCC3806, and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCILLATOR (continued) IDCHG VOL Discharge current VOH VIL High-level output voltage, SYNC Low-level input voltage, SYNC IOUT = −4 mA VCT = 0 V, VIH ISYNC High-level input voltage, SYNC VCT = 0 V, Low-level output voltage, SYNC TJ = 25°C, IOUT = 1 mA VCT = 2.0 V 2 mA 0.4 2.4 VRT = VREF VRT = VREF Input current, SYNC 0.8 V 2.0 −1 1 µA ERROR AMPLIFIER Input offset voltage IBIAS IOFSET Input bias current CMR Common mode range(1) AVOL GBW Open loop gain ICOMP_SINK ICOMP_SRC Output sink current VCOMP_L VCOMP_H Low-level output voltage UCC1806 UCC2806 5 UCC3806 10 Input offset current 0 1 V ≤ VOUT ≤ 4 V bandwidth VID < −20 mV, VID < 20 mV, Output source current High-level output voltage Maximum differential input signal (VCS+ − VCS−) Input offset voltage UCC1806 UCC2806 UCC3806 CMRR Common mode rejection ratio PSRR Power supply rejection ratio Input bias current (3) Input offset current (3) Delay-to-output time (5) VCOMP = 1 V VCOMP = 3 V VID = −50 mV VID = −50 mV CURRENT SENSE AMPLIFIER A Amplifier gain(3)(4) IBIAS 80 VCS− = 0 V, VCURLIM = VREF VCURLIM = VNI = VREF, VINV = 0V mV −1 µA 500 nA VIN−2 100 V dB 1 MHz 1 mA −80 µA −120 0.5 V 4.5 2.75 3.00 3.35 1.1 V/V V VCURLIM = 0.5 V, VCOMP = OPEN 10 30 µA VCURLIM = 0.5 V, VCOMP = OPEN 0 V ≤ VCM ≤ (VIN − 3.5 V) 10 50 mV 60 dB 56 dB −1 µA 1 µA 125 175 ns 0.4 0.5 0.6 V 300 200 VCURLIM = 0.5 V, VCOMP = OPEN VCURLIM = 0.5 V, VCOMP = OPEN VNI = VREF, VINV = 0 V, VCURLIM = 2.75 V, (VCS+ − VCS−) = 0 V to 1.5 V step CURRENT LIMIT ADJUST Current limit offset IBIAS VCS− = VCS+ = 0 V,VCOMP = OPEN Input bias current 1 Minimum latching current Maximum non-latching current (1) (2) 4 200 Line range = 10 V to 15 V, load range = 0.2 mA to 5 mA Ensured by design. Not production tested. www.ti.com µA 80 SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 ELECTRICAL CHARACTERISTICS VIN = 12 V, RT = 33 kΩ, CT = 330 pF, CBYPASS on VREF = 0.01 µF, −55°C to 125°C for the UCC1806, −40°C < TA < 85°C for the UCC2806, 0°C < TA < 70°C for the UCC3806, and TA = TJ (unless otherwise noted) SHUTDOWN TERMINAL Threshold voltage UCC1806 UCC2806 0.94 1.00 1.06 UCC3806 0.9 1.0 1.1 75 VIN 150 Input voltage range 0 0 V ≤ VSHUTDOWN ≤ 1.3 V tDLY Delay-to-output time OUTPUT Output supply voltage 2.5 ISINK = 20 mA ISINK = 100 mA 100 0.4 1.1 100 200 UCC3806 ISINK = 20 mA ISINK = 100 mA 0.4 1.1 tRISE tFALL 11.6 11.9 11.0 11.6 300 Rise time ISRC = −20 mA ISRC = −100 mA TJ = 25°C, CLOAD = 1000 pF 35 65 Fall time TJ = 25°C, CLOAD = 1000 pF 35 65 7.5 8.0 High-level output voltage ns 15.0 UCC1806 UCC2806 Low-level output voltage V V ns UNDERVOLTAGE LOCKOUT (UVLO) VSTART Startup threshold voltage Threshold hysteresis ISTART I (1) (2) (3) (4) (5) 6.5 0.75 Startup current VIN < VSTART Operating supply current VIN shunt voltage IVIN = 10 mA 15.0 Line range = 10 V to 15 V, load range = 0.2 mA to 5 mA Ensured by design. Not production tested. Parameters measured at trip point of latch with VNI = VREF , VINV = 0V. Amplifier gain defined as: G = delta change at COMP /delta change forced at CS+ delta voltage at CS+ = 0 to 1V Current-sense amplifier output is slew rate limited to provide noise immunity. V V 50 100 µA 1.0 1.4 mA 17.5 THERMAL RESISTANCE TABLE PACKAGE DESIGNATOR PACKAGE TYPE D DW θJC θJA (°C/W) (°C/W) SOIC−16 35 SOICW−16 27 50 to 120(1) 50 to 100(1) 80 to 120 J CDIP−16 28 L CLCC−20 20 70 to 80 M SSOP−16 38 N PDIP−16 45 144 to 172(2) 90(1) PW TSSOP−16 15 123 to 147(2) 43 to 75(1) Q PLCC−20 34 (1) Specified θ JA (junction to ambient) is for devices mounted to 5 in2 FR4 PC board with one ounce copper where noted. When resistance range is given, lower values are for 5 in2 aluminum PC board. Test PWB was 0.062 in thick and typically used 0.635 mm trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100x100 mil probe land area at the end of each trace. (2) Modeled data. If value range given for θ JA, the lower value is for 3x3 inch1 oz internal copper ground plane, and the higher value is for 1x1 inch ground plane. All model data assumes only one trace for each non-fused lead. www.ti.com 5 SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 TERMINAL FUNCTIONS TERMINAL PACKAGES NAME D/DW/J/M /N/PW L,Q AOUT 11 14 BOUT 14 18 COMP 7 CS− 3 CS+ I/O DESCRIPTION O High-current gate drive for the external MOSFETs 9 O Output of the error amplifier 4 I Inverting input of the 3×, differential current sense amplifier 4 5 I Non-inverting input of the 3×, differential current sense amplifier CT 8 10 I Oscillator timing capacitor connection point CURLIM 1 2 I Programs the primary current limit threshold that determins latching or retry after an overcurrent situation GND 12 15 − Reference ground and power ground for all functions of this device INV 6 8 I Inverting input of the error amplifier. NI 5 7 I Non-nverting input of the error amplifier. RT 9 12 I Connection point for the oscillator timing resistor SHUTDOWN 16 20 I Provided for enhanced protection. When SHUTDOWN is driven above 1 V, AOUT and BOUT are forced low. SYNC 10 13 I/O VC 13 17 I Input supply connection for the FET drive outputs. VIN 15 19 I Input supply connection for this device. VREF 2 3 O Reference output. Allows providing external synchronization with TTL compatible thresholds. DETAILED PIN DESCRIPTIONS AOUT and BOUT: AOUT and BOUT provide alternating high current gate drive for the external MOSFETs. Duty cycle can be varied from 0% to 50% where minimum dead time is a function of CT. Both outputs use MOS transistor switches with inherent anti-parallel body diodes to clamp voltage swings to the supply rails, allowing operation without the use of clamp diodes. COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier is a low output impedance, 2-MHz operational amplifier which allows sinking or sourcing of current at the COMP pin. The error amplifier is internally current limited, so that zero duty cycle can be commanded by externally forcing COMP to GND. CS−: CS− is the inverting input of the 3× differential current sense amplifier. CS+: CS+ is the non-inverting input of the 3× differential current sense amplifier. CT: CT is the oscillator timing capacitor connection point, which is charged by the current set by RT. CT is discharged to GND through a 2.6-mA current sink. This causes a linear discharge of CT to 0 V which then initiates the next switching cycle. Dead time occurs during the discharge of CT, forcing AOUT and BOUT low. Switching frequency (fS) and dead time (tD) are approximated by: fS + 6 1 2 RT CT ) tD and t D + 961 CT www.ti.com (1) SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 DETAILED PIN DESCRIPTIONS (continued) CURLIM: CURLIM programs the primary current limit threshold and determines whether the device latches off or retries after an overcurrent condition. When a shutdown signal is generated, a 200-µA current source to ground pulls down on CURLIM. If the voltage on the pin remains above 350 mV the device remains latched and the power must be cycled to restart. If the voltage on the pin falls below 350 mV, the device attempts a restart. The voltage threshold is typically set by a resistor divider from VREF to ground. To calculate the current limit adjust voltage threshold the following equations can be used. Current limit adjust latching mode voltage is calculated in equation (2) V+ V REF * (R1 300 mA ǒ Ǔ 3) 1 ) R1 R2 u 350 mV (2) Current limit adjust non-latching mode voltage is calculated in equation (3) V+ V REF * (R1 80 mA ǒ Ǔ 1 ) R1 R2 3) t 350 mV (3) where D R1 is the resistance from the VREF to CURLIM D R2 is the resistance from CURLIM to GND GND: GND is the reference ground and power ground for all functions of this part. Bypass and timing capacitors should be connected as close as possible to GND. RT: RT is the connection point for the oscillator timing resistor. It has a low impedance input and is nominally at 1.25 V. The current through RT is mirrored to the timing capacitor pin, CT. This causes a linear charging of CT from 0 V to 2.35 V. Note that the current mirror is limited to a maximum of 100 µA so RT must be greater than 12.5 kΩ. SYNC: SYNC is a bi-directional pin, allowing or providing external synchronization with TTL compatible thresholds. In a typical application RT is connected through a timing resistor to GND which allows the internal oscillator to free run. In this mode SYNC outputs a TTL compatible pulse during the oscillator dead time (when CT is being discharged). If RT is forced above 4.4 V, SYNC acts as an input with TTL compatible thresholds and the internal oscillator is disabled. When SYNC is high, greater than 2 V the outputs are held active low. When SYNC returns low, the outputs may be high until the on−time is terminated by the normal peak current signal, a fault seen at SHUTDOWN or the next high assertion of SYNC. Multiple UCC3806s can be synchronized by a single master UCC3806 or external clock. VC: VC is the input supply connection for the FET drive outputs and has an input range from 2.5 V to 15 V. VC should be capacitively bypassed for proper operation. VIN: VIN is the input supply connection for this device. The UCC1806 has a maximum startup threshold of 8 V and internally limited by means of a 15 V shunt regulator. The shunted supply current must be limited to 2.5 mA. For proper operation, VIN must be bypassed to GND with at least a 0.01-µF ceramic capacitor VREF: VREF is a 5.1 V ±1% trimmed reference output with a 5 mA maximum available current. VREF must be bypassed to GND with at least a 0.1-µF ceramic capacitor for proper operation. www.ti.com 7 SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 FUNCTIONAL BLOCK DIAGRAM SYNC 10 13 VC 4.4V RT 1.5 V − + 9 − + 11 AOUT OSC CT CS− CS+ Q LO 8 3 Comparator − 3X + 4 INV 12 GND S2 Shutdown − Lockout 120 µA 0.5 V + NI QB S1 + − 14 BOUT T R QB 5 6 1 + EA − R S1 COMP 7 Q Q 7.0 V VIN 15 + − S2 R S 7.5 V 15 V 5.1 V Reference Regulator Current Limit Restart R CURLIM 0.35 V S 200 µA Q + − − + + − 1.0 V 16 SHUT DOWN 200kΩ UVLO 4.25 V + − 2 VREF Reference Low UDG−99035 8 www.ti.com SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 TYPICAL APPLICATION DIAGRAM UDG−99036 TYPICAL CHARACTERISTICS Design equations for oscillator are described in the following equations. f OSC + 1 t RAMP ) t FALL t RAMP + 1.92 t FALL + ǒ 2.4 RT (4) CT (5) CT ǒ ǓǓ 0.002 * 1.25 RT (6) t DEAD + t FALL (7) www.ti.com 9 SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003 TYPICAL CHARACTERISTICS 180 135 Phase Gain − dB 58 fOSC − Oscillator Frequency − kHz 60 90 40 20 45 0 Gain OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 60 Phase − ° 80 ERROR AMPLIFIER GAIN AND PHASE vs FREQUENCY 0 56 54 52 50 48 46 44 42 −20 1k 10 k 100 k 1M 40 −55 −45 10 M −25 0 25 50 TJ − Junction Temperature − °C fOSC − Oscillator Frequency − Hz Figure 1. Figure 2. OSCILLATOR FREQUENCY vs TIMING RESISTANCE fOSC − Oscillator Frequency − kHz 1M CT = 220 pF CT = 100 pF 100 k 10 k CT = 47 pF CT = 330 pF CT = 470 pF 0 10 k CT = 1.0 nF CT = 2.2 nF 100 k RT − Timing Resistance − Ω Figure 3. 10 75 www.ti.com 1M 100 125 PACKAGE OPTION ADDENDUM www.ti.com 8-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) 5962-9457501MEA ACTIVE CDIP J 16 1 None 5962-9457501Q2A ACTIVE LCCC FK 20 1 None Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish A42 SNPB MSL Peak Temp (3) Level-NC-NC-NC POST-PLATE Level-NC-NC-NC 5962-9457501V2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-9457501VEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC UCC1806J ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC 1 None A42 SNPB Level-NC-NC-NC None Call TI UCC1806J883B ACTIVE CDIP J 16 UCC1806JQMLV ACTIVE CDIP J 16 UCC1806L ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC 1 None POST-PLATE Level-NC-NC-NC UCC1806L883B ACTIVE LCCC FK 20 UCC1806LQMLV ACTIVE LCCC FK 20 UCC2806D ACTIVE SOIC D 16 UCC2806DTR ACTIVE SOIC D UCC2806DW ACTIVE SOIC DW UCC2806DWTR ACTIVE SOIC Call TI None Call TI 40 None CU NIPDAU Call TI Level-1-220C-UNLIM 16 2500 None CU NIPDAU Level-1-220C-UNLIM 16 40 None CU NIPDAU Level-2-220C-1 YEAR DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UCC2806J ACTIVE CDIP J 16 1 None A42 SNPB UCC2806M ACTIVE SSOP/ QSOP DBQ 16 75 None CU NIPDAU Level-NC-NC-NC Level-2-220C-1 YEAR UCC2806MTR ACTIVE SSOP/ QSOP DBQ 16 2500 None CU NIPDAU Level-2-220C-1 YEAR UCC2806N ACTIVE PDIP N 16 25 None CU SNPB UCC2806PW ACTIVE TSSOP PW 16 90 None CU NIPDAU Level-2-220C-1 YEAR None CU NIPDAU Level-2-220C-1 YEAR CU NIPDAU Level-1-260C-UNLIM UCC2806PWTR ACTIVE TSSOP PW 16 2000 UCC2806PWTRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) Level-NA-NA-NA UCC2806Q ACTIVE PLCC FN 20 46 None CU SNPB Level-2-220C-1 YEAR UCC2806QTR ACTIVE PLCC FN 20 1000 None CU SNPB Level-2-220C-1 YEAR UCC3806DW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UCC3806DWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UCC3806J ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UCC3806N ACTIVE PDIP N 16 25 None CU SNPB Level-NA-NA-NA UCC3806PW ACTIVE TSSOP PW 16 90 None CU NIPDAU Level-2-220C-1 YEAR UCC3806PWTR ACTIVE TSSOP PW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UCC3806Q ACTIVE PLCC FN 20 46 None CU SNPB Level-2-220C-1 YEAR UCC3806QTR ACTIVE PLCC FN 20 1000 None CU SNPB Level-2-220C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Mar-2005 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated