ONSEMI CAT34TS02VP2GT4B

CAT34TS02
Digital Output Temperature Sensor with
On-board SPD EEPROM
FEATURES
DESCRIPTION
 JEDEC JC42.4 Compliant Temperature Sensor
The CAT34TS02 combines a JC42.4 compliant
Temperature Sensor (TS) with 2-Kb of Serial
Presence Detect (SPD) EEPROM.
 Temperature Range: - 40°C to +125°C
 DDR3 DIMM compliant SPD EEPROM
 Supply Range: 3.3 V ± 10%
The TS measures temperature at least 10 times every
second. Temperature readings can be retrieved by the
host via the serial interface, and are compared to
high, low and critical trigger limits stored into internal
registers. Over or under limit conditions can be
¯¯¯¯¯¯ pin.
signaled on the open-drain EVENT
2
 I C / SMBus Interface
 Schmitt Triggers and Noise Suppression Filters
on SCL and SDA Inputs
 Low Power CMOS Technology
 RoHS-compliant 2 x 3 x 0.75 mm TDFN package
The integrated 2-Kb SPD EEPROM is internally
organized as 16 pages of 16 bytes each, for a total of
256 bytes. It features a 16-byte page write buffer and
supports both the Standard (100 kHz) as well as Fast
2
(400 kHz) I C protocol.
For Ordering Information details, see page 21.
Write operations to the lower half memory can be
inhibited via software commands. The CAT34TS02
features Permanent, as well as Reversible Software
Write Protection, as defined for DDR3 DIMMs.
PIN CONFIGURATION
TDFN (VP2)
(2 x 3 x 0.75 mm)
A0 1
8 VCC
A1 2
7 EVENT
A2 3
6 SCL
VSS 4
5 SDA
FUNCTIONAL SYMBOL
VCC
Note: For the location of Pin 1, please consult the corresponding
package drawing.
SCL
PIN FUNCTIONS
Name
A0, A1, A2
SDA
SCL
¯¯¯¯¯¯
EVENT
VCC
VSS
DAP
A2, A1, A0
Description
Device Address Input
CAT34TS02
EVENT
SDA
Serial Data Input/Output
VSS
Serial Clock Input
Open-drain Event Output
Power Supply
Ground
Backside exposed DAP at VSS
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1129 Rev. G
CAT34TS02
Absolute Maximum Ratings
(1)
Parameter
Operating Temperature
Storage Temperature
(2)
Voltage on any pin (except A0) with respect to Ground
Voltage on pin A0 with respect to Ground
Rating
-45 to +130
-65 to +150
-0.5 to +6.5
-0.5 to +10.5
Units
°C
°C
V
V
(3)
RELIABILITY CHARACTERISTICS
Symbol
(4)
NEND
TDR
Parameter
Endurance (EEPROM)
Data Retention (EEPROM)
Min
1,000,000
100
Units
Write Cycles
Years
TEMPERATURE CHARACTERISTICS
VCC = 3.3 V ± 10%, TA = −40°C to +125°C, unless otherwise specified
Parameter
Temperature Reading Error
Class B, JC42.4 compliant
Test Conditions/Comments
Max
Unit
+75°C ≤ TA ≤ +95°C, active range
±1.0
°C
+40°C ≤ TA ≤ +125°C, monitor range
±2.0
°C
-40°C ≤ TA ≤ +125°C, sensing range
±3.0
°C
12
Bits
0.0625
°C
100
ms
92
ºC/W
Max
Unit
TS active, SPD and Bus idle
500
μA
EEPROM Write, TS shut-down
500
μA
ADC Resolution
Temperature Resolution
Conversion Time
Thermal Resistance θJA
(3)
Junction-to-Ambient (Still Air)
D.C. OPERATING CHARACTERISTICS
VCC = 3.3 V ± 10%, TA = −40°C to +125°C, unless otherwise specified
Symbol
ICC
Parameter
Supply Current
Test Conditions/Comments
Min
ISHDN
Standby Current
TS shut-down; SPD and Bus idle
10
μA
ILKG
I/O Pin Leakage Current
Pin at GND or VCC
2
μA
VIL
Input Low Voltage
-0.5
0.3 x VCC
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.5
V
VOL1
Output Low Voltage
IOL = 3 mA, VCC > 2.7 V
0.4
V
VOL2
Output Low Voltage
IOL = 1 mA, VCC < 2.7 V
0.2
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level for
RSWP command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC.
(3) Power Dissipation is defined as PJ = (TJ − TA)/θJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2-layer PCB.
(4) Page Mode, VCC = 3.3 V, 25°C
Doc. No. MD-1129 Rev. G
2
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
A.C. CHARACTERISTICS
(1)
VCC = 3.3 V ± 10%, TA = −40°C to +125°C
Symbol
(2)
FSCL
tHIGH
tLOW
(2)
tTIMEOUT
Parameter
Min
Max
Units
Clock Frequency
10
400
kHz
High Period of SCL Clock
600
ns
Low Period of SCL Clock
1300
ns
35
ms
(3)
SDA and SCL Rise Time
300
ns
(3)
SDA and SCL Fall Time
300
ns
tR
tF
(4)
tSU:DAT
(3)
tHD:DAT
SMBus SCL Clock Low Timeout
25
Data Setup Time
Data Hold Time (for Input Data)
100
ns
0
ns
Data Hold Time (for Output Data)
300
tSU:STA
START Condition Setup Time
600
ns
tHD:STA
START Condition Hold Time
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
tBUF
Bus Free Time Between STOP and START
1300
ns
Ti
Noise Pulse Filtered at SCL and SDA Inputs
tWR
(5)
tPU
900
100
ns
5
ms
100
ms
Write Cycle Time
Power-up Delay to Valid Temperature Recording
ns
PIN CAPACITANCE
TA = 25°C, VCC = 3.3 V, f = 1 MHz
Symbol
CIN
Parameter
Test Conditions/Comments
¯¯¯¯¯¯ Pin Capacitance
SDA, EVENT
Input Capacitance (other pins)
Min
Max
Unit
VIN = 0
8
pF
VIN = 0
6
pF
Notes:
(1) Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 4. Bus loading must be such as to allow meeting
the VIL, VOL as well as the various timing limits.
(2)
The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time-out count is
started (and then re-started) on every negative transition of SCL in the time interval between START and STOP. The minimum clock
frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02’s SPD component is DC,
while the minimum operating frequency for the TS component is limited only by the SMBus time-out.
(3)
In a “Wired-OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull-down device must be
able to sink the (external) bus pull-up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster
than SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW - tHD:DAT - tSU:DAT,
where tLOW and tHD:DAT are actual values (rather than spec limits). A shorter tHD:DAT leaves more room for a longer SDA tR, allowing for a
more capacitive bus or a larger bus pull-up resistor. At the minimum tLOW spec limit of 1300 ns, the maximum tHD:DAT of 900 ns demands a
maximum SDA tR of 300 ns. The CAT34TS02’s maximum tHD:DAT is <700 ns, thus allowing for an SDA tR of up to 500 ns at minimum tLOW.
(4)
The minimum tSU:DAT of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a tSU:DAT of 0 ns.
(5)
The first valid temperature recording can be expected after tPU at nominal supply voltage.
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1129 Rev. G
CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, TA = −25°C to +125°C, unless otherwise specified.
TS Active Current
Standby Current
(I²C-bus and SPD EEPROM idle, TS shut-down)
300
7
250
6
200
5
ISHDN (µA)
ICC (µA)
(I²C-bus and SPD EEPROM idle)
150
100
4
3
2
50
1
0
-25
0
25
50
75
100
0
125
-50
TAMB (ºC)
-25
0
25
50
75
100
125
150
TAMB (ºC)
SPD EEPROM Write Current
Temperature Read-Out Error
(I²C-bus idle, TS shut-down)
4
500
3
2
ΔT (ºC)
ICC_WR (µA)
400
300
1
Part # 2
0
Part # 1
-1
-2
200
-3
-4
100
-25
-25
0
25
50
75
100
0
25
125
50
75
100
125
TAMB (ºC)
TAMB (ºC)
EEPROM Write Time
80
5
70
4.5
60
4
tWR (ms)
TCONV (ms)
A/D Conversion Time
50
3.5
40
3
30
2.5
20
2
-25
0
25
50
75
100
125
-25
TAMB (ºC)
Doc. No. MD-1129 Rev. G
0
25
50
75
100
125
TAMB (ºC)
4
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, TA = −25°C to +125°C, unless otherwise specified.
TS POR Threshold Voltage
3.00
2.60
VTH (V)
2.20
1.80
1.40
1.00
-25
0
25
50
TAMB (ºC)
75
100
125
SPD POR Threshold Voltage
2.00
VTH (V)
1.80
1.60
1.40
1.20
1.00
-25
0
25
50
75
100
125
TAMB (ºC)
SMBus SCL Clock Low Timeout
40
tTIMEOUT (ms)
35
30
25
20
-25
0
25
50
75
100
125
TAMB (ºC)
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-1129 Rev. G
CAT34TS02
PIN DESCRIPTION
I2C/SMBUS PROTOCOL
SCL: The Serial Clock input pin accepts the Serial
Clock generated by the Master (Host).
The I C/SMBus uses two ‘wires’, one for clock (SCL)
and one for data (SDA). The two wires are
connected to the VCC supply via pull-up resistors.
Master and Slave devices connect to the bus via
their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
2
SDA: The Serial Data I/O pin receives input data
and transmits data stored in the internal registers. In
transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on
the negative edge of SCL.
Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
A0, A1 and A2: The Address pins accept the device
address. These pins have on-chip pull-down resistors.
During data transfer, the SDA line must remain
stable while the SCL line is HIGH. An SDA transition
while SCL is HIGH will be interpreted as a START or
STOP condition (Figure 1).
¯¯¯¯¯¯: The open-drain EVENT
¯¯¯¯¯¯ pin can be
EVENT
programmed to signal over/under temperature limit
conditions.
START
The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while
SCL is HIGH. The START acts as a ‘wake-up’ call to
all Slaves. Absent a START, a Slave will not
respond to commands.
POWER-ON RESET (POR)
The CAT34TS02 incorporates Power-On Reset
(POR) circuitry which protects the device against
powering up to invalid state. The TS component will
power up into conversion mode after VCC exceeds
the TS POR trigger level and the SPD component
will power up into standby mode after VCC exceeds
the SPD POR trigger level. Both the TS and SPD
components will power down into Reset mode when
VCC drops below their respective POR trigger levels.
This bi-directional POR behavior protects the
CAT34TS02 against brown-out failure following a
temporary loss of power. The POR trigger levels are
set below the minimum operating VCC level.
STOP
The STOP condition completes all commands. It
consists of a LOW to HIGH transition on SDA while
SCL is HIGH. The STOP tells the Slave that no more
data will be written to or read from the Slave.
DEVICE ADDRESSING
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address (the preamble) select either the Temperature
Sensor (TS) registers (0011) or the EEPROM memory
contents (1010), as shown in Figure 2. The next 3 bits,
A2, A1 and A0, select one of 8 possible Slave devices.
¯¯, specifies whether a Read (1) or
The last bit, R/W
Write (0) operation is being performed
DEVICE INTERFACE
ACKNOWLEDGE
The CAT34TS02 supports the Inter-Integrated
2
Circuit (I C) and the System Management Bus
(SMBus) data transmission protocols. These
protocols describe serial communication between
transmitters and receivers sharing a 2-wire data bus.
Data flow is controlled by a Ma ster device, which
generates the serial clock and the START and
STOP conditions. The CAT34TS02 acts as a Slave
device. Master and Slave alternate as transmitter
and receiver. Up to 8 CAT34TS02 devices may be
present on the bus simultaneously, and can be
individually addressed by matching the logic state of
the address inputs A0, A1, and A2.
Doc. No. MD-1129 Rev. G
A matching Slave address is acknowledged (ACK)
by the Slave by pulling down the SDA line during the
th
9 clock cycle (Figure 3). After that, the Slave will
acknowledge all data bytes sent to the bus by the
Master. When the Slave is the transmitter, the
th
Master will in turn acknowledge data bytes in the 9
clock cycle. The Slave will stop transmitting after the
Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is
illustrated in Figure 4.
6
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
Figure 1. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 2. Slave Address Bits
EEPROM
1
0
1
0
A2
A1
A0
R/W
TEMPERATURE SENSOR
0
0
1
1
A2
A1
A0
R/W
PREAMBLE
DEVICE ADDRESS
Figure 3. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 4. Bus Timing
tF
tR
tHIGH
tLOW
SCL
70%
70%
30%
70%
30%
tSU:STA
70%
tHD:DAT
tHD:STA
SDA
tSU:DAT
70%
30%
70%
30%
tSU:STO
70%
70%
30%
tBUF
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-1129 Rev. G
CAT34TS02
WRITE OPERATIONS
EEPROM Byte and TS Register Write
To write data to a TS register, or to the on-board
EEPROM, the Master creates a START condition on
the bus, and then sends out the appropriate Slave
¯¯ bit set to ‘0’), followed by an
address (with the R/W
address byte and data byte(s). The matching Slave
will acknowledge the Slave address, EEPROM byte
or TS register address and the data byte(s), one for
EEPROM data (Figure 5) and two for TS register
data (Figure 6). The Master then ends the session
by creating a STOP condition on the bus. The STOP
completes the (volatile) TS register update or starts
the internal Write cycle for the (non-volatle)
EEPROM data (Figure 7).
EEPROM Page Write
The on-board EEPROM contains 256 bytes of data,
arranged in 16 pages of 16 bytes each. A page is
selected by the 4 most significant bits of the address
byte immediatelly following the Slave address, while
the 4 least significant bits point to the byte within the
page. Up to 16 bytes can be written in one Write
cycle (Figure 8).
The internal EEPROM byte address counter is
automatically incremented after each data byte is
loaded. If the Master transmits more than 16 data
bytes, then earlier data will be overwritten by later
data in a ‘wrap-around’ fashion within the selected
page. The internal Write cycle, using the most
recently loaded data, then starts immediatelly
following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34TS02 is busy writing to EEPROM, or is ready
to accept commands. Polling is executed by
interrogating the device with a ‘Selective Read’
command (see READ OPERATIONS). The
CAT34TS02 will not acknowlwdge the Slave
address as long as internal EEPROM Write is in
progress.
DELIVERY STATE
The CAT34TS02 is shipped ‘unprotected’, i.e. neither
Software Write Protection (SWP) flag is set. The
entire 2-Kb memory is erased, i.e. all bytes are 0xFF.
Doc. No. MD-1129 Rev. G
8
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
Figure 5. EEPROM Byte Write
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SPD
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
SLAVE
A
C
K
A
C
K
Figure 6. Temperature Sensor Register Write
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
TS
SLAVE
ADDRESS
REGISTER
ADDRESS
DATA (MSB)
S
T
O
P
DATA (LSB)
P
S
A
C
K
A
C
K
SLAVE
A
C
K
A
C
K
Figure 7. EEPROM Write Cycle Timing
SCL
8th Bit
Byte n
SDA
ACK
tWR
START
CONDITION
STOP
CONDITION
ADDRESS
Figure 8. EEPROM Page Write
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SPD
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
S
T
O
P
DATA n+P
S
SLAVE
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-1129 Rev. G
CAT34TS02
READ OPERATIONS
Immediate Read
Upon power-up, the address counters for both the
Temperature Sensor (TS) and on-board EEPROM
are initialized to 00h. The TS address counter will
thus point to the Capability Register and the
EEPROM address counter will point to the first
location in memory. The two address counters may
be updated by subsequent operations.
A CAT34TS02 presented with a Slave address
¯¯ position will acknowledge
containing a ‘1’ in the R/W
the Slave address and will then start transmitting
data being pointed at by the current EEPROM data
or respectively TS register address counter. The
Master stops this transmission by responding with
NoACK, followed by a STOP (Figure 9).
Selective Read
The Read operation can be started at an address
different from the one stored in the respective
address counters, by preceeding the Immediate
Read sequence with a ‘data less’ Write operation.
The Master sends out a START, Slave address and
address byte, but rather than following up with data
(as in a Write operation), the Master then issues
another START and continuous with an Immediate
Read sequence (Figure 10).
Sequential EEPROM Read
EEPROM data can be read out indefinitely, as long
as the Master responds with ACK (Figure 11). The
internal address count is automatically incremented
after every data byte sent to the bus. If the end of
memory is reached during continuous Read, then
the address counter ‘wraps-around’ to beginning of
memory, etc. Sequential Read works with either
Immediate Read or Selective Read, the only
difference being that in the latter case the starting
address is intentionally updated.
Doc. No. MD-1129 Rev. G
10
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
Figure 9. Immediate Read
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
N
OS
AT
CO
KP
SPD
SLAVE
ADDRESS
S
P
A
C
K
SLAVE
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
DATA
TS
SLAVE
ADDRESS
N
OS
AT
CO
KP
A
C
K
P
S
A
C
K
SLAVE
DATA (MSB)
DATA (LSB)
Figure 10. Selective Read
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SPD
SLAVE
ADDRESS
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
N
OS
AT
CO
KP
SLAVE
ADDRESS
P
S
S
A
C
K
SLAVE
BUS ACTIVITY:
S
T
A
R
T
TS
SLAVE
ADDRESS
A
C
K
A
C
K
S
T
A
R
T
REGISTER
ADDRESS
DATA n
N
OS
AT
CO
KP
A
C
K
SLAVE
ADDRESS
P
S
S
A
C
K
SLAVE
A
C
K
A
C
K
DATA (MSB)
DATA (LSB)
Figure 11. EEPROM Sequential Read
BUS ACTIVITY:
MASTER
SPD
SLAVE
ADDRESS
A
C
K
A
C
K
N
O
A
C
K
A
C
K
SDA LINE
SLAVE
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
S
T
O
P
P
A
C
K
DATA n
DATA n+1
11
DATA n+2
DATA n+x
Doc. No. MD-1129 Rev. G
CAT34TS02
SOFTWARE WRITE PROTECTION
The lower half of memoryfirst
( 128 bytes) can be
protected against Write requests by setting one of two
Software Write Protection (SWP) flags.
VHV is interpreted as logic ‘1’. The VHV condition
must be established on pin A0 before the START
and maintained just beyond the STOP. Otherwise
an RSWP request could be interpreted by the
CAT34TS02 as a PSWP request.
The Permanent Software Write Protection (PSWP)
flag can be set or read while all address pins are at
regular CMOS levels (GND or VCC), whereas the very
high voltage VHV must be present on address pin A0
to set, clear or read the Reversible Software Write
Protection (RSWP) flag. The D.C. OPERATING
CONDITIONS for RSWP operations are shown in
Table 1.
2
The SWP Slave addresses follow the standard I C
convention, i.e. to read the state of the SWP flag, the
LSB of the Slave address must be ‘1’, and to set or
clear a flag, it must be ‘0’. For Write commands a
dummy byte address and dummy data byte must be
provided (Figure 12). In contrast to a regular memory
Read, a SWP Read does not return Data. Instead the
CAT34TS02 will respond with NoACK if theflag is set
and with ACK if the
flag is not set. Therefore, the
Master can immediately follow up with a STOP, as
there is no meaningful data following the ACK interval
(Figure 13).
The SWP commands are listed in Table 2. All
commands are preceded by a START and terminated
with a STOP, following the ACK or NoACK from the
CAT34TS02. All SWP related Slave addresses use
the pre-amble: 0110 (6h), instead of the regular 1010
(Ah) used for memory access. For PSWP commands,
the three address pins can be at any logic level,
whereas for RSWP commands the address pins must
be at pre-assigned logic levels.
Table 1: RSWP D.C. Operation Condition
Symbol
ΔVHV
Parameter
Test Conditions
A0 Overdrive (VHV - VCC)
IHVD
A0 High Voltage Detector Current
VHV
A0 Very High Voltage
Doc. No. MD-1129 Rev. G
Min
Max
4.8
1.7 V < VCC < 3.6 V
7
12
Units
V
0.1
mA
10
V
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
Table 2. SWP Commands
Control Pin
Levels (1)
Action
Set
PSWP
Set
RSWP
Clear
RSWP
Flag State(2)
A2
A1
A0
PSWP
RSWP
A2
A1
A0
1
A2
A1
A0
A2
A1
GND
GND
Slave Address
b7 to
b4
ACK
?
b3
b2
b1
b0
X
A2
A1
A0
X
No
0
X
A2
A1
A0
0
Yes
A0
0
X
A2
A1
A0
1
Yes
GND
VHV
1
X
0
0
1
X
No
GND
VHV
0
1
0
0
1
X
No
0
0
1
0
Yes
0110
GND
GND
VHV
0
0
GND
GND
VHV
0
0
0
0
1
1
Yes
GND
VCC
VHV
1
X
0
1
1
X
No
GND
VCC
VHV
0
X
0
1
1
0
Yes
GND
VCC
VHV
0
X
0
1
1
1
Yes
Address
Byte
ACK
?
Data
Byte
ACK
?
Write
Cycle
X
Yes
X
Yes
Yes
X
Yes
X
Yes
Yes
X
Yes
X
Yes
Yes
Figure 12. Software Write Protect (Write)
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
DATA
XXXXXXXX
XXXXXXXX
A
C
K
SLAVE
S
T
O
P
BYTE
ADDRESS
SLAVE
ADDRESS
A
C
K
P
N
A
C or O
A
K
C
K
X = Don't Care
Figure 13. Software Write Protect (Read)
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
N
A
C or O
A
K
C
K
SLAVE
Notes:
(1) Here A2, A1 and A0 are either at VCC or GND.
(2) 1 stands for ‘Set’, 0 stands for ‘Not Set’, X stands for ‘don’t care’.
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
13
Doc. No. MD-1129 Rev. G
CAT34TS02
TEMPERATURE SENSOR OPERATION
REGISTERS
The TS component in the CAT34TS02 combines a
Proportional to Absolute Temperature (PTAT)
sensor with a ∑ -Δ modulator, yielding a 12 bit plus
sign digital temperature representation.
The CAT34TS02 contains eight 16-bit wide registers
allocated to TS functions, as shown in Table 3. Upon
power-up, the internal address counter points to the
capability register.
Capability Register (User Read Only)
The TS runs on an internal clock, and starts a new
conversion cycle at least every 100 ms. The result of
the most recent conversion is stored in the
Temperature Data Register (TDR), and remains
there following a TS Shut-Down. Reading from the
TDR does not interfere with the conversion cycle.
This register lists the capabilities of the TS, as
detailed in the corresponding bit map.
Configuration Register (Read/Write)
This register controls the various operating modes of
the TS, as detailed in the corresponding bit map.
The value stored in the TDR is compared against
limits stored in the High Limit Register (HLR), the
Low Limit Register (LLR) and/or Critical
Temperature Register (CTR). If the measured
value is outside the alarm limits or above the critical
¯¯¯¯¯¯ pin may be asserted. The
limit, then the EVENT
¯¯¯¯¯¯ output function is programmable, via the
EVENT
Configuration Register for interrupt mode,
comparator mode and polarity.
Temperature Trip Point Registers (Read/Write)
The CAT34TS02 features 3 temperature limit
registers, the HLR, LLR and CLR mentioned earlier.
The temperature value recorded in the TDR is
compared to the various limit values, and the result
¯¯¯¯¯¯ pin. To avoid
is used to activate the EVENT
¯¯¯¯¯¯ pin activity, this pin is
undesirable EVENT
automatically disabled at power-up to allow the host
to initialize the limit registers and the converter to
complete the first conversion cycle under nominal
supply conditions. Data format is two’s complement
with the LSB representing 0.25°C, as detailed in the
corresponding bit maps.
The temperature limit registers can be Read or
Written by the host, via the serial interface. At
power-on, all the (writable) internal registers default
to 0x0000, and should therefore be initialized by the
¯¯¯¯¯¯ output starts
host to the desired values.The EVENT
out disabled (corresponding to polarity active low);
thus preventing irrelevant event bus activity before
the limit registers are initialized. While the TS is
enabled (not shut-down), event conditions are
normally generated by a change in measured
temperature as recorded in the TDR, but limit
changes can also trigger events as soon as the new
limit creates an event condition, i.e. asynchronously
with the temperature sampling activity.
Temperature Data Register (User Read Only)
This register stores the measured temperature, as
well as trip status information. B15, B14, and B13
are the trip status bits, representing the relationship
between measured temperature and the 3 limit
values; these bits are not affected by EVENT status
or by Configuration register settings. Measured
temperature is represented by bits B12 to B0. Data
format is two’s complement, where B12 represents
the sign, B11 represents 128°C, etc. and B0
represents 0.0625°C.
In order to minimize the thermal resistance between
sensor and PCB, it is recommended that the
exposed backside die attach pad (DAP) be soldered
to the PCB ground plane.
Manufacturer ID Register (Read Only)
The manufacturer ID assigned by the PCI-SIG trade
organization to the CAT34TS02 device is fixed at
0x1B09.
Device ID and Revision Register (Read Only)
This register contains manufacturer specific device
ID and device revision information.
Doc. No. MD-1129 Rev. G
14
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
Table 3: The TS Registers
Register Address
Register Name
Power-On Default
Read/Write
0x00
Capability Register
0x007F
Read
0x01
Configuration Register
0x0000
Read/Write
0x02
High Limit Register
0x0000
Read/Write
0x03
Low Limit Register
0x0000
Read/Write
0x04
Critical Limit Register
0x0000
Read/Write
0x05
Temperature Data Register
Undefined
Read
0x06
Manufacturer ID Register
0x1B09
Read
0x07
Device ID/Revision Register
0x0813
Read
CAPABILITY REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
B7
B6
B5
B4
B3
B2
B1
B0
EVSD
TMOUT
RFU
RANGE
ACC
EVENT
Bit
B15:B8
B7
(1)
B6
B5
B4:B3
TRES [1:0]
Description
Reserved for future use; can not be written; should be ignored; will read as 0
0: Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set (i.e. a TS
¯¯¯¯¯¯ output)
shut-down freezes the EVENT
1: Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set (i.e. a
¯¯¯¯¯¯ output)
TS shut-down de-asserts the EVENT
0: The TS implements SMBus time-out within the range 10 to 60 ms
1: The TS implements SMBus time-out within the range 25 to 35 ms
0:
1:
00:
01:
10:
11:
Pin A0 VHV compliance required for RSWP Write/Clear operations not explicitly stated
Pin A0 VHV compliance required for RSWP Write/Clear operations explicitly stated
LSB = 0.50°C (9 bit resolution)
LSB = 0.25°C (10 bit)
LSB = 0.125°C (11 bit)
LSB = 0.0625°C (12 bit)
B2
0: Positive Temperature Only
1: Positive and Negative Temperature
B1
0: ±2°C over the active range and ±3°C over the operating range (Class C)
1: ±1°C over the active range and ±2°C over the monitor range (Class B)
B0
0: Critical Temperature only
1: Alarm and Critical Temperature
Notes:
(1) Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a "1" to Configuration Register
¯¯¯¯¯¯ output can be de-asserted during TS shut-down periods)
bit 5 (EVENT
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
15
Doc. No. MD-1129 Rev. G
CAT34TS02
CONFIGURATION REGISTER
B15
B14
B13
B12
B11
RFU
RFU
RFU
RFU
RFU
B7
B6
B5
B4
B3
CLEAR
EVENT_STS
TCRIT_LOCK EVENT_LOCK
B15:B11
(1)
B10:B9
(5)
B7
(4)
B6
(4)
B5
(3)
B4
(2)
B3
(1)
B2
(7)
B1
(1), (6)
B0
(1)
B9
HYST [1:0]
B2
B8
SHDN
B1
EVENT_CTRL TCRIT_ONLY EVENT_POL
B0
EVENT_MODE
Description
Bit
B8
B10
Reserved for future use ; can not be written ; should be ignored; will read as 0
00: Disable hysteresis
01: Set hysteresis at 1.5°C
10: Set hysteresis at 3°C
11: Set hysteresis at 6°C
0: Thermal Sensor is enabled; temperature readings are updated at sampling rate
1: Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN
0: Critical trip register can be updated
1: Critical trip register cannot be modified; this bit can be cleared only at POR
0: Alarm trip registers can be updated
1: Alarm trip registers cannot be modified; this bit can be cleared only at POR
0: Always reads as 0 (self-clearing)
1: Writing a 1 to this position clears an event recording in interrupt mode only
0: EVENT output pin is not being asserted
1: EVENT output pin is being asserted
0: EVENT output disabled; polarity dependent: open-drain for B1 = 0; grounded for B1 = 1
1: EVENT output enabled
0: event condition triggered by alarm or critical temperature limit crossing
1: event condition triggered by critical temperature limit crossing only
0: EVENT output active low
1: EVENT output active high
0: Comparator mode
1: Interrupt mode
Notes:
(1) Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.
¯¯¯¯¯¯ pin, i.e. it is under the control of B3.
(2) This bit is a polarity independent ‘software’ copy of the EVENT
(3) Writing a ‘1’ to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always
returns 0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 5).
(4) Cleared at power-on reset (POR). Once set, this bit can only be cleared by a POR condition.
(5) The TS powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the TS is shut down the ADC is disabled and
the temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either
one of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time.
(6) The ¯¯¯¯¯¯
EVENT output is “open-drain” and requires an external pull-up resistor for either polarity. The “natural” polarity is “active low”, as it
allows “wired-or” operation on the EVENT bus.
(7) Can not be set as long as lock bit B6 is set.
Doc. No. MD-1129 Rev. G
16
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
HIGH LIMIT REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
0
0
0
Sign
128°C
64°C
32°C
16°C
B7
B6
B5
B4
B3
B2
B1
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C
0
0
LOW LIMIT REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
0
0
0
Sign
128°C
64°C
32°C
16°C
B7
B6
B5
B4
B3
B2
B1
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C
0
0
TCRIT LIMIT REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
0
0
0
Sign
128°C
64°C
32°C
16°C
B7
B6
B5
B4
B3
B2
B1
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C
0
0
TEMPERATURE DATA REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
TCRIT
HIGH
LOW
Sign
128°C
64°C
32°C
16°C
B7
B6
B5
B4
B3
B2
B1
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C*
0.125°C*
0.0625°C*
* When applicable (as defined by Capability bit TRES), unsupported bits will read as 0
Bit
Description
B15
0: Temperature is below the TCRIT limit
1: Temperature is equal to or above the TCRIT limit
B14
0: Temperature is equal to or below the High limit
1: Temperature is above the High limit
B13
0: Temperature is equal to or above the Low limit
1: Temperature is below the Low limit
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
17
Doc. No. MD-1129 Rev. G
CAT34TS02
REGISTER DATA FORMAT
EVENT PIN FUNCTIONALITY
The values used in the temperature data register and
the 3 temperature trip point registers are expressed in
two’s complement format. The measured temperature
value is expressed with 12-bit resolution, while the 3
trip temperature limits are set with 10-bit resolution. The
total temperature range is arbitrarily defined as 256°C,
thus yielding an LSB of 0.0625°C for the measured
temperature and 0.25°C for the 3 limit values. Bit B12 in
all temperature registers represents the sign, with a ‘0’
indicating a positive, and a ‘1’ a negative value. In two’s
complement format, negative values are obtained by
complementing their positive counterpart and adding a
‘1’, so that the sum of opposite signed numbers, but of
equal absolute value, adds up to zero.
¯¯¯¯¯¯ output reacts to temperature changes as
The EVENT
illustrated in Figure 14, and according to the operating
mode defined by the Configuration register.
¯¯¯¯¯¯ output will be
In Interrupt Mode, the enabled EVENT
asserted every time the temperature crosses one of
the alarm window limits, and can be de-asserted by
writing a ‘1’ to the clear event bit (B5) in the
configuration register. When the temperature exceeds
the critical limit, the event remains asserted as long as
the temperature stays above the critical limit and can
not be cleared.
¯¯¯¯¯¯ output is asserted
In Comparator Mode, the EVENT
outside the alarm window limits, while in Critical
¯¯¯¯¯¯ is asserted only above
Temperature Mode, EVENT
the critical limit. The exact trip limits are determined by
the 3 temperature limit settings and the hystersis
offsets, as illustrated in Figure 15.
Note that trailing ‘0’ bits, are ‘0’ irrespective of polarity.
Therefore the don’t care bits (B1 and B0) in the 10-bit
resolution temperature limit registers, are always ‘0’.
12-Bit Temperature Data Format
Binary (B12 to B0)
1
1
1
1
0
0
0
0
0
1100 1001 0000
1100 1110 0000
1110 0111 0000
1111 1111 1111
0000 0000 0000
0000 0000 0001
0001 1001 0000
0011 0010 0000
0111 1101 0000
Doc. No. MD-1129 Rev. G
Hex
Temperature
1C90
1CE0
1E70
1FFF
000
001
190
320
7D0
−55°C
−50°C
−25°C
−0.0625°C
0°C
+0.0625°C
+25°C
+50°C
+125°C
Following a TS shut-down request, the converter is
stopped and the most recently recorded temperature
¯¯¯¯¯¯ output
value present in the TDR is frozen; the EVENT
will continue to reflect the state immediatelly
preceding the shut-down command. Therefore, if the
¯¯¯¯¯¯ output creates an undesirable bus
state of the EVENT
condition, appropriate action must be taken either
before or after shutting down the TS. This may require
¯¯¯¯¯¯ output or
clearing the event, disabling the EVENT
¯¯¯¯¯¯ output polarity.
perhaps changing the EVENT
In normal use, events are triggered by a change in
recorded temperature, but the CAT34TS02 will also
respond to limit register changes. Whereas recorded
temperature values are updated at sampling rate
frequency, limits can be modified at any time. The
¯¯¯¯¯¯ output will react to limit changes as
enabled EVENT
soon as the respective registers are updated.This
feature may be useful during testing.
18
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
Figure 14. Event Detail
TEMPERATURE
CRITICAL
HYSTERESIS AFFECTS
THESE TRIP POINTS
UPPER
ALARM
WINDOW
LOWER
TIME
S/W CLEARS EVENT
EVENT IN “INTERRUPT”
EVENT IN “COMPARATOR” MODE
EVENT IN “CRITICAL TEMP ONLY” MODE
1. EVENT CANNOT BE CLEARED ONCE THE DUT TEMPERATURE IS GREATER THAN
THE CRITICAL TEMPERATURE
Figure 15. Hysteresis Detail
TH
TH – HYST
TL
TL – HYST
BELOW
WINDOW BIT
ABOVE
WINDOW BIT
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
19
Doc. No. MD-1129 Rev. G
CAT34TS02
PACKAGE OUTLINE DRAWING
TDFN 8-Pad 2 x 3 mm (VP2)
(1)
D
e
A
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A2
0.45
0.55
0.65
A3
A2
A3
FRONT VIEW
0.20
0.25
0.30
D
1.90
2.00
2.10
D2
1.30
1.40
1.50
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
L
BOTTOM VIEW
0.20 REF
b
e
L
050 TYP
0.20
0.30
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MO-229.
Doc. No. MD-1129 Rev. G
20
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT34TS02
EXAMPLE OF ORDERING INFORMATION (1)
Prefix
Device # Suffix
CAT
34TS02
VP2
G
Package
VP2: TDFN
Group ID
T4
B
Tape & Reel
T: Tape & Reel
4: 4,000/Reel
Lead Finish
G: NiPdAu
Device Revision
TOP MARKING
G
T
B
4
5
6
7
8
1
Top Mark Legend
1
2
5
2
3
(Position)
3
Device code “GTB”.
4
Assembly location code
6
Last two digits of assembly lot number
7
8
Production year (last digit)
Production month (1 - 9, O, N, D)
Pb-free microdot
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) This device used in the above example is a CAT34TS02, device revision ‘B’ in TDFN, NiPdAu Lead Frame, Tape & Reel, 4,000/Reel.
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
21
Doc. No. MD-1129 Rev. G
CAT34TS02
REVISION HISTORY
Date
06-Aug-08
Revision
A
Description
Initial Issue
15-Aug-08
B
Update Power-On Reset, Temperature Sensor Operation and Register
04-Nov-08
C
Change logo and fine print to ON Semiconductor
20-Apr-09
D
21-Jul-09
E
2-Sep-09
F
8-June-10
G
Update Features, Description, Parametric Tables, TS functionality description,
Ordering Information, Align to JC42.4 TSE2002av Standard terminology
Updated Features
Updated Parametric tables (D.C. and A.C.)
Updated Bus Timing figure
Added Typical Performance Characteristics
Updated Capability Register content
Updated Configuration Register description
Updated Ordering Information
Updated A.C. Characteristics table and notes
Updated Capability Register description and notes
Updated D.C. Operating Characteristics table
Updated POR Description
Updated Capability Register
Updated Device ID register
Updated Ordering Part Number (OPN)
Updated Marking
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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Doc. No. MD-1129 Rev. G
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For additional information, please contact your local
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© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice