NCP5359A Gate Driver for Notebook Power Systems http://onsemi.com MARKING DIAGRAMS 8 SOIC−8 D SUFFIX CASE 751 8 1 • • • • • • • • • • Faster Rise and Fall Times Thermal Shutdown Protection Adaptive Nonoverlap Circuit Floating Top Driver Accommodates Boost Voltages of up to 30 V Output Disable Control Turns Off Both MOSFETs Complies with VRM 11.1 Specifications Undervoltage Lockout Power Saving Operation Under Light Load Conditions Thermally Enhanced Package These are Pb−Free Devices 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package A L Y W G Features 5359A ALYW G DFN8 MN SUFFIX CASE 506AA 1 AA M G The NCP5359A is a high performance dual MOSFET gate driver optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. Each of the drivers can drive up to 3 nF load with a 25 ns propagation delay and 15 ns transition time. Adaptive nonoverlap and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook and desktop systems. A high floating top driver design can accommodate VBST voltage as high as 35 V, with transient voltages as high as 35 V. Bidirectional EN pin can provide a fault signal to controller when the gate driver fault detect under OVP, UVLO occur. Also, an undervoltage lockout function guarantees the outputs are low when supply voltage is low, and a thermal shutdown function provides the IC with overtemperature protection. 1 PIN CONNECTIONS 1 BST 8 DRVH PWM EN SW GND VCC Typical Applications DRVL 1 • Power Solutions for Desktop and Notebook Systems 4 AA = Device Code M = Date Code G = Pb−Free Package 8 BST PWM EN VCC DRVH SW GND DRVL (Top View) ORDERING INFORMATION Device Package Shipping† NCP5359ADR2G SOIC−8 (Pb−Free) 2500 Tape & Reel NCP5359AMNR2G DFN8 (Pb−Free) 3000 Tape & Reel NCP5359AMNTBG DFN8 (Pb−Free) 3000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2009 June, 2009 − Rev. 0 1 Publication Order Number: NCP5359A/D NCP5359A BST VCC ChipEN DRVH Level Shift and Driver Falling Edge Delay DRVH Comparator PWM > 2.2 V = 1, Else = 0 PWM + − Fault EN + 1.0 V UVLO Fault SW ChipEN Thermal Shutdown FPWM Comparator 0.8 V < PWM < 2.2 V = 1, Else 0 + − SW 1 mV GND + EN Pre −Over voltage Pre−OV 2 V/1 V R S Q Q l GND + + − Falling Edge Delay l l ChipEN VCC DRVL Driver Pre−OV Figure 1. Internal Block Diagram http://onsemi.com 2 NCP5359A 4 V to 15 V DRVH BST PWM PWM EN GND EN VCC 10 V to 13.2 V VOUT SW DRVL Figure 2. Typical Application PIN DESCRIPTION SOIC−8 DFN8 Symbol Description 1 1 BST Upper MOSFET Floating Bootstrap Supply Pin 2 2 PWM PWM Input Pin When PWM voltage is higher than 2.2 V, DRVH will set to 1 and DRVL set to 0 When PWM voltage is lower than 0.8 V, DRVL will set to 1 and DRVH set to 0 When 0.8 V < PWM < 2.2 V and SW < 0, DRVL will set to 1 When 0.8 V < PWM < 2.2 V and SW > 0, DRVL will set to 0 3 3 EN Enable Pin When OVP, TSD or UVLO has happened, the gate driver will pull the pin to low 4 4 VCC Connect to Input Power Supply 10 V to 13.2 V 5 5 DRVL Low Side Gate Drive Output 6 6 GND Ground Pin 7 7 SW 8 8 DRVH Switch Node Pin High Side Gate Drive Output http://onsemi.com 3 NCP5359A MAXIMUM RATINGS Rating Thermal Characteristics, Plastic Package Thermal Resistance Junction−to−Air Symbol SOIC−8 (20.2 sq mm, 2 oz Cu) DFN8 Value RqJA Unit °C/W 178 330 Operating Junction Temperature Range TJ 0 to +150 °C Operating Ambient Temperature Range TA 0 to +85 °C Tstg − 55 to +150 °C MSL 1 1 − Storage Temperature Range Moisture Sensitivity Level SOIC−8 DFN8 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MAXIMUM RATINGS Pin Symbol Pin Name VMAX VMIN Vcc Main Supply Voltage Input 15 V −0.3 V BST Bootstrap Supply voltage 35 V wrt / GND 40 V ≤ 50 ns wrt / GND 15V wrt / SW −0.3 V SW Switching Node (Bootstrap Supply Return) 35 V wrt / GND 40 V ≤ 50 ns wrt / GND −1 VDC −10 V (200 ns) DRVH High Side Driver Output BST + 0.3 V 35 V ≤ 50 ns wrt / GND 15V wrt / SW −0.3 V −5 V (200 ns) DRVL Low Side Driver Output Vcc + 0.3 V −0.3 V −5 V (200 ns) PWM DRVH and DRVL Control Input 6V −0.3 V EN Enable Pin 6V −0.3 V GND Ground 0V 0V 1. Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78. 2. Moisture Sensitivity Level (MSL): 1&3 per IPC/JEDEC standard: J−STD−020A. 3. The maximum package power dissipation limit must not be exceeded. PD + NOTE: TJ(max) * TA RqJA This device is ESD sensitive. Use standard ESD precautions when handling. http://onsemi.com 4 NCP5359A ELECTRICAL CHARACTERISTICS (VCC = 10 V − 13.2 V, TA = 0°C to +85°C, VEN = 5 V unless otherwise noted) Characteristics Symbol Test Conditions Min Typ Max Units 13.2 V Supply Voltage VCC Operating Voltage Power ON Reset threshold VCC 10 VPOR 2.8 V Supply Current VCC Quiescent Supply Current in Normal Operation VCC Standby Current BST Quiescent Supply Current in Normal Operation BST Standby Current IVCC_NORM IVCC_SBC EN = 5 V, PWM = OSC, FSW = 100 k CLOAD = 0 p 5.0 8.0 mA EN = GND; No switching 0.5 2.5 mA IBST1_normal PWM = +5 V, SW = 0 V 1.0 1.8 mA IBST2_normal PWM = GND, SW = 0 V 1.0 1.8 IBST1_SD PWM = +5 V 0.25 IBST2_SD PWM = GND 0.25 mA Undervoltage Lockout VCC Start Threshold VCCTH VCC UVLO Hysteresis VCCHYS Output Overvoltage Trip Threshold at Startup OVPSU 8.2 8.7 9.5 1.0 Power Startup time, VCC > 9 V. (Without trimming) 1.8 V V 2.0 V EN Input Input Voltage High VEN_HI Input Voltage Low VEN_LOW Hysteresis (Note 4) VEN_HYS Enable Pin Sink Current IEN_SINK Propagation Delay Time (Note 4) 2.0 V 1.0 500 VCC = 5.5 V V mV 4.0 mA tpdhEN 20 60 ns tpdlEN 20 60 ns 1.5 1.6 PWM Input DRVH Comparator Drop Threshold PWM Input Self Bias Voltage DRVL Comparator Rise Threshold Input Current VTH_DRVH 2.2 VPWM 1.4 V VTH_DRVL IPWM 0.8 PWM = 0 V, EN = GND 30 V V mA High Side Driver Output Resistance, Sourcing RH_TG VBST – VSW = 12 V 2.0 3.5 Output Resistance, Sinking RL_TG VBST – VSW = 12 V 1.0 2.5 W 55 kW 55 kW ns Output Resistance, unbiased (Note 4) SW Pull Down Resistance (Note 4) Transition Time (Note 6) Propagation Delay (Notes 4 & 5) BST − SW = 0 V 10 SW to GND 10 trDRVH CLOAD = 3 nF, VBST – VSW = 12 V tfDRVH CLOAD = 3 nF, VBST – VSW = 12 V 16 25 15 20 tpdhDRVH Driving High, CLOAD = 3 nF 10 35 tpdlDRVH Driving Low, CLOAD = 3 nF 15 30 W ns Low Side Driver Output Resistance, Sourcing RH_BG SW = GND 2.0 3.5 Output Resistance, Sinking RL_BG SW = VCC 1.0 2.5 W 55 kW ns Output Resistance, unbiased (Note 4) Transition Time (Note 6) Propagation Delay (Notes 4 & 5) Negative Current Detector Threshold BST − SW = 0 V 10 trDRVL CLOAD = 3 nF 16 25 tfDRVL CLOAD = 3 nF 15 20 tpdhDRVL Driving High, CLOAD = 3 nF 10 35 tpdlDRVL Driving Low, CLOAD = 3 nF 15 35 VNCDT (Note 6) Tsd (Note 6) Tsdhys (Note 6) W ns −1.0 mV 170 °C 20 °C Thermal Shutdown Thermal Shutdown Thermal Shutdown Hysteresis 4. Guaranteed by design; not tested in production . 5. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. 6. Design guaranteed. http://onsemi.com 5 150 NCP5359A Table 1. DECODER TRUTH TABLE PWM Input ZCD Greater than 2.2 V DRVL DRVH X Low High Greater than 0.8 V, but less than 2.2 V High (current through MOSFET is greater than 0) High Low Greater than 0.8 V, but less than 2.2 V Low (current through MOSFET is less than 0) Low Low X High Low Less than 0.8 V PWM tpdlDRVL DRVL tfDRVL 90% 90% 2V 10% 10% tpdhDRVH DRVH−SW tpdlDRVH trDRVH 90% 10% trDRVL tfDRVH 90% 2V 10% tpdhDRVL SW Figure 3. PWM DRVH−SW DRVL IL Figure 4. Timing Diagram http://onsemi.com 6 NCP5359A APPLICATION INFORMATION Power ON reset The NCP5359A gate driver is a single phase MOSFET driver designed for driving two N−channel MOSFETs in a synchronous buck converter topology. This driver is compatible with the NCP3418B gate drive. This gate drives operation is similar with the NCP3418B, but has two additional new features: Bidirection fault detection and multilevel PWM input. When the gate driver works with ON Semiconductor’s NCP5392 controller, it can provide a difference output logic status through multi−level PWM input. For this new feature, higher efficiency can be provided. For the bidirection fault detection function, it is used to provide a driver state information to other gate drivers and controller in a multiphase buck converter. e.g overvoltage protection (OVP) function at startup, thermal shutdown and undervoltage lockout (UVLO). This feature can provide an additional protection function for the multi−phase system when the fault condition occurs in one channel. With this additional feature, converter overall system will be more reliable and safe. Power on reset feature is used to protect a gate driver avoid abnormal status driving the startup condition. When the initial soft−start voltage is higher than 3.2 V, the gate driver will monitor the switching node SW pin. If SW pin high than 1.9 V, bottom gate will be force to high for discharge the output capacitor. The fault mode will be latch and EN pin will force to be low, unless the driver is recycle. When input voltage is higher than 9 V, the gate driver will normal operation, top gate driver DRVH and bottom gate driver will follow the PWM signal decode to a status. Adaptive Nonoverlap The nonoverlap dead time control is used to avoid the shoot through damage the power MOSFETs. When the PWM signal pull high, DRVL will go low after a propagation delay, the controller will monitors the switching node (SWN) pin voltage and the gate voltage of the MOSFET to know the status of the MOSFET. When the low side MOSFET status is off an internal timer will delay turn on of the high–side MOSFET. When the PWM pull low, gate DRVH will go low after the propagation delay (tpd DRVH). The time to turn off the high side MOSFET is depending on the total gate charge of the high−side MOSFET. A timer will be triggered once the high side MOSFET is turn off to delay the turn on the low−side MOSFET. Enable Pin The bidirection enable pin is connected with an open drain MOSFET. This pin is controlled by internal or external signal. There are three conditions will be triggered: 1. The voltage at SWN pin is higher than preset voltage at power startup. 2. The controller hits the UVLO at VCC pin. 3. The controller hits the thermal shutdown. When the internal fault has been detected, EN pin will be pull low. In this case, the drive output DRVH and DRVL will be forced low, until the fault mode remove then restart automatic. Layout Guidelines Layout is very important thing for design a DC−DC converter. Bootstrap capacitor and VCC capacitor are most critical items, it should be placed as close as to the driver IC. Another item is using a GND plane. Ground plane can provide a good return path for gate drives for reducing the ground noise. Therefore GND pin should be directly connected to the ground plane and close to the low−side MOSFET source pin. Also, the gate drive trace should be considered. The gate drives has a high di/dt when switching, therefore a minimized gate drives trace can reduce the di/dv, raise and fall time for reduce the switching loss. Undervoltage Lockout The DRVH and DRVL are held low until VCC reaches 9 V during startup. The PWM signals will control the gate status when VCC threshold is exceeded. If VCC decreases to 3.2 V below the threshold, the output gate will be forced low until input voltage VCC rises above the startup threshold. http://onsemi.com 7 NCP5359A PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NCP5359A PACKAGE DIMENSIONS DFN8 MN SUFFIX CASE 506AA−01 ISSUE D D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ TOP VIEW 0.10 C 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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