TI SN74LVCH16373ADLR

SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003
D Member of the Texas Instruments
D
D
D
D
D
D
D
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Widebus  Family
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC )
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description/ordering information
This 16-bit transparent D-type latch is designed
for 1.65-V to 3.6-V VCC operation.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
The SN74LVCH16373A is particularly suitable for
24
25
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow
the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube
SN74LVCH16373ADL
Tape and reel
SN74LVCH16373ADLR
TSSOP − DGG
Tape and reel
SN74LVCH16373ADGGR
LVCH16373A
TVSOP − DGV
Tape and reel
SN74LVCH16373ADGVR
LDH373A
SSOP − DL
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
VFBGA − GQL
VFBGA − ZQL (Pb-free)
LVCH16373A
SN74LVCH16373AGQLR
Tape and reel
SN74LVCH16373AZQLR
LDH373A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
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1
SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003
description/ordering information (continued)
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
5
6
A
A
1OE
NC
NC
NC
NC
1LE
B
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
1D4
1Q6
1Q5
VCC
GND
1D3
D
VCC
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
C
D
E
F
G
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
GND
2D6
2D5
2D8
2D7
NC
NC
2LE
H
J
2Q7
2Q8
VCC
GND
J
K
2OE
NC
NC
K
NC − No internal connection
FUNCTION TABLE
INPUTS
2
4
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1OE
1LE
1
2OE
48
2LE
C1
1D1
47
2
1D
24
25
C1
1Q1
2D1
36
To Seven Other Channels
1D
13
2Q1
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, and DL packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
Operating
VCC
VIH
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
MAX
1.65
3.6
UNIT
V
1.5
0.65 × VCC
1.7
V
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Low-level input voltage
VI
MIN
0.7
V
0.8
0
5.5
V
High or low state
0
3-state
0
VCC
5.5
V
VCC = 1.65 V
VCC = 2.3 V
−4
VCC = 2.7 V
VCC = 3 V
−12
−8
mA
−24
VCC = 1.65 V
VCC = 2.3 V
4
VCC = 2.7 V
VCC = 3 V
12
8
mA
24
10
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 µA
IOH = −4 mA
VOH
VCC
MIN
1.65 V to 3.6 V
1.65 V
VCC−0.2
1.2
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2.2
IOH = −8 mA
IOH = −12 mA
IOH = −24 mA
IOL = 100 µA
VOL
II
UNIT
V
0.2
IOL = 4 mA
IOL = 8 mA
1.65 V
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3V
0.55
VI = 0 to 5.5 V
VI = 0.58 V
3.6 V
±5
V
µA
‡
1.65 V
‡
45
2.3 V
VI = 1.7 V
VI = 0.8 V
µA
−45
75
3V
VI = 2 V
VI = 0 to 3.6 V§
Ioff
VI or VO = 5.5 V
IOZ
VO = 0 to 5.5 V
ICC
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V¶
IO = 0
One input at VCC − 0.6 V,
Other inputs at VCC or GND
∆ICC
Ci
MAX
1.65 V to 3.6 V
VI = 1.07 V
VI = 0.7 V
II(hold)
TYP†
−75
3.6 V
±500
0
±10
µA
3.6 V
±10
µA
20
3.6 V
20
2.7 V to 3.6 V
VI = VCC or GND
500
3.3 V
Co
VO = VCC or GND
3.3 V
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This information was not available at the time of publication.
§ This is the bus-hold maximum dynamic current required to switch the input from one state to another.
¶ This applies in the disabled state only.
µA
A
µA
5
pF
6.5
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
tw
tsu
MIN
‡
Pulse duration, LE high
Setup time, data before LE↓
th
Hold time, data after LE↓
‡ This information was not available at the time of publication.
MAX
VCC = 2.5 V
± 0.2 V
MIN
‡
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
3.3
3.3
ns
‡
‡
1.7
1.7
ns
‡
‡
1.2
1.2
ns
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5
SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN
†
MAX
†
MIN
†
MAX
†
Q
†
†
†
†
Q
†
†
†
†
†
†
D
tpd
LE
ten
OE
VCC = 2.5 V
± 0.2 V
tdis
Q
OE
† This information was not available at the time of publication.
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
4.9
1.6
4.2
5.3
2.1
4.6
†
5.7
1.3
4.7
ns
†
6.3
2.5
5.9
ns
ns
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per latch
Outputs enabled
Outputs disabled
VCC = 1.8 V
TYP
†
f = 10 MHz
† This information was not available at the time of publication.
6
POST OFFICE BOX 655303
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†
VCC = 2.5 V
TYP
†
†
VCC = 3.3 V
TYP
UNIT
39
6
pF
SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
VLOAD
Open
S1
RL
GND
CL
(see Note A)
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
VCC
VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
th
VI
VM
Input
VI
VM
VM
Data Input
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
tPLH
VOH
Output
VM
VM
VOL
VI
Output
Control
VM
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VM
VM
0V
tPLZ
tPZL
VLOAD/2
VM
VOL + V∆
VOL
tPHZ
tPZH
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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7
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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