TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 ULTRALOW-NOISE, HIGH PSRR, FAST RF 1.5 A LOW-DROPOUT LINEAR REGULATORS FEATURES • • • • • • • 1.5 A Low-Dropout Regulator With Enable Available in 1.8-V, 2.5-V, 2.8-V, 3-V, 3.3-V, and Adjustable (1.2-V to 5.5-V) High PSRR (49 dB at 10 kHz) Ultralow Noise (48 µVRMS, TPS79630) Fast Start-Up Time (50 µs) Stable With a 1-µF Ceramic Capacitor Excellent Load/Line Transient Response Very Low Dropout Voltage (390 mV at Full Load, TPS78630) 6-Pin SOT223-6 and 5-Pin DDPAK Package The TPS786xx family of low-dropout (LDO) low-power linear voltage regulators features high power supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in small outline, SOT223-6 and 5-pin DDPAK packages. Each device in the family is stable, with a small 1-µF ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (e.g., 390 mV at 1.5 A). Each device achieves fast start-up times (approximately 50 µs with a 0.001 µF bypass capacitor) while consuming very low quiescent current (265 µA typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 µA. The TPS78630 exhibits approximately 48 µVRMS of output voltage at 3.0 V output noise with a 0.1 µF bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR, low noise features, and the fast response time. APPLICATIONS • • • • • RF: VCOs, Receivers, ADCs Audio Bluetooth™, Wireless LAN Cellular and Cordless Telephones Handheld Organizers, PDAs DCQ PACKAGE SOT223-6 (TOP VIEW) KTT (DDPAK) PACKAGE (TOP VIEW) EN IN GND OUT NR 1 2 3 4 5 TPS78630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 80 6 GND 70 Ripple Rejection − (dB) 1 2 3 4 5 EN IN GND OUT NR TPS78630 RIPPLE REJECTION vs FREQUENCY IOUT = 1 mA 60 Output Spectral Noise Density − (µV/ Hz) • • DESCRIPTION VIN = 4 V COUT = 10 µF CNR = 0.01 µF 50 IOUT = 1.5 A 40 30 20 10 0 1 10 100 1k 10k 100k Frequency (Hz) 1M 10M 0.80 VIN = 5.5 V COUT = 2.2 µF CNR = 0.1 µF 0.70 0.60 0.50 0.40 0.30 IOUT = 1 mA 0.20 0.10 0.00 100 IOUT = 1.5 A 1k 10k 100k Frequency (Hz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a trademark of Bluetooth SIG, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2004, Texas Instruments Incorporated TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) PRODUCT VOLTAGE TPS78601 1.2 to 5.5 V TPS78618 TPS78625 1.8 V 2.5 V PACKAGE TPS78630 TPS78633 (1) 2.8 V 3.0 V 3.3 V SYMBOL SOT223-6 PS78601 DDPAK TPS78601 SOT223-6 PS78618 DDPAK TPS78618 SOT223-6 DDPAK TPS78628 TJ PS78625 -40°C to 125°C TPS78625 SOT223-6 PS78628 DDPAK TPS78628 SOT223-6 PS78630 DDPAK TPS78630 SOT223-6 PS78633 DDPAK TPS78633 PART NUMBER TRANSPORT MEDIA, QUANTITY TPS78601DCQ Tube, 78 TPS78601DCQR Tape and Reel, 2500 TPS78601KTT Reel, 500 TPS78618DCQ Tube, 78 TPS78618DCQR Tape and Reel, 2500 TPS78618KTT Reel, 500 TPS78625DCQ Tube 78 TPS78625DCQR Tape and Reel, 2500 TPS78625KTT Reel, 500 TPS78628DCQ Tube 78 TPS78628DCQR Tape and Reel, 2500 TPS78628KTT Reel, 500 TPS78630DCQ Tube 78 TPS78630DCQR Tape and Reel, 2500 TPS78630KTT Reel, 500 TPS78633DCQ Tube 78 TPS78633DCQR Tape and Reel, 2500 TPS78633KTT Reel, 500 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. ABSOLUTE MAXIMUM RATINGS over operating temperature (unless otherwise noted) (1) VALUE VIN range -0.3 V to 6 V VEN range -0.3 V to VIN + 0.3 V VOUT range 6V Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation See Dissipation Ratings table Junction temperature range, TJ -40°C to 150°C Storage temperature range, Tstg -65°C to 150°C (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 PACKAGE DISSIPATION RATINGS (1) (2) PACKAGE BOARD RΘJC RΘJA DDPAK High-K (1) 2 °C/W 23 °C/W SOT223 Low-K (2) 15 °C/W 53 °C/W The JEDEC high-K (2s2p) board design used to derive this data was a 3-in x 3-in (7,5-cm x 7,5-cm), multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. The JEDEC low-K (1s) board design used to derive this data was a 3-in x 3-in (7,5-cm x 7,5cm), two-layered board with 2 ounce copper traces on top of the board. ELECTRICAL CHARACTERISTICS Over recommended operating temperature range (TJ = -40°C to 125°C), VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1mA, COUT = 10µF, CNR = 0.01 µF, unless otherwise noted. Typical values are at 25°C. PARAMETER TEST CONDITIONS Input voltage, VIN (1) TPS78601 TPS78618 0 µA < IOUT < 1.5 A 2.8 V < VIN < 5.5 V TPS78625 0 µA < IOUT < 1.5 A TPS78628 0 µA < IOUT < 1.5 A TPS78630 0 µA < IOUT < 1.5 A 4 V < VIN < 5.5 V TPS78633 0 µA < IOUT < 1.5 A 4.3 V < VIN < 5.5 V Load regulation (∆VOUT%/VOUT) 0 µA < IOUT < 1.5 A V 0 1.5 A VFB 5.5 - VDO V 1.836 V 1.8 3.5 V < VIN < 5.5 V 2.45 2.5 2.55 V 3.8 V < VIN < 5.5 V 2.744 2.8 2.856 V 2.94 3 3.06 V 3.234 3.3 3.366 5 12 TJ = 25°C 580 TPS78630 IOUT = 1.5 A 390 550 TPS78633 IOUT = 1.5 A 340 510 Ground pin current 0 µA < IOUT < 1.5 A Shutdown current (3) VEN = 0 V, 2.7 V < VIN < 5.5 V FB pin current FB = 1.8 V Time, start-up (TPS78630) 2.4 A 260 385 µA 0.07 1 µA 1 µA 59 f = 100 Hz, IOUT = 1.5 A 52 f = 10 kHz, IOUT = 1.5 A 49 f = 100 kHz, IOUT = 1.5 A 32 RL = 2 Ω, COUT = 1 µF CNR = 0.001 µF 66 CNR = 0.0047 µF 51 CNR = 0.01 µF 49 CNR = 0.1 µF 48 CNR = 0.001 µF 50 CNR = 0.0047 µF 75 CNR = 0.01 µF mV 4.2 f = 100 Hz, IOUT = 10 mA BW = 100 Hz to 100 kHz, IOUT = 1.5 A V %/V mV 410 VOUT = 0 V Output noise voltage (TPS78630) 7 TPS78628 IOUT = 1.5 A TPS78630 UNIT 1.764 Output current limit Power supply ripple rejection MAX 5.5 Output voltage line regulation (∆VOUT%/VIN) (1) VOUT + 1 V < VIN ≤ 5.5 V Dropout voltage (2) VIN = VOUT(nom) - 0.1 V TYP 2.7 Continuous output current IOUT Output voltage MIN dB µVRMS µs 110 High-level enable input voltage 2.7 V < VIN < 5.5 V 1.7 VIN Low-level enable input voltage 2.7 V < VIN < 5.5 V 0 0.7 V EN pin current VEN = 0 -1 1 µA UVLO threshold VCC rising UVLO hysteresis (1) (2) (3) 2.25 2.65 100 V V mV Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater. Dropout is not measured for TPS78618 or TPS78625 since minimum VIN = 2.7 V. For adjustable version, this applies only after VIN is applied; then VEN transitions high to low. 3 TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION IN OUT Current Sense UVLO SHUTDOWN ILIM _ GND R1 + FB EN UVLO R2 Thermal Shutdown Quickstart Bandgap Reference 1.225 V VIN 250 kΩ External to the Device VREF FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION IN OUT UVLO Current Sense GND SHUTDOWN ILIM _ EN + R1 UVLO Thermal Shutdown R2 Quickstart VIN R2 = 40k Bandgap Reference 1.225 V 250 kΩ VREF NR Terminal Functions TERMINAL NAME DESCRIPTION ADJ FIXED NR NA 5 An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise. EN 1 1 The EN terminal is an input which enables or shuts down the device. When EN goes to a logic high, the device will be enabled. When the device goes to a logic low, the device is in shutdown mode. FB GND 5 3, Tab N/A This terminal is the feedback input voltage for the adjustable device. 3, Tab Regulator ground IN 2 2 Unregulated input to the device. OUT 4 4 Output of the regulator. 4 TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS TPS78630 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS78628 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 2.798 5 3.05 VIN = 4 V COUT = 10 µF TJ = 25°C 3.04 3.03 350 VIN = 3.8 V COUT = 10 µF VIN = 3.8 V COUT = 10 µF 340 4 2.794 IOUT = 1 mA 3.02 3.00 2.99 IGND (µA) 330 3.01 VOUT (V) VOUT (V) TPS78628 GROUND CURRENT vs JUNCTION TEMPERATURE 3 2.790 2 2.786 IOUT = 1.5 A 2.98 2.97 IOUT = 1.5 A 320 310 IOUT = 1 mA 1 2.782 300 2.96 2.95 0.0 0.3 0.6 0.9 1.2 0 2.778 −40 −25 −10 5 1.5 IOUT (A) 20 35 50 65 80 95 110 125 TJ (°C) TJ (°C) Figure 1. Figure 2. Figure 3. TPS78630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS78630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS78630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 0.80 0.70 Output Spectral Noise Density (µV/Hz) VIN = 5.5 V COUT = 2.2 µF CNR = 0.1 µF 0.60 0.50 0.40 0.30 IOUT = 1 mA 0.20 0.10 0.00 100 IOUT = 1.5 A 1k 10k Frequency (Hz) Figure 4. 100k 0.5 IOUT = 1.5 A Output Spectral Noise Density − (µV/Hz) 0.6 Output Spectral Noise Density (µV/Hz) 290 −40 −25 −10 5 20 35 50 65 80 95 110 125 VIN = 5.5 V COUT = 10 µF CNR = 0.1 µF 0.4 0.3 0.2 IOUT = 1 mA 0.1 0.0 100 1k 10k Frequency (Hz) Figure 5. 100k 3.0 2.5 CNR = 0.1 µF VIN = 5.5 V COUT = 10 µF IOUT = 1.5 A 2.0 CNR = 0.0047 µF 1.5 CNR = 0.01 µF 1.0 CNR = 0.001 µF 0.5 0.0 100 1k 10k 100k Frequency (Hz) Figure 6. 5 TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) TPS78630 ROOT MEAN SQUARED OUTPUT NOISE vs BYPASS CAPACITANCE TPS78628 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 80 80 600 VIN = 2.7 V COUT = 10 µF IOUT = 1.5 A 60 40 30 300 200 20 IOUT = 1.5 A COUT = 10 µF BW = 100 Hz to 100 kHz 10 0 0.001 µF 0.0047 µF 100 0.01 µF 10k 100k 1M VIN = 4 V COUT = 10 µF CNR = 0.1 µF 80 IOUT = 1 mA 60 IOUT = 1.5 A 40 30 20 10 0 0 1k 10k 100k 1M IOUT = 1 mA 50 10 10M VIN = 4 V COUT = 2.2 µF CNR = 0.1 µF 70 Ripple Rejection (dB) 20 100 VIN = 4 V COUT = 2.2 µF CNR = 0.01 µF 70 30 10M f (Hz) TPS78630 RIPPLE REJECTION vs FREQUENCY IOUT = 1.5 A 60 50 IOUT = 1.5 A 40 30 20 10 0 1 10 1k 100 f (Hz) 10k 100k 1M 1 10M 10 100 1k 10k 100k 1M 10M f (Hz) f (Hz) Figure 10. Figure 11. Figure 12. TPS78618 LINE TRANSIENT RESPONSE TPS78630 LINE TRANSIENT RESPONSE TPS78628 LOAD TRANSIENT RESPONSE 2 4 5 1 3 dv 1V s dt IOUT = 1.5 A COUT = 10 µF CNR = 0.01 µF IOUT (A) 6 VIN (V) 5 4 IOUT = 1.5 A COUT = 10 µF CNR = 0.01 µF 3 80 0 −30 −60 dv 1V s dt 150 40 0 −40 t (µs) Figure 13. VIN = 3.8 V COUT = 10 µF CNR = 0.01 µF di 1.5 A s dt 75 0 −75 −150 −80 20 40 60 80 100 120 140 160 180 200 0 −1 ∆VOUT (mV) ∆VOUT (mV) 30 0 1k TPS78630 RIPPLE REJECTION vs FREQUENCY 40 60 100 TPS78630 RIPPLE REJECTION vs FREQUENCY 60 2 10 Figure 9. Ripple Rejection (dB) Ripple Rejection (dB) 1 Figure 8. IOUT = 1 mA VIN (V) 20 Figure 7. 70 ∆VOUT (mV) 30 0 80 10 IOUT = 1.5 A 40 TJ (°C) 80 1 50 20 35 50 65 80 95 110 125 CNR (µF) 50 IOUT = 1 mA 60 10 0 −40 −25 −10 5 0.1 µF VIN = 4 V COUT = 10 µF CNR = 0.01 µF 70 400 50 VDO (mV) RMS Output Noise (µVRMS) 500 Ripple Rejection − (dB) 70 6 TPS78630 RIPPLE REJECTION vs FREQUENCY 0 20 40 60 80 100 120 140 160 180 200 t (µs) Figure 14. 0 100 200 300 400 500 600 700 800 900 1000 t (µs) Figure 15. TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) TPS78630 DROPOUT VOLTAGE vs OUTPUT CURRENT TPS78625 POWER UP/POWER DOWN 600 4.0 VOUT = 2.5 V RL = 1.6 Ω CNR = 0.01 µF 450 500 400 TJ = 125°C 400 2.5 VDO (mV) 2.0 1.5 TJ = 25°C 300 200 VIN TJ = 25°C 250 TJ = −40°C 200 100 100 VOUT 300 150 TJ = −40°C 1.0 0.5 TJ = 125°C 350 IOUT = 1.5 A COUT = 10 µF CNR = 0.01 µF 50 0 0 0 1 2 3 4 5 6 7 8 9 0 0 10 200 400 200 µs/Div 600 800 1000 1200 1400 2.5 3.0 3.5 IOUT (mA) 4.0 4.5 5.0 VIN (V) Figure 16. Figure 17. Figure 18. MINIMUM REQUIRED INPUT VOLTAGE vs OUTPUT VOLTAGE TPS78630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT TPS78630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT ESR − Equivalent Series Resistance (Ω 5.0 IOUT = 1.5 A 4.5 4.0 TJ = 125°C 3.5 3.0 TJ = −40°C 2.5 TJ = 25°C 100 100 COUT = 1 µF ESR − Equivalent Series Resistance (Ω) 500 mV/Div 3.0 500 VDO (mV) 3.5 Minimum VIN (V) TPS78601 DROPOUT VOLTAGE vs INPUT VOLTAGE Region of Instability 10 1 Region of Stability 0.1 0.01 2.0 1.5 2.0 2.5 3.0 VOUT (V) Figure 19. 3.5 4.0 COUT = 2.2 µF Region of Instability 10 1 Region of Stability 0.1 0.01 1 30 125 500 IOUT (mA) Figure 20. 1000 1500 1 30 125 500 1000 1500 IOUT (mA) Figure 21. 7 TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) TPS78630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT START-UP 3 COUT = 10 µF 2.50 Region of Instability 10 CNR = 0.0047 µF 2.25 Region of Stability Enable CNR = 0.001 µF 2 1 1.75 1.50 CNR = 0.01 µF 1.25 1 0.1 0.75 0.50 0.25 0.01 0 1 30 125 500 IOUT (mA) Figure 22. 8 VIN = 4 V, COUT = 10 µF, IIN = 1.5 A 2.75 VOUT (V) ESR − Equivalent Series Resistance (Ω) 100 1000 1500 0 100 200 300 400 t (ns) Figure 23. 500 600 TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 APPLICATION INFORMATION The TPS786xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (265 µA typically), and enable input to reduce supply currents to less than 1 µA when the regulator is turned off. A typical application circuit is shown in Figure 24. VIN IN VOUT OUT TPS786xx 2.2µF EN GND 1 µF NR 0.01µF Figure 24. Typical Application Circuit External Capacitor Requirements A 2.2-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS786xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. The bypass capacitor should be no more than 0.1-µf to ensure that it is fully charged during the quickstart time provided by the internal switch shown in the functional block diagram. For example, the TPS78630 exhibits only 48 µVRMS of output voltage noise using a 0.1-µF ceramic bypass capacitor and a 10-µF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250-kΩ resistor and external capacitor. Board Layout Recommendation to Improve PSRR and Noise Performance To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device. Regulator Mounting Like most low dropout regulators, the TPS786xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 1 µF. Any 1 µF or larger ceramic capacitor is suitable. The tab of the SOT223-6 package is electrically connected to ground. For best thermal performance, the tab of the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area improves heat dissipation. The internal voltage reference is a key source of noise in an LDO regulator. The TPS786xx has an NR pin which is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a low pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current Solder pad footprint recommendations for the devices are presented in an application bulletin Solder Pad Recommendations for Surface-Mount Devices, literature number AB-132, available from the TI web site (www.ti.com). 9 TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 Programming the TPS78601 Adjustable LDO Regulator C1 The output voltage of the TPS78601 adjustable regulator is programmed using an external resistor divider as shown in Figure 25. The output voltage is calculated using Equation 1: V V 1 R1 O ref R2 (1) Regulator Protection where: • VREF = 1.2246 V typ (the internal reference voltage) The TPS786xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be used for improved noise performance, but the device wastes more power. Higher values should be avoided, as leakage current at FB increases the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 µA, C1 = 15 pF for stability, and then calculate R1 using Equation 2: R1 V V O 1 ref The TPS786xx features internal current limiting and thermal protection. During normal operation, the TPS786xx limits output current to approximately 2.8 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds approximately 165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately 140°C, regulator operation resumes. R2 (2) In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. The approximate value of this capacitor can be calculated using Equation 3: VIN IN 2.2 µF OUT TPS78601 EN NR 0.01 µF GND OUTPUT VOLTAGE PROGRAMMING GUIDE VOUT R1 FB R2 C1 1 µF OUTPUT VOLTAGE R1 R2 C1 1.8 V 14.0 kΩ 30.1 kΩ 33 pF 3.6V 57.9 kΩ 30.1 kΩ 15 pF Figure 25. TPS78601 Adjustable LDO Regulator Programming 10 (3) The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is not used (such as in a unity-gain configuration), then the minimum recommended output capacitor is 2.2 µF instead of 1 µF. (3 x 10 –7) x (R1 R2) (R1 x R2) TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 THERMAL INFORMATION temperature due to the regulator's power dissipation. The temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (RΘJC), the case to heatsink (RΘCS), and the heatsink to ambient (RΘSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object's thermal resistance. The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJMAX) above which normal operation is not assured. A system designer must design the operating environment so that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJMAX). The two main environmental variables that a designer can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment for a linear regulator that is operating at a specific power level. Figure 26 illustrates these thermal resistances for (a) a SOT223 package mounted in a JEDEC low-K board, and (b) a DDPAK package mounted on a JEDEC high-K board. Equation 5 summarizes the computation: In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as shown in Equation 4: T T PDmax x R R R A θJC θCS θSA (5) P max V V I V xI D I(avg) O(avg) O(avg) I(avg) (Q) The RΘJC is specific to each regulator as determined by its package, lead frame, and die size provided in the regulator's data sheet. The RΘSA is a function of the type and size of heatsink. For example, black body radiator type heatsinks can have RΘCS values ranging from 5°C/W for very large heatsinks to 50°C/W for very small heatsinks. The RΘCS is a function of how the package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a SOT223 package, RΘCS of 1°C/W is reasonable. (4) where: • VI(avg) is the average input voltage. • VO(avg) is the average output voltage. • IO(avg) is the average output current. • I(Q) is the quiescent current. For most TI LDO regulators, the quiescent current is insignificant compared to the average output current; therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the ambient temperature (TA) and the increase in A CIRCUIT BOARD COPPER AREA J TJ A RθJC B C B B TC RθCS A C RθSA SOT223 Package (a) TA DDPAK Package (b) C Figure 26. Thermal Resistances 11 TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 Equation 5 simplifies into Equation 6: T T PDmax x R J A θJA Rearranging Equation 6 gives Equation 7: T –T R J A θJA P max D (6) (7) Using Equation 6 and the computer model generated curves shown in Figure 27 and Figure 30, a designer can quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power dissipation, and operating environment. R θJA max (125 55)°C2.5 W 28°CW 40 ° C/W No Air Flow 35 150 LFM 30 250 LFM 25 20 15 0.1 DDPAK Power Dissipation The DDPAK package provides an effective means of managing power dissipation in surface mount applications. The DDPAK package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the DDPAK package enhances the thermal performance of the package. To illustrate, the TPS78625 in a DDPAK package was chosen. For this example, the average input voltage is 5 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is shown in Equation 8: P Dmax (5 2.5) V x 1 A 2.5 W (8) Substituting TJmax for TJ into Equation 6 gives Equation 9: 12 (9) From Figure 27, DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be 1 cm2 for the part to dissipate 2.5 W. The operating environment used in the computer model to construct Figure 27 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 28 shows the side view of the operating environment used in the computer model. Rθ JA − Thermal Resistance − Even if no external black body radiator type heatsink is attached to the package, the board on which the regulator is mounted provides some heatsinking through the pin solder connections. Some packages, like the DDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board's ground plane for additional heatsinking to improve their thermal performance. Computer-aided thermal modeling can be used to compute very accurate approximations of an integrated circuit's thermal performance in different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks, and different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between junction and ambient (RΘJA). This RΘJA is valid only for the specific operating environment used in the computer model. 1 10 Copper Heatsink Area − cm2 100 Figure 27. DDPAK Thermal Resistance vs Copper Heatsink Area 2 oz. Copper Solder Pad with 25 Thermal Vias 1 oz. Copper Power Plane 1 oz. Copper Ground Plane Thermal Vias, 0.3 mm Diameter, 1,5 mm Pitch Figure 28. DDPAK Thermal Resistance TPS78601, TPS78618 TPS78625, TPS78628 TPS78630, TPS78633 www.ti.com SLVS389D – SEPTEMBER 2002 – REVISED OCTOBER 2004 From the data in Figure 29 and rearranging Equation 6, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed. 5 dissipate 800 mW. The operating environment used to construct Figure 30 consisted of a board with 1 oz. copper planes. The package is soldered to a 1 oz. copper pad on the top of the board. The pad is tied through thermal vias to the 1 oz. ground plane. 180 ° C/W 4 250 LFM Rθ JA − Thermal Resistance − PD − Maximum Power Dissipation − W TA = 55°C 150 LFM 3 No Air Flow 2 No Air Flow 160 140 120 100 80 60 40 20 1 10 Copper Heatsink Area − cm2 100 Figure 29. Maximum Power Dissipation vs Copper Heatsink Area SOT223 Power Dissipation The SOT223 package provides an effective means of managing power dissipation in surface mount applications. The SOT223 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the SOT223 package enhances the thermal performance of the package. To illustrate, the TPS78625 in a SOT223 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, no air flow is present, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is calculated as shown in Equation 10: P Dmax (3.3 2.5) V x 1 A 800 mW (10) Substituting TJmax for TJ into Equation 6 gives Equation 11: R max (125 55)°C800 mW 87.5°CW θJA (11) From Figure 30, RΘJA vs PCB Copper Area, the ground plane needs to be 0.55 in2 for the part to 0 0.1 1 PCB Copper Area − in2 10 Figure 30. SOT223 Thermal Resistance vs PCB Area From the data in Figure 30 and rearranging Equation 6, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed (see Figure 31). 6 TA = 25°C 5 4 4 in2 PCB Area PD (W) 1 0.1 3 0.5 in2 PCB Area 2 1 0 0 25 50 75 100 125 150 TA − Ambient Temperature − °C Figure 31. SOT223 Power Dissipation 13 PACKAGE OPTION ADDENDUM www.ti.com 13-Oct-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY TPS78601DCQ ACTIVE SOP DCQ 6 49 TPS78601DCQR ACTIVE SOP DCQ 6 2500 TPS78601KTT OBSOLETE PFM KTT 5 TPS78601KTTR ACTIVE PFM KTT 5 500 TPS78601KTTT ACTIVE PFM KTT 5 50 TPS78618DCQ ACTIVE SOP DCQ 6 78 TPS78618DCQR ACTIVE SOP DCQ 6 2500 TPS78618KTT OBSOLETE PFM KTT 5 TPS78618KTTR ACTIVE PFM KTT 5 500 TPS78618KTTT ACTIVE PFM KTT 5 50 TPS78625DCQ ACTIVE SOP DCQ 6 78 TPS78625DCQR ACTIVE SOP DCQ 6 2500 TPS78625KTT OBSOLETE PFM KTT 5 TPS78625KTTR ACTIVE PFM KTT 5 500 TPS78625KTTT ACTIVE PFM KTT 5 50 TPS78628DCQ ACTIVE SOP DCQ 6 78 TPS78628DCQR ACTIVE SOP DCQ 6 2500 TPS78628KTT OBSOLETE PFM KTT 5 TPS78628KTTR ACTIVE PFM KTT 5 500 TPS78628KTTT ACTIVE PFM KTT 5 50 TPS78630DCQ ACTIVE SOP DCQ 6 78 TPS78630DCQR ACTIVE SOP DCQ 6 2500 TPS78630KTT OBSOLETE PFM KTT 5 TPS78630KTTR ACTIVE PFM KTT 5 500 TPS78630KTTT ACTIVE PFM KTT 5 50 TPS78633DCQ ACTIVE SOP DCQ 6 78 TPS78633DCQR ACTIVE SOP DCQ 6 2500 TPS78633KTT OBSOLETE PFM KTT 5 TPS78633KTTR ACTIVE PFM KTT 5 500 TPS78633KTTT ACTIVE PFM KTT 5 50 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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