NTMFS4834N Power MOSFET 30 V, 130 A, Single N−Channel, SO−8FL Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices* http://onsemi.com V(BR)DSS Applications • • • • RDS(ON) MAX ID MAX 3.0 mW @ 10 V Refer to Application Note AND8195/D CPU Power Delivery DC−DC Converters Low Side Switching 30 V 130 A 4.0 mW @ 4.5 V D (5,6) MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Symbol Value Unit VDSS VGS 30 ±20 21 V V Continuous Drain Current RqJA (Note 1) TA = 25°C Power Dissipation RqJA (Note 1) TA = 25°C PD 2.31 W Continuous Drain Current RqJA (Note 2) TA = 25°C ID 13 A Power Dissipation RqJA (Note 2) ID TA = 85°C Steady State Continuous Drain Current RqJC (Note 1) TC = 25°C Power Dissipation RqJC (Note 1) TC = 25°C A N−CHANNEL MOSFET 0.9 PD 86.2 W IDM 260 A TJ, TSTG −55 to +150 °C Source Current (Body Diode) Drain to Source DV/DT Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 32 Apk, L = 1.0 mH, RG = 25 W) IS dV/dt EAS 71 6 512 A V/ns mJ Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL TC = 85°C Operating Junction and Storage Temperature A 93 260 °C *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. May, 2010 − Rev. 5 S S S G 1 SO−8 FLAT LEAD CASE 488AA STYLE 1 4834N AYWWG G D D D A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2010 D W 130 TA = 25°C, tp = 10 ms MARKING DIAGRAM 9.5 PD ID Pulsed Drain Current S (1,2,3) 15 TA = 85°C TA = 25°C G (4) 1 Device Package Shipping† NTMFS4834NT1G SO−8FL (Pb−Free) 1500 Tape / Reel NTMFS4834NT3G SO−8FL (Pb−Free) 5000 Tape / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTMFS4834N/D NTMFS4834N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Junction−to−Case (Drain) Parameter RqJC 1.45 Junction−to−Ambient – Steady State (Note 3) RqJA 54 Junction−to−Ambient – Steady State (Note ) RqJA 138.7 Unit °C/W 3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 21 VGS = 0 V, VDS = 24 V mV/°C TJ = 25 °C 1 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) 1.5 6.1 VGS = 10 V to 11.5 V ID = 30 A 2.6 ID = 15 A 2.5 VGS = 4.5 V ID = 30 A 3.5 ID = 15 A 3.4 gFS VDS = 15 V, ID = 15 A mV/°C 3.0 4.0 35.2 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance 4500 VGS = 0 V, f = 1 MHz, VDS = 12 V 960 CRSS 500 Total Gate Charge QG(TOT) 32 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge VGS = 4.5 V, VDS = 15 V; ID = 30 A 5.4 12 pF 48 nC 11 QG(TOT) VGS = 11.5 V, VDS = 15 V; ID = 30 A 74 nC SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) 20 tr td(OFF) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 34 22 tf 23 td(ON) 11 tr td(OFF) VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 23 37 15 5. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns ns NTMFS4834N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max TJ = 25°C 0.77 1.2 TJ = 125°C 0.70 Unit DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 30 A tRR ta tb V 34 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A 18 ns 16 QRR 25.9 nC Source Inductance LS 0.65 nH Drain Inductance LD 0.005 nH Gate Inductance LG 1.84 nH Gate Resistance RG 1.4 W PACKAGE PARASITIC VALUES TA = 25°C 5. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTMFS4834N TYPICAL PERFORMANCE CURVES 200 VGS = 5 to 6 V 160 160 4.0 V 140 120 120 100 3.6 V 80 60 3.4 V 40 3.2 V 20 3.0 V 0 1 2 3 60 TJ = 25°C 40 TJ = 125°C 20 TJ = −55°C 1 0 2 3 4 5 6 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 30 ID = 30 A TJ = 25°C 25 20 15 10 5 0 80 0 5 4 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 140 3.8 V 100 0 VDS ≥ 10 V 180 4.2 V TJ = 25°C ID, DRAIN CURRENT (AMPS) 180 2 4 8 6 10 12 0.007 TJ = 25°C 0.006 0.005 VGS = 4.5 V 0.004 0.003 VGS = 11.5 V 0.002 0.001 0 10 15 25 20 30 35 40 45 50 55 60 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100,000 2.0 VGS = 0 V ID = 30 A VGS = 10 V 1.0 0.5 0 −50 TJ = 150°C 10,000 1.5 IDSS, LEAKAGE (nA) ID, DRAIN CURRENT (AMPS) 200 1,000 TJ = 125°C 100 10 −25 0 25 50 75 100 125 150 2 4 8 12 16 20 24 28 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 30 NTMFS4834N TJ = 25°C VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 12 6500 6000 Ciss 5500 5000 4500 4000 3500 3000 2500 Crss 2000 1500 1000 500 0 15 10 Ciss Coss 5 0 5 VGS VDS 10 15 20 25 30 16 VDS 8 10 6 8 4 2 0 0 20 15 10 5 0.4 1 ms 0.1 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D, DRAIN CURRENT (AMPS) 100 ms 1 0.5 0.6 0.7 0.8 0.9 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.1 Figure 10. Diode Forward Voltage vs. Current 10 ms VGS = 20 V SINGLE PULSE TC = 25°C 2 VGS = 0 V TJ = 25°C 25 0 100 1000 10 4 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 QG, TOTAL GATE CHARGE (nC) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 100 6 ID = 30 A TJ = 25°C IS, SOURCE CURRENT (AMPS) t, TIME (ns) td(off) tr tf td(on) 10 RG, GATE RESISTANCE (W) Qgd Qgs 30 VDS = 15 V ID = 15 A VGS = 11.5 V 1 14 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 100 1 VGS 12 Figure 7. Capacitance Variation 10 18 10 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 20 QT VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) TYPICAL PERFORMANCE CURVES 560 520 480 440 400 360 320 280 240 200 160 120 80 40 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area ID = 32 A 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 NTMFS4834N PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA−01 ISSUE D 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D 2 A B D1 2X 0.20 C 4X E1 1 2 3 q E 2 c A1 4 TOP VIEW C 3X e 0.10 C SEATING PLANE DETAIL A A MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.15 BSC 4.50 4.90 5.10 3.50 −−− 4.22 6.15 BSC 5.50 5.80 6.10 3.45 −−− 4.30 1.27 BSC 0.51 0.61 0.71 0.51 −−− −−− 0.51 0.61 0.71 0.05 0.17 0.20 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q 0.10 C SIDE VIEW 8X 0.10 C A B c STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN e/2 L 1 4 K G 3X 4X 1.270 b 0.05 PIN 5 (EXPOSED PAD) SOLDERING FOOTPRINT* DETAIL A 0.750 4X 1.000 0.965 1.330 2X 0.905 2X E2 L1 0.495 M 4.530 3.200 0.475 D2 2X 1.530 BOTTOM VIEW 4.560 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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