VGA Port Companion Circuit PACVGA201 Features Product Description • The PACVGA201 provides seven channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection is implemented with current-steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-2 Level-4 ESD Protection (±8kV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated. • • • • • • Seven channels of ESD protection for all VGA port connector pins Meets IEC-61000-4-2 Level-4 ESD requirements (±8kV contact discharge) Very low loading capacitance from ESD protection diodes on VIDEO lines, 4pF typical TTL to CMOS level-translating buffers with power down mode for HSYNC and VSYNC lines Three power supplies for design flexibility Compact 16-pin QSOP package RoHS compliant (lead-free) finishing Applications • • • • ESD protection and termination resistors for VGA (video) port interfaces Desktop PCs Notebook computers LCD monitors Separate positive supply rails are provided for the VIDEO, DDC_OUT and SYNC channels to facilitate interfacing with low-voltage video controller ICs and to provide design flexibility in multiple-supply-voltage environments. An internal diode (D1, in schematic below) is provided such that VCC2 is derived from VCC3 (VCC2 does not require an external power supply input). In applications where VCC3 may be powered down, diode D1 blocks any DC current path from the DDC_OUT pins back to the powered down VCC3 rail via the upper ESD protection diodes. Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC_IN1, SYNC_IN2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC3. When the PWR_UP input is driven LOW, the SYNC outputs are driven LOW and the SYNC inputs can float: no current will be drawn from the VCC3 supply. The PACVGA201 is housed in a 16-pin QSOP package with RoHS compliant lead-free finishing. ©2010 SCILLC. All rights reserved. May 2010 Rev. 3 Publication Order Number: PACVGA201/D PACVGA201 Simplified Electrical Schematic VCC1 2 VCC3 VCC2 D1 8 VIDEO_1 VIDEO_2 VIDEO_3 GND 1 15 3 RB 5 16 6 14 12 DDC_OUT1 DDC_OUT2 SYNC_IN1 SYNC_IN2 SD1 4 9 GND 7 10 RP 11 13 GND To p View VCC3 1 16 SD2 VCC1 2 15 SD1 VIDEO_1 3 14 SYNC_OUT2 VIDEO_2 4 13 SYNC_IN2 VIDEO_3 5 12 SYNC_OUT1 GND 6 11 SYNC_IN1 PWR_UP 7 10 DDC_OUT2 VCC2 8 9 DDC_OUT1 16-Pin QSOP Rev. 3 | Page 2 of 8 | www.onsemi.com SD2 SYNC_OUT2 SYNC_OUT1 PWR_UP PACVGA201 Ordering Information PART NUMBERING INFORMATION Pins Package Ordering Part Number1 Part Marking 16 QSOP PACVGA201QR PACVGA 201QR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. PIN DESCRIPTIONS Pins(s) NAME DESCRIPTION 1 VCC3 VCC3 supply pin. This is an isolated supply input for the two sync buffers and SD1 and SD2 ESD protection circuits. 2 VCC1 VCC1 supply pin. This is an isolated supply pin for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits. 3 VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 4 VIDEO_2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 5 VIDEO_3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 6 GND 7 PWR_UP 8 VCC2 9 DDC_OUT1 DDC_OUT1 ESD protection channel. 10 DDC_OUT2 DDC_OUT2 ESD protection channel 11 SYNC_IN1 Sync signal buffer input. Connects to the VGA Controller side of one of the sync lines. 12 SYNC_OUT1 13 SYNC_IN2 14 SYNC_OUT2 15 SD1 ESD protection channel input. 16 SD2 ESD protection channel input. Ground reference supply pin. Enables the sync buffers when high. When PWR_UP is low the sync outputs are forced low and the inputs can be floated. VCC2 supply pin. This is an isolated supply pin for the DDC_OUT1 and DDC_OUT2 ESD protection circuits. Internally, VCC2 is derived from the VCC3 input if the VCC2 input is not connected to a supply voltage. Sync signal buffer output. Connects to the video connector side of one of the sync lines. Sync signal buffer input. Connects to the VGA Controller side of one of the sync lines. Sync signal buffer output. Connects to the video connector side of one of the sync lines. Rev. 3 | Page 3 of 8 | www.onsemi.com PACVGA201 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER VCC1,VCC2 and VCC3 Supply Voltage Inputs Diode Forward Current (one diode conducting at a time) DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2 Operating Temperature Range Storage Temperature Range Package Power Rating Rev. 3 | Page 4 of 8 | www.onsemi.com RATING UNITS [GND - 0.5] to +6.0 V 20 mA [GND - 0.5] to [VCC1 + 0.5] [GND - 0.5] to [VCC2 + 0.5] [GND - 0.5] to [VCC3 + 0.5] V V V 0 to +70 °C -65 to +150 °C 750 mW PACVGA201 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP ICC1 VCC1 Supply Current VCC1 = 5.0V ICC3 VCC3 Supply Current VCC3 = 5V; SYNC inputs at GND or VCC3; PWR_UP pin at VCC3; SYNC ouputs unloaded 10 μA VCC3 = 5V; SYNC inputs at 3.0V; PWR_UP pin at VCC3; SYNC ouputs unloaded 200 μA VCC3 = 5V; PWR_UP input at GND; SYNC ouputs unloaded UNITS 10 μA 10 VCC2 VCC2 Pin Open Circuit Voltage VCC2 voltage internally derived from VCC3 via diode D1; no external current drawn VIH Logic High Input Voltage VCC3 = 5V; Note 2 VIL Logic Low Input Voltage VCC3 = 5V; Note 2 VOH Logic High Output Voltage IOH = -4mA, VCC3 = 5.0V; Note 3 VOL Logic Low Output Voltage IOL = 4mA, VCC3 = 5.0V; Note 3 Resistor Value PWR_UP = VCC3 = 5.0V IIN Input Current VIDEO_x pins HSYNC, VSYNC pins VCC1 = 5.0V; VIN = VCC1 or GND VCC3 = 5.0V; VIN = VCC3 or GND CIN Input Capacitance on VIDEO_1, VIDEO_2 and VIDEO_3 pins VCC1 = 5.0V; VIN = 2.5V; measured at 1MHz VCC1 = 2.5V; VIN = 1.25V; measured at 1MHz 4 4.5 RB, RP MAX [VCC3 0.80] V 2.0 V 0.8 4.4 0.5 μA V V 1 0.4 V 2 MΩ ±1 ±1 μA μA pF pF tPLH SYNC Buffer L => H Propagation Delay CL = 50pF; VCC3 = 5.0V; Input tR and tF ≤ 5ns 8 12 ns tPHL SYNC Buffer H => L Propagation Delay CL = 50pF; VCC3 = 5.0V; Input tR and tF ≤ 5ns 8 12 ns tR, tF SYNC Buffer Output Rise & Fall Times CL = 50pF; VCC3 = 5.0V; Input tR and tF ≤ 5ns 7.0 VESD ESD Withstand Voltage VCC1 = VCC2 = VCC3 = 5V; Note 4 Note 1: Note 2: Note 3: Note 4: ±8 ns kV All parameters specified over standard operating conditions unless otherwise noted. These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP. These parameters apply only to SYNC_OUT1 and SYNC_OUT2. Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VCC1, VCC2 and VCC3 must be bypassed to GND via a low impedance ground plane with a 0.2uF or greater, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015). Rev. 3 | Page 5 of 8 | www.onsemi.com PACVGA201 Application Information Figure 1. Typical Connection Diagram A resistor may be necessary between the VCC2 pin and ground if protection against a stream of ESD pulses is required while the PACVGA201 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into the VCC2 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PACVGA201 is in the power-up state, an internal discharge resistor is connected to ground via a FET switch for this purpose. For the same reason, VCC1 and VCC3 may also require bypass capacitor discharging resistors to ground if there are no other components in the system to provide a discharge path to ground. Rev. 3 | Page 6 of 8 | www.onsemi.com PACVGA201 Mechanical Details QSOP Mechanical Specifications PACVGA201 devices are supplied in 16-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-16, see the California Micro Devices QSOP Package Information document. PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins 16 Millimeters Inches Dimensions Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.81 3.98 0.150 0.157 e 0.64 BSC 0.025 BSC H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs Package Dimensions for QSOP-16 Controlling dimension: inches * This is an approximate number which may vary. Rev. 3 | Page 7 of 8 | www.onsemi.com PACVGA201 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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