Ordering number : ENA0919 Bi-CMOS IC LV8095LQ For VCMs Constant-current Driver IC Overview The LV8095LQ is a constant current driver IC for voice coil motors. It supports I2C control and integrates a digital/analog converter (DAC). Its ultraminiature package makes the IC ideal for constant-current driving the voice coil motors (AF and ZM) used in a wide variety of portable equipment including camera cell-phones. Features • Constant current driver for voice coil motors. • Constant current control enabled by DAC (8 bits). • Wide operating voltage range (2.5 to 5.5V). • I2C bus control supported. • No external capacitors needed (capacitor-less). • Ultraminiature package (USLP8 : 2.0×1.3×0.56mm) for easy soldering. • Built-in thermal protection circuit. • Built-in voltage drop protection circuit. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max -0.3 to +5.5 V Maximum VDD voltage VDD max -0.3 to +5.5 V OUT1 -0.3 to +6.0 V SCL, SDA, PD -0.3 to +5.5 Output voltage VOUT max Input voltage VIN max GND pin source current Allowable power dissipation IGND Pd max *Mounted on a specified board. V 200 mA 650 mW Operating temperature Topr -30 to +85 °C Storage temperature Tstg -40 to +150 °C * Specified board : 50mm×40mm×0.8mm, 4-layer glass epoxy circuit board. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. O3107 MS PC 20070827-S00002 No.A0919-1/8 LV8095LQ Allowable Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage VCC 2.5 to 5.0 VDD voltage VDD 1.3 to 5.0 Maximum preset output current IO High-level input voltage VIH Low-level input voltage VIL V V 200 Applied to SCL, SDA, and PD pins mA 0.8×VDD to VDD V -0.3 to 0.2×VDD V Electrical Characteristics Ta = 25°C, VCC = 2.8V, VDD = 2.8V Parameter Symbol Ratings Conditions min Supply current Input current max ICCO PD = 0V 0.1 1 µA ICC1 PD = 2.8V 0.5 3 mA IIN Output saturation voltage Unit typ VIN = 2.8V, VENA = 2.8V Vsat1 -1 SW : ON, SW : b, Full code setting, 0 1 µA 0.10 0.18 V 0.20 0.4 V ±1 LSB IOUT = 50mA Vsat2 SW : ON, SW : b, Full code setting, IOUT = 100mA DAC block Resolution RF = 1Ω, SW1 : OFF, SW2 : a Relative accuracy INL RF = 1Ω, SW1 : OFF, SW2 : a Differential linearity DNL RF = 1Ω, SW1 : OFF, SW2 : a Full code current Ifull RF = 1Ω, SW1 : OFF, SW2 : a Izero RF = 1Ω, SW1 : OFF, SW2 : a Error code current 0 8 95 bits ±1 LSB 100 105 mA 1 4 mA 1 µA 1.3 V Spark killer diode Reverse current IS (leak) Forward voltage VSF IOUT = 200mA * *1 : Design guaranteed value (no measurement is performed) Package Dimensions unit : mm (typ) 3348 TOP VIEW SIDE VIEW BOTTOM VIEW (0.18) 2.0 1.3 (0.65) 8 2 SIDE VIEW 0.5 (0.25) 0.6MAX 0.25 1 0.3 2 0.0NOM 1 0.14 Allowable power dissipation, Pd max – W 0.8 0.7 Pd max -- Ta Specified board : 50.0×40.0×0.8mm3 4-layer glass epoxy (2S2P) 0.65 0.6 0.5 0.4 0.34 0.3 0.2 0.1 0 – 30 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C SANYO : USLP8(1.3X2.0) No.A0919-2/8 LV8095LQ Pin Assignment USLP8 (Top View) PD SCL 8 7 SDA 6 VDD Pin No. Pin Name 1 GND 5 1 2 3 4 GND RFG OUT VCC Pin Description Ground 2 RFG Current sensing resistor connection 3 OUT Output pin 4 VCC Analog system power supply 5 VDD Logic system power supply *1 6 SDA I2C SDA input 7 SCL I2C SCL input 8 PD Power-down & reset *2 *1 : The voltage applied to the VDD pin must be set to the same level as those of the SDA, SCL and PD input high-level voltages. *2 : Setting the PD pin to low level powers down and resets the IC. Set this pin temporarily to low level, then to high level after power-on, and keep it to high level (same voltage level as VDD) during normal operation. Block Diagram VCC 0.1µF Reference voltage VDD Voltage drop protection & thermal protection VCM SDA C P U SCL I2C IF I2C DECODE DAC 8 bits current setting + - OUT PD RFG GND RF 1Ω Wiring resistance (thick line) around the RF is added to the resistance of RF as an error. It must be kept as small as possible. Formula for calculating constant current : IOUT = 0.1 ÷ RF If, for instance, IOUT is to be set to 100mA max : RF = 0.1 ÷ (100mA) RF = 1Ω Notes on use • Determine the preset current value using the resistor between RFG and GND according to the formula above. • The recommended RF value is 1Ω. No.A0919-3/8 LV8095LQ Pin Description Pin No. Pin Name Description 1 GND Ground pin 2 RFG 2 : RFG 3 OUT Current detection resistor connection pin Equivalent Circuit VCC The current detection resistor (1Ω) is connected between this pin and GND to detect the output current and perform constant current control. 3 3 : OUT Output pin This is an NMOS open drain output, and the voice coil 2 motor is connected between this pin and the VCC pin for 1kΩ use. 4 5 VCC VDD 4 : VCC Power supply input pin 5 : VDD This is separate from the VCC power supply pin for the SDA, SCL and PD logic input, and it is used while the same voltage as that for the high level of these logic input is applied to it. 6 SDA I2C serial data input pin VDD Input high level : 0.8 × VDD or higher Input low level : 0.2 × VDD or lower 1kΩ 6 GND 7 SCL 7 : SCL 8 PD I2C serial clock input pin VDD 8 : PD Power down and reset When low, power-down and reset is performed at the same time. This pin is held high for normal use. In normal operation, however, this pin must be set low 7 1kΩ 8 temporarily and an initial reset must be applied after VCC starts up. Input high level : 0.8 × VDD or higher GND Input low level : 0.2 × VDD or lower No.A0919-4/8 LV8095LQ Serial Bus Communication Specifications I2C serial transfer timing conditions Standard mode twH SCL th1 twL th2 tbuf SDA th1 ts2 ts1 ts3 Resend start condition Start condition ton Stop condition tof Input waveform condition Standard mode Parameter symbol Conditions min typ unit fscl SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 4.7 ts2 Setup time of SDA with respect to the rising edge of SCL 250 ns ts3 Setup time of SCL with respect to the rising edge of SDA 4.0 µs th1 Hold time of SCL with respect to the rising edge of SDA 4.0 µs th2 Hold time of SDA with respect to the falling edge of SCL 0 µs twL SCL low period pulse width 4.7 µs twH SCL high period pulse width 4.0 ton SCL, SDA (input) rising time 1000 ns tof SCL, SDA (input) falling time 300 ns tbuf Interval between stop condition and start condition Data hold time Pulse width Input waveform conditions Bus free time 0 max SCL clock frequency 100 kHz µs µs µs 4.7 High-speed mode Parameter Symbol Conditions min typ unit fscl SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 0.6 ts2 Setup time of SDA with respect to the rising edge of SCL 100 ns ts3 Setup time of SCL with respect to the rising edge of SDA 0.6 µs th1 Hold time of SCL with respect to the rising edge of SDA 0.6 µs th2 Hold time of SDA with respect to the falling edge of SCL 0 µs twL SCL low period pulse width 1.3 µs twH SCL high period pulse width 0.6 ton SCL, SDA (input) rising time 300 ns tof SCL, SDA (input) falling time 300 ns tbuf Interval between stop condition and start condition Data hold time Pulse width Input waveform conditions Bus free time 0 max SCL clock frequency 1.3 400 kHz µs µs µs No.A0919-5/8 LV8095LQ I2C bus transmission method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation. SCL SDA ts2 th2 When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high. Start condition Stop condition th1 ts3 SCL SDA Data transfer and acknowledgement response After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I2C bus, a unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) indicating the transfer direction of the subsequent data. However, this IC is provided with only a write mode for receiving the data. Every time 8 bits of data for each byte are transferred, the ACK signal is sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status, the receiving end releases SDA at the falling edge of the ninth SCL clock. Start M S B Slave address L S B W A C K M S B Data L S B A C K M S B Data L S B A C K Stop SCL 1st byte SDA (WRITE) A1 A2 A3 A4 A5 A6 A7 0 2nd byte 3ed byte PD X D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X : DON'T CARE No.A0919-6/8 LV8095LQ The standard data transfer to this device consists of three bytes : the slave address of the first byte and the data of the second and third bytes. The table below shows the format of the second and third bytes. 2nd byte 3rd byte Serial data bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Function PD × D7 D6 D5 D4 D3 D2 D1 D0 × × × × × × Slave address : 0110011(0) PD : Power-down D1-D7 : 8-bit data used to set output constant current ; MIN = 00000000, MAX = 11111111 D0-D7 setting method (output current design values assume an RF of 1Ω) Output setting Output current (mA) (LSB) (design value) Current setting code D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0.392 2 0 0 0 0 0 1 0 2 0.784 254 1 1 1 1 1 1 0 254 99.608 255 1 1 1 1 1 1 1 255 100 Specified Test Circuit A A A 8 7 6 5 PD SCL SDA VDD GND RFG OUT VCC 1 2 3 4 1µF A 1µF SW2 b SW1 1Ω a A 15Ω V No.A0919-7/8 LV8095LQ SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2007. Specifications and information herein are subject to change without notice. PS No.A0919-8/8