Ordering number : ENA0597 Monolithic Linear IC LA6559 For CD 5-Channel Driver (BTL : Four-Channel, H Bridge : One-Channel) Overview The LA6559 is a 5-channel driver (BTL : 4-channel, H bridge : 1-channel) for CD players. Functions • Power amplifier 5-channel built-in. (Bridge-connection (BTL) : 4-channel, H bridge : 1-channel) • IO max 1A • Level shift circuit built-in (except H bridge). • Mute circuit (output ON/OFF) built-in. (Operable with BTL AMP with MUTE1 : CH1 and MUTE2 : CH2 to 4 and not operable for the H bridge of 3.3VREG) • 3.3V regulator built-in (external PNP transistor). • With a function to set the loading output voltage • Overheat protection circuit (thermal shutdown) built-in. Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage Symbol Conditions Ratings VCC max Allowable power dissipation Pd max Maximum output current IO max Maximum input voltage VINB MUTE pin voltage Unit 14 V 0.8 W Mounted on a standard board. * 2 W Each output for H bridge, channel 1 to 4. 1 A 13 V Independent IC 13 V Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C * Standard board size : VMUTE 76.1×114.3×1.6mm3, glass epoxy. Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage Symbol VCC Conditions Same for VCC-VREG Ratings Unit 5.6 to 13 V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 11707 MS PC B8-5272 No.A0597-1/9 LA6559 Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 8V, VREF = 1.65V, unless especially specified. Parameter Symbol Ratings Conditions min typ Unit max ALL Blocks No-load current drain ON ICC-ON BTL-AMP output ON, 30 50 mA 10 20 mA LOADING block OFF *1 No-load current drain OFF ICC-OFF VREF input voltage range VREF-IN Thermal shutdown temperature TSD All outputs OFF *1 1 VCC-1.5 V 200 °C -60 60 mV Input voltage range for input for OP-AMP. 0 VCC-1.5 mA Each voltage between V0+ and V0- when 5.7 *2 150 Voltage difference between outputs for BTL 175 BTL AMP Block (CH1 to CH4) Output offset voltage VOFF AMP, each channel. *3 Input voltage range VIN Output voltage VO 6.5 V RL = 8Ω. *4 Closed-circuit voltage gain VG Input and output gain. *3 Slew rate SR AMP Independent 5.4 6 6.6 0.5 Times V/μs Multiply 2 between outputs. *2 MUTE ON voltage VMUTE-ON Each MUTE *5 MUTE OFF voltage VMUTE-OFF Each MUTE *5 2 V 0.5 V Input AMP Block (CH1 to 4) Input voltage range Output current (SINK) Output current (SOURCE) VIN-OP 0 SINK-OP 2 SOURCE-OP Output offset voltage *6 300 VCC-1.5 μA 500 -10 VOFF-OP V mA 10 mV Loading Block (CH5, H bridge) Output voltage VO-LOAD Forward, reverse, 5.7 6.5 V RL = 8Ω, VCONT=8V *4 Break output saturation voltage VCE-BREAK Input low level Output voltage at braking *7 VIN-L VIN-H Input high level Output set voltage VCONT 0.3 V 1 V V 2 IO = 200mA (Between outputs), V 2.9 3.15 3.4 3.15 3.3 3.45 VCONT = 3V Power Supply Block (PNP transistor : 2SB632K-use) 3.3V supply voltage REG-IN SINK current VOUT REG-IN-SINK IO = 200mA Base current of external PNP *8 10 V mA Line regulation ΔVOLN 6V ≤ VCC ≤ 12V 20 150 mV Load regulation ΔVOLD 5mA ≤ IO ≤ 200mA 50 200 mV Note *1 : Current dissipation that is a sum of VCC1 and VCC2 and S-VCC at no load. *2 : Design guarantee value *3 : Input AMP is a BUFFER AMP. *4 : Voltage difference between both ends of load (8Ω). Output saturated. *5 : Output ON with MUTE : [H] and OFF with MUTE : [L] (HI impedance). *6 : The source of input OP-AMP is a constant current. As the 11kΩ resistance to the next stage is a load, pay due attention when setting the input OP-AMP gain. *7 : Short (GND) brake used. SINK side output ON. *8 : 3.3VREG incorporates a drooping protection circuit and operated when the base current is 10mA (TYP). No.A0597-2/9 LA6559 Package Dimensions unit : mm (typ) 3251 17.8 (6.2) 19 1 18 0.3 0.25 2.45max (2.25) 2.0 0.1 0.8 2.7 SANYO : HSOP36R(375mil) Pd max – Ta 3 Allowable power dissipation, Pd max – W (0.5) 0.65 (4.9) 7.9 10.5 36 Designated board : 76.1×114.3×1.6mm3 glass epoxy 2.5 2 Mounted on a board 1.5 1.04 1 0.5 0 – 40 – 30 – 20 0 20 40 60 80 85 100 Ambient temperature, Ta – °C No.A0597-3/9 LA6559 Block Diagram Thermal shutdown REV 1 S-VCC 2 Signal system VCC Signal system GND VLO- 4 VLO+ 5 VO4+ 6 VO4- 7 VO3+ 8 VO3- 9 FR FR Level shift 3 FWD 35 S-GND CH2 to CH4 Output MUTE 34 MUTE2 Output ON/OFF MUTE 33 MUTE1 32 VIN4 31 VIN4- 30 VIN4+ 29 VREF-IN 28 VCONT(LOADING) 33kΩ 11kΩ Level shift VCC2 Input (Forward/Reversed/ Break/OFF) Output control Power supply (LOADING) 36 Power system GND Power system GND FR FR Level shift PNP Tr Collector VO2+ 10 VO2- 11 27 REG-OUT 26 REG-IN 25 VIN3+ 24 VIN3- 23 VIN3 22 GND-VREG 21 VCC-VREG 20 VIN2+ 19 VIN2- 3.3VREG (External PNP) PNP Tr Base Level shift VO1+ 12 VO1- 13 VCC1 14 VIN1+ 17 VIN2 18 11kΩ Power supply (CH1 to CH4) 3.3VREG GND VIN1 15 VIN1- 16 33kΩ 33kΩ 3.3VREG Power supply 11kΩ 33kΩ 11kΩ No.A0597-4/9 LA6559 Pin Functions Pin No. Symbol 1 REV Pin descriptions 2 S-VCC 3 VCC2 Power supply for loading block 4 VLO- Loading output (-) 5 VLO+ Loading output (+) 6 VO4+ Output pin (+) for channel 4 7 VO4- Output pin (-) for channel 4 8 VO3+ Output pin (+) for channel 3 Output pin (-) for channel 3 5CH (VLO) Output change pin (REV), logic input for loading block. Signal system power supply (BTL-AMP : CH1 to 4) 9 VO3- 10 VO2+ Output pin (+) for channel 2 11 VO2- Output pin (-) for channel 2 12 VO1+ Output pin (+) for channel 1 13 VO1- Output pin (-) for channel 1 14 VCC1 CH1 to CH4 (BTL-AMP) output stage power supply 15 VIN1 Input pin for channel 1 16 VIN1- OP-AMP input AMP-A input pin (-) 17 VIN1+ OP-AMP input AMP-A input pin (+) 18 VIN2 Input pin for channel 2, input AMP output 19 VIN2- Input pin (-) for channel 2 20 VIN2+ 21 VCC-VREG 3.3VREG power supply 22 GND-VREG 3.3VREG GND 23 VIN3 Input pin for channel 3, input AMP output 24 VIN3- Input pin (-) for channel 3 25 VIN3+ Input pin (+) for channel 3 26 REG-IN 27 REG-OUT 28 VCONT (LOADING) 29 VREF-IN 30 VIN4+ Input pin (+) for channel 4 31 VIN4- Input pin (-) for channel 4 32 VIN4 Input pin for channel 4, input AMP output 33 MUTE1 Output ON/OFF, channel 1 (BTL AMP) 34 MUTE2 Output ON/OFF, channel 2 to 4 (BTL AMP) 35 S-GND Signal system GND 36 FWD Input pin (+) for channel 2 PNP transistor base connected 3.3V power output to which the PNP transistor collector connected. Output voltage set pin for loading block Reference voltage applied pin Output change pin (FWD) for loading output (VLO+ -), logic input for loading block. Note 1 : Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with S-GND. Note 2 : Short-circuit each of VCC1, VCC2, VCC-VREG, and S-VCC power pins externally. No.A0597-5/9 LA6559 Pin Description Pin No. 17 16 15 20 19 18 25 24 23 30 Symbol VIN1+ VIN1- Pin function Input Description Input pin (CH1 to 4) (CH1 to 4) VIN*- VCC VIN1 VIN2+ VIN2VIN2 VIN* VIN*+ VIN3+ VIN3VIN3 VIN4+ S-GND 32 VIN4VIN4 36 FWD Input Logic input pin. 1 REV (LOADING) By combining H and L 31 Equivalent circuit of this pin, any one of four modes (forward/ reversed/brake/idling) FWD can be selected. 12 13 10 11 8 9 6 VO1+ VO1- Output Output for channel (CH1 to 4) 1 to 4. VCC1 VO2+ VO2VO3+ VO3- 7 VO4+ VO4- 33 MUTE1 34 MUTE2 VO* RF MUTE BTL AMP output. Output ON/OFF for S-VCC CH1 to CH4. MUTE : H Output OFF MUTE : L Output OFF MUTE 100kΩ 100kΩ S-GND 5 VLO- Output Output voltage set pin 4 VLO+ (LOADING) for loading block 28 VCONT VO5+ VO5- VCONT No.A0597-6/9 LA6559 Truth Table (loading (H bridge) section) FWD L H REV Loading output L OFF *1 H Forward L Reversed H (Short) brake *2 *1 The output has a high impedance. *2 At brake, the SINK side transistor is ON (short brake). VLO+ and VLO- are approximately on the GND level. Relation of MUTE and Power (VCC*) MUTE1 CH1(BTL) CH2(BTL) MUTE2 CH3(BTL) VCC1 CH4(BTL) CH5 (H bridge) VCC2 No.A0597-7/9 LA6559 Sample Application Circuit MUTE1 MUTE2 FWD 36 1 REV 2 S-VCC S-GND 35 3 VCC2 MUTE2 34 4 VLO- MUTE1 33 5 VLO+ VIN4 32 6 VO4+ VIN4- 31 7 VO4- VIN4+ 30 8 VO3+ VREF-IN 29 9 VO3- VCONT 28 LOADING SLED LOADING MOTOR M TRACKING COIL FOCUS COIL FR FR SPINDLE MOTOR FR FR 10 VO2+ REG-OUT 27 11 VO2- REG-IN 26 12 VO1+ VIN3+ 25 13 VO1- VIN3- 24 14 VCC1 VIN3 23 3.3VREG M VCC SLED MOTOR M VCC 15 VIN1 GND-VREG 22 16 VIN1- VCC-VREG 21 17 VIN1+ VIN2+ 20 18 VIN2 VIN2- 19 TRACKING FOCUS VCONT SPINDLE VREF Note : Add CR between outputs or to a circuit to GND when oscillation occurs in the output (Example : R = 2.2Ω, C = 0.1μF). Apply 4.5V or more to the external PNPTr emitter pin. No.A0597-8/9 LA6559 Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. PS No.A0597-9/9