Ordering number : ENN7740 LA6568 Monolithic Linear IC Six-Channel Driver for Optical Disc Drives Overview The LA6568 is a six-channel driver for optical disc drives that includes built-in 3.3 V and 5 V regulators. Functions • Six power amplifier channels • IOmax: 700 mA • Built-in level shifter circuits (for the BTL amplifiers) • Muting circuit (output on/off control) for one channel • Built-in 3.3 V power supply (IOmax = 300 mA) • Built-in 5 V power supply (IOmax = 5 mA) • Thermal protection circuit (thermal shutdown circuit) Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max 14 V Maximum output current IO max 0.7 A Maximum input voltage VINB max Mute pin voltage VMUTE Allowable power dissipation Pd max Each channel for Ch.1 to Ch.6 13 V 13 V Mounted on a board ∗1 2.00 Independent IC 1.20 W Operating temperature Topr −30 to +85 °C Storage temperature Tstg −55 to +150 °C Note ∗1: Mounted on a board (76.1 × 114.3 × 1.66 mm) Material: glass epoxy Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage Symbol VCC Conditions Ratings 6 to 13 Unit V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206 / 81004TN(OT) No.7740-1/8 LA6568 Electrical Characteristics (Unless specified otherwise, the conditions are Ta = 25°C, S–VCC = P–VCC = 8 V, VREF = 1.65 V) Parameter Symbol Conditions Ratings min typ Unit max [Overall] No load current drain - outputs on ICC-ON All outputs on ∗1 30 50 mA No load current drain - outputs off ICC-OFF All outputs off ∗1 10 20 mA VREF input voltage range VREF-IN 0.5 VCC-1.5 V [BTL Amplifier Block] Output offset voltage Input voltage range Output voltage VOFF VIN VO Closed circuit voltage gain 1 VG1 Closed circuit voltage gain 2 VG2 Slew rate The voltage difference between the output amplifier outputs, for each channel SR The voltage between the VO+ and VO− outputs −50 +50 mV 0 VCC V 4 4.5 The gain between input and output for channels 1, 4, and 5 1.6 2 2.4 Multiplier The gain between input and output for channel 2. Input resistance: 11 kΩ 3.5 4 4.5 Multiplier when RL = 8 Ω ∗2 Twice the value between each output pair ∗3 Muting on voltage VMUTE-ON For each of the muting functions ∗4 Muting off voltage VMUTE-OFF For each of the muting functions ∗4 V 1 V/µs 0.5 2 V V [Loading Block] Voltage between outputs: F VOF VIN+ = 2 V, VIN−=0 V 2.5 2.9 3.3 Voltage between outputs: R VOR VIN+ = 0 V, VIN− = 2 V −3.3 −2.9 −2.5 4.5 5.0 VIN+ = 5 V, VIN− = 0 Output voltage range: F VOMF Output voltage range: R VOMR VIN+ = 0 V, VIN− = 5 V VOFF Potential difference between the outputs when braking is applied Output offset voltage Input current I-IN −5.0 −50 When VIN = 3.3 V V V V −4.5 V +50 mV 500 µA [3.3 V Regulator Block] IO = 100 mA 3.15 3.45 V When IO = 100 mA, VCC = 6 to 12 V −100 +100 mV ∆V-LOAD1 When IO = 0 to 200 mA −100 +100 mV VO-REG2 ∆V-LIN1 When IO = 3 mA 4.75 Line regulation When IO = 3 mA, VCC = 6 to 12 V 100 mV Load regulation ∆V-LOAD When IO = 1 to 3 mA 100 mV Output voltage VO-REG1 Line regulation ∆V-LIN1 Load regulation 3.3 [5 V Regulator Block] Output voltage 5 5.25 V [0-RESET Block] (Operating for VREF) High-level reset output voltage VORH With a 10 kΩ resistor between VCC and RESET Low-level reset output voltage VORL With a 10 kΩ resistor between VCC and RESET 0-RESET threshold voltage 0-RESET hysteresis 6.5 V 0.5 V VRT 0.5 0.7 0.9 V VHYS 50 100 200 mV Note ∗1: The combined current drain for P-VCC and S-VCC with no load ∗2: The voltage difference across the load (8Ω) terminals. With the outputs in the saturated state. ∗3: Design target value. Parameters are not tested. ∗4: When IN-MUTE is high: output on, when IN-MUTE is low: output off (high-impedance state) No.7740-2/8 LA6568 Package Dimensions unit: mm 3196A SANYO : DIP30S-D (400mil) Pin Functions Pin No. Symbol 20 VIN1 19 VIN2 12 VIN4 13 VIN5 Pin name Input Pin description Inputs Equivalent circuit VIN Vref VO1+ 25 VO1− 28 VO2+ 27 VO2− 6 VO4+ 5 VO4− 4 VO5+ 3 VO5− 2 VO3+ 1 VO3− 30 VO6+ 29 VO6− 10 IN-MUTE Output Outputs OUT Mute Controls the on/off state of the outputs. VCC IN-MUTE high: outputs on IN-MUTE low: outputs off IN-MUTE S-GND 100kΩ 100kΩ 26 Continued on next page. No.7740-3/8 LA6568 Continued from preceding page. Symbol 11 O-RESET Reset Pin name Open-collector output Pin description 15 VIN3− Input Inputs 14 VIN3+ 17 VIN6− (Loading block) 18 VIN6+ Equivalent circuit 100kΩ Pin No. 50kΩ 5VREG 5VREG 5 V regulator output 22 3.3VREG 3.3VREG 3.3 V regulator output 5.46kΩ 8.87kΩ 13kΩ 39kΩ 16 No.7740-4/8 LA6568 Block Diagram 1 Level shift VO3- ×2 ×2 Level shift ×2 30 VO6+ ×2 29 VO6- VO5- 3 28 VO2+ VO5+ 4 27 VO2- VO4- 5 26 VO1+ VO4+ 6 25 VO1- 24 P-GND2 23 P-VCC (IN) 22 3.3VREG(OUT) 21 S-VCC (IN) 20 VIN1 19 VIN2 18 VIN6+ 17 VIN6- 16 5VREG Level shift Level shift Level shift 2 Level shift VO3+ Power system ground P-GND1 7 Power system ground + - S-GND 8 Signal system ground VREF Power system VCC Reference voltage 9 3.3 VREG Signal system VCC IN- MUTE 10 The reset output goes low when VREF is under 0.7 V. MUTE RESET O- RESET 11 22 kΩ 22 kΩ + 22 kΩ 22 kΩ 200 Ω VIN4 12 22 kΩ + + 22 kΩ ×3/8 22 kΩ VIN5 13 VIN3+ 14 + ×3/8 ×3/8 VIN3- 15 ×3/8 Overheat protection circuit (Thermal shutdown) 5VREG No.7740-5/8 LA6568 Sample Application Circuit 1 LOADING MOTOR V O 3- V O 6+ 30 M 2 V O 3+ V O 6- 29 3 V O 5- V O 2+ 28 FOCUS COIL 4 V O 5+ V O 2- 27 5 V O 4- V O 1+ 26 TRACKING COIL M CHANGER MOTOR M SPINDLE MOTOR M SLED MOTOR V O 1- 25 P-GND2 24 P-V CC 23 V CC 3.3VREG 22 3.3 V S-V CC 21 O-RESET V IN 1 20 SLED MOTOR 12 V IN 4 V IN 2 19 SPINDLE MOTOR 13 V IN 5 V IN 6+ 18 14 V IN 3+ V IN 6- 17 V IN 3- 5VREG 6 V O 4+ 7 P-GND1 8 S-GND 9 VREF 10 IN-MUTE 11 V CC MUTE RESET CHANGER REV FW D LOADING FW D FOCUS COIL TRACKING COIL REV 15 16 VREF No.7740-6/8 LA6568 Relationship Between Muting and the P-VCC Power Supply CH1(BTL AMP) CH2(BTL AMP) MUTE P-VCC CH6(LOADING) CH4(BTL AMP) CH5(BTL AMP) CH3(LOADING) Note: • Connect both S-VCC and P-VCC to the power supply system externally. • Connect both S-GND and P-GND to the ground system externally. Muting Functions vs. Outputs and 3.3 V Regulator Operating States CH1, 2, 4, 5 CH3, 6 3.3VREG (BTL-AMP) (LOADING) 5VREG When IN-MUTE is low OFF − OFF When the thermal shutdown circuit has operated OFF OFF OFF When VREF has fallen below 0.7 V OFF − − Note: • A dash (−) indicates no operation for functions to which muting, thermal shutdown, or VREF fall protection apply. • The IN-MUTE pin applies to the BTL amplifiers (channels 1, 2, 4, and 5) and the 3.3 V and 5 V regulators. • The VREF fall protection function only applies to the BTL amplifiers. The muting function applies to the BTL amplifiers (channels 1, 2, 4, and 5) and the 3.3 V and 5 V regulators. BTL-AMP (CH1, 2, 4, 5) IN-MUTE state 3.3VREG 5 VREG H ON L OFF The VREF fall protection function only applies to the BTL amplifiers. BTL-AMP (CH1, 2, 4, 5) VREF state VREF > 0.7 (V) ON VREF < 0.7 (V) OFF Loading Block VIN∗+ (FWD) L H VIN∗− (REV) Loading output L Brake H Reverse (VO = −1.5 × REV) ∗1 L Forward (VO = 1.5 × FWD) ∗1 H (VO = 1.5 × (FWD − REV)) Note ∗1: FWD: VIN6+, VIN3+, REV: VIN6−, VIN3− Note: • In brake mode, the + and - output voltages both go to VCC/2. • The "L" voltage level is any level less than VF (approximately 0.6 V). • The loading circuit (channels 3 and 6) gain is 3.5 dB (typical). No.7740-7/8 LA6568 Reset Function IN-MUTE L H VREF O-RESET VREF < 0.7 V L VREF > 0.7 V L VREF < 0.7 V L VREF > 0.7 V H Note: The O-RESET output is an open-collector output (NPN). The O-RESET low state is when the NPN transistor output is on, and the O-RESET high state is when the NPN transistor output is off. Relationship Between the BTL Amplifier Inputs and Outputs VIN1 VO1+ VIN2 VO2+ VIN4 VO4+ VIN5 VO5+ VO1VO2VO4VO5- Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 2004. Specifications and information herein are subject to change without notice. No.7740-8/8