MICROCHIP MCP1824S

MCP1824/MCP1824S
300 mA, Low Voltage, Low Quiescent Current LDO Regulator
Features
Description
• 300 mA Output Current Capability
• Input Operating Voltage Range: 2.1V to 6.0V
• Adjustable Output Voltage Range: 0.8V to 5.0V
(MCP1824 only)
• Standard Fixed Output Voltages:
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V
• Other Fixed Output Voltage Options Available
Upon Request
• Low Dropout Voltage: 200 mV Typical at 300 mA
• Typical Output Voltage Tolerance: 0.4%
• Stable with 1.0 µF Ceramic Output Capacitor
• Fast Response to Load Transients
• Low Supply Current: 120 µA (typical)
• Low Shutdown Supply Current: 0.1 µA (typical)
(MCP1824 only)
• Fixed Delay on Power Good Output
(MCP1824 only)
• Short Circuit Current Limiting and
Overtemperature Protection
• 5-Lead Plastic SOT-223, SOT-23 Package
Options (MCP1824)
• 3-Lead Plastic SOT-223 Package Option
(MCP1824S)
The MCP1824/MCP1824S is a 300 mA Low Dropout
(LDO) linear regulator that provides high current and
low output voltages. The MCP1824 comes in a fixed or
adjustable output voltage version, with an output
voltage range of 0.8V to 5.0V. The 300 mA output
current capability, combined with the low output voltage
capability, make the MCP1824 a good choice for new
sub-1.8V output voltage LDO applications that have
high current demands. The MCP1824S is a 3-pin fixed
voltage version.
Applications
•
•
•
•
•
•
High-Speed Driver Chipset Power
Networking Backplane Cards
Notebook Computers
Network Interface Cards
Palmtop Computers
2.5V to 1.XV Regulators
© 2007 Microchip Technology Inc.
The MCP1824/MCP1824S is stable using ceramic
output capacitors that inherently provide lower output
noise and reduce the size and cost of the entire
regulator solution. Only 1 µF of output capacitance is
needed to stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1824/MCP1824S is typically
less than 120 µA over the entire input voltage range,
making it attractive for portable computing applications
that demand high output current. The MCP1824
versions have a Shutdown (SHDN) pin. When shut
down, the quiescent current is reduced to less than
0.1 µA.
On the MCP1824 fixed output versions, the scaleddown output voltage is internally monitored and a
power good (PWRGD) output is provided when the
output is within 92% of regulation (typical). The
PWRGD delay is internally fixed at 110 µs (typical).
The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
fault conditions.
DS22070A-page 1
MCP1824/MCP1824S
Package Types
MCP1824
MCP1824S
Fixed/Adjustable
SOT-23-5
SOT-223-5
SOT-223-3
4
6
5
4
1
1
2
3
4
2
1
5
SOT-223
Pin
Fixed
3
SOT-23
Adjustable
Fixed
Pin
Adjustable
1
SHDN
SHDN
VIN
VIN
2
VIN
VIN
GND (TAB)
GND (TAB)
3
GND (TAB)
GND (TAB)
SHDN
SHDN
4
VOUT
VOUT
PWRGD
ADJ
5
PWRGD
ADJ
VOUT
VOUT
6
GND (TAB)
GND (TAB)
—
—
DS22070A-page 2
2
3
SOT-223
1
VIN
2
GND (TAB)
3
VOUT
4
GND (TAB)
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
Typical Applications
MCP1824 Fixed Output Voltage
PWRGD
R1
100 kΩ
On
SHDN
Off
VIN = 2.3V to 2.8V
VIN
1
VOUT = 1.8V @ 300 mA
VOUT
GND
C1
4.7 µF
C2
1 µF
MCP1824 Adjustable Output Voltage
VADJ
R1
40 kΩ
On
R2
20 kΩ
SHDN
Off
VIN = 2.1V to 2.8V
VIN
1
VOUT
C1
4.7 µF
VOUT = 1.2V @ 300 mA
C2
1 µF
GND
© 2007 Microchip Technology Inc.
DS22070A-page 3
MCP1824/MCP1824S
Functional Block Diagram - Adjustable Output
(MCP1824)
PMOS
VIN
VOUT
Undervoltage
Lock Out
(UVLO)
ISNS
Cf
Rf
SHDN
ADJ/SENSE
Overtemperature
Sensing
+
Driver w/limit
and SHDN
EA
–
SHDN
VREF
V IN
SHDN
Reference
Soft-Start
Comp
TDELAY
GND
92% of VREF
DS22070A-page 4
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
Functional Block Diagram - Fixed Output (MCP1824S)
PMOS
VIN
VOUT
Undervoltage
Lock Out
(UVLO)
Sense
ISNS
Cf
Rf
SHDN
Overtemperature
Sensing
+
Driver w/limit
and SHDN
EA
–
SHDN
VREF
V IN
SHDN
Reference
Soft-Start
Comp
TDELAY
GND
92% of VREF
© 2007 Microchip Technology Inc.
DS22070A-page 5
MCP1824/MCP1824S
Functional Block Diagram - Fixed Output (MCP1824)
PMOS
VIN
VOUT
Undervoltage
Lock Out
(UVLO)
Sense
ISNS
Cf
Rf
SHDN
Overtemperature
Sensing
+
Driver w/limit
and SHDN
EA
–
SHDN
VREF
V IN
SHDN
Reference
Soft-Start
PWRGD
Comp
GND
TDELAY
92% of VREF
DS22070A-page 6
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Input Voltage, VIN .............................................................6.5V
Maximum Voltage on Any Pin ... (GND – 0.3V) to (VIN + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration ................................ Continuous
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, TJ ........................... +150°C
Operating Junction Temperature, TJ .............-40°C to +125°C
EESD protection on all pins ........... ≥ 4 kV HBM; ≥ 300V MM
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters
Sym
Min
Typ
Max
Units
Conditions
VIN
2.1
—
6.0
V
VOUT
0.8
—
5.0
V
Iq
—
120
220
µA
IL = 0 mA, VOUT = 0.8V to
5.0V
Input Quiescent Current for
SHDN Mode
ISHDN
—
0.1
3
µA
SHDN = GND
Maximum Continuous Output
Current
IOUT
300
—
—
mA
VIN = 2.1V to 6.0V
VR = 0.8V to 5.0V
Line Regulation
ΔVOUT/
(VOUT x ΔVIN)
—
±0.05
±0.17
%/V
(Note 1) ≤ VIN ≤ 6V
Load Regulation
ΔVOUT/VOUT
-1.0
±0.5
1.0
%
Input Operating Voltage
Output Voltage Range
Input Quiescent Current
Output Short Circuit Current
Dropout Voltage
IOUT = 1 mA to 300 mA,
(Note 4)
IOUT_SC
—
720
—
mA
RLOAD < 0.1Ω, Peak Current
VDROPOUT
—
200
320
mV
Note 5, IOUT = 300 mA,
VIN(MIN) = 2.1V
IPULSE
—
500
—
mA
VIN = 2.1V to 6.0V
VR = 0.8V to 5.0V,
Duty Cycle ≤ 60%,
Period < 10 ms
Pulsed Applications
Maximum Pulsed Output
Current
Note 1:
2:
3:
4:
5:
6:
7:
The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2007 Microchip Technology Inc.
DS22070A-page 7
MCP1824/MCP1824S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters
Sym
Min
Typ
Max
Units
IPULSE_DUTY
—
—
60
%
VIN = 2.1V to 6.0V,
VR = 0.8V to 5.0V,
IOUT = 500 mA,
Period < 10 ms
IPULSE_PERIOD
—
—
10
ms
VIN = 2.1V to 6.0V
VR = 0.8V to 5.0V,
IOUT = 500 mA
VOUT_ADJ
0.8
—
5.5
V
Adjust Pin Reference Voltage
VADJ
0.402
0.410
0.418
V
VIN = 2.1V to VIN = 6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current
IADJ
-10
±0.01
+10
nA
VIN = 6.0V, VADJ = 0V to 6V
TCVOUT
—
40
—
ppm/°C
Note 3
V
Note 2
Maximum Pulsed Output Duty
Cycle
Maximum Pulsed Output Period
Conditions
Adjust Pin Characteristics (Adjustable Output Only)
Adjustable Output Voltage
Range
Adjust Temperature Coefficient
Fixed-Output Characteristics (Fixed Output Only)
Voltage Regulation
VOUT
VR - 2.5%
VR ±0.5% VR + 2.5%
Power Good Characteristics
PWRGD Input Voltage Operating Range
VPWRGD_VIN
PWRGD Threshold Voltage
(Referenced to VOUT)
VPWRGD_TH
90
92
94
PWRGD Threshold Hysteresis
VPWRGD_HYS
1.0
2.0
3.0
%VOUT
PWRGD Output Voltage Low
VPWRGD_L
—
0.05
0.4
V
PWRGD Output Current Sink
Capability
IPWRGD
1.2
6.0
—
mA
PWRGD_LK
—
1
—
nA
VPWRGD = VIN = 6.0V
TPG
—
110
—
µs
Rising Edge
RPULLUP = 10 kΩ
1.0
—
6.0
1.2
—
6.0
V
TA = +25°C
TA = -40°C to +125°C
For VIN < 2.1V, ISINK = 100 µA
PWRGD Leakage
PWRGD Time Delay
Note 1:
2:
3:
4:
5:
6:
7:
%VOUT
89
92
Falling Edge
VOUT < 2.5V Fixed,
VOUT = Adj.
95
VOUT >= 2.5V Fixed
IPWRGD SINK = 1.2 mA,
ADJ = 0V
VPWRGD = 0.200V
The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
DS22070A-page 8
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters
Sym
Min
Typ
Max
Units
TVDET-PWRGD
—
200
—
µs
Logic High Input
VSHDN-HIGH
45
—
—
%VIN
VIN = 2.1V to 6.0V
Logic Low Input
VSHDN-LOW
—
—
15
%VIN
VIN = 2.1V to 6.0V
SHDNILK
-0.1
±0.001
+0.1
µA
VIN = 6V, SHDN =VIN,
SHDN = GND
TOR
—
100
—
µs
SHDN = GND to VIN,
VOUT = GND to 95% VR
eN
—
2.0
—
µV/√Hz
Power Supply Ripple Rejection
Ratio
PSRR
—
55
—
dB
f = 100 Hz,
IOUT = 10 mA,
VINAC = 200 mV pk-pk,
CIN = 0 µF
Thermal Shutdown Temperature
TSD
—
150
—
°C
IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
ΔTSD
—
10
—
°C
IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Detect Threshold to PWRGD
Active Time Delay
Conditions
VOUT = VPWRGD_TH + 50 mV
to VPWRGD_TH - 50 mV
Shutdown Input
SHDN Input Leakage Current
AC Performance
Output Delay From SHDN
Output Noise
Thermal Shutdown Hysteresis
Note 1:
2:
3:
4:
5:
6:
7:
IOUT = 200 mA, f = 1 kHz,
COUT = 10 µF (X7R Ceramic),
VOUT = 2.5V
The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2007 Microchip Technology Inc.
DS22070A-page 9
MCP1824/MCP1824S
TEMPERATURE SPECIFICATIONS
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Steady State
Maximum Junction Temperature
TJ
—
—
+150
°C
Transient
Storage Temperature Range
TA
-65
—
+150
°C
°C/W
EIA/JEDEC JESD51-751-7
4 Layer Board
°C/W
EIA/JEDEC JESD51-751-7
4 Layer Board
°C/W
EIA/JEDEC JESD51-751-7
4 Layer Board
Thermal Package Resistances
Thermal Resistance, 3LD SOT-223
Thermal Resistance, 5LD SOT-23
Thermal Resistance, 5LD SOT-223
DS22070A-page 10
θJA
—
62
—
θJC
—
15
—
θJA
—
256
—
θJC
—
81
—
θJA
—
62
—
θJC
—
15
—
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
VOUT = 1.2V Adj
IOUT = 0 mA
μ 130
Line Regulation (%/V)
Quiescent Current ( A)
140
130°C
120
90°C
110
25°C
0°C
100
-45°C
90
2
3
4
5
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
6
IOUT = 1 mA
IOUT = 50 mA
IOUT=100 mA
IOUT=200 mA
IOUT=300 mA
-45
-20
5
Input Voltage (V)
0.10
VIN=5.0V
150
VIN=3.3V
140
130
120
110
130
0.05
VOUT = 0.8V
0.00
VOUT = 1.8V
-0.05
-0.10
VOUT = 5.0V
-0.15
-0.20
0
50
100
150
200
250
-45
300
-20
5
FIGURE 2-2:
Ground Current vs. Load
Current (Adjustable Version).
Adjust Pin Voltage (V)
150
VIN=6.0V
VIN=5.0V
120
110
VIN=4.0V
100
VIN=2.1V
80
105
130
0.413
VOUT = 0.8V Adj
IOUT = 0 mA
140
55
FIGURE 2-5:
Load Regulation vs.
Temperature (Adjustable Version).
170
160
30
Temperature (°C)
Load Current (mA)
Quiescent Current ( A)
105
VIN=2.5V
100
130
80
IOUT = 1.0 mA to 300 mA
VOUT = 3.3V
Load Regulation (%)
Ground Current ( A)
VOUT = 1.2V Adj
μ 160
55
FIGURE 2-4:
Line Regulation vs.
Temperature (Adjustable Version).
180
μ
30
Temperature (°C)
FIGURE 2-1:
Quiescent Current vs. Input
Voltage (Adjustable Version).
170
VOUT = 1.2V adj
VIN = 2.1V to 6.0V
0.412
0.411
0.410
VIN = 4.0V
0.409
0.408
VIN = 2.1V
VIN=3.0V
90
VOUT = 1.2V
IOUT = 1.0 mA
VIN = 6.0V
0.407
-45
-20
5
30
55
80
105
Temperature (°C)
FIGURE 2-3:
Quiescent Current vs.
Junction Temperature (Adjustable Version).
© 2007 Microchip Technology Inc.
130
-45
-20
5
30
55
80
105
130
Temperature (°C)
FIGURE 2-6:
Adjust Pin Voltage vs.
Temperature (Adjustable Version).
DS22070A-page 11
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
160
0.25
Quiescent Current ( A)
Dropout Voltage (V)
0.30
μ
0.20
VOUT = 5.0V Adj
0.15
0.10
VOUT = 2.5V Adj
0.05
0.00
VOUT = 0.8V
IOUT = 0 mA
150
140
+130°C
+90°C
130
+25°C
120
0°C
110
-45°C
100
90
0
50
100
150
200
250
300
2
3
4
FIGURE 2-10:
Voltage.
μ
VOUT = 5.0V Adj
VOUT = 3.3V Adj
VOUT = 2.5V Adj
VOUT = 2.5V
IOUT = 0 mA
140
130
+130°C
+90°C
120
+25°C
110
+0°C
-45°C
100
90
-45
-20
5
30
55
80
105
130
3.0
3.5
Temperature (°C)
4.0
FIGURE 2-11:
Voltage.
Ground Current ( A)
VOUT = 0.8V Fixed
IOUT = 0 mA
μ
VIN = 5.0V
90
80
70
VIN = 2.1V
5.0
5.5
6.0
Quiescent Current vs. Input
250
110
100
4.5
Input Voltage (V)
FIGURE 2-8:
Dropout Voltage vs.
Temperature (Adjustable Version).
Power Good Time Delay (µS)
6
Quiescent Current vs. Input
150
IOUT = 300 mA
Quiescent Current ( A)
Dropout Voltage (V)
FIGURE 2-7:
Dropout Voltage vs. Load
Current (Adjustable Version).
0.24
0.23
0.22
0.21
0.20
0.19
0.18
0.17
0.16
0.15
0.14
5
Input Voltage (V)
Load Current (mA)
VIN = 3.3V
60
VIN = 2.1V for VR=0.8V
VIN = 3.5V for VR=3.0V
200
150
VOUT=3.0V
100
VOUT=0.8V
50
0
50
-45
-20
5
30
55
80
105
130
0
50
Temperature (°C)
FIGURE 2-9:
Power Good (PWRGD)
Time Delay vs. Temperature.
DS22070A-page 12
100
150
200
250
300
Load Current (mA)
FIGURE 2-12:
Current.
Ground Current vs. Load
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
μ
0.042
IOUT = 0 mA
125
Line Regulation (%/V)
Quiescent Current ( A)
130
120
115
VOUT = 2.5V
110
105
VOUTc= 0.8V
100
95
90
0.038
VR = 2.5V
VIN = 3.0V to 6.0V
IOUT = 1 mA
0.034
0.030
IOUT = 50 mA
IOUT = 100 mA
0.026
0.022
0.018
0.014
IOUT = 300 mA
IOUT = 200 mA
0.010
-45
-20
5
30
55
80
105
130
-45
-20
5
Temperature (°C)
μ
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
FIGURE 2-16:
Temperature.
Quiescent Current vs.
VR = 0.8V
VIN = 2.3V
VIN = 6.0V
-45
-20
Load Regulation (%)
Ishdn ( A)
FIGURE 2-13:
Temperature.
VIN = 3.3V
5
30
55
80
105
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
130
VIN = 4.0V
80
105
130
VOUT = 0.8V
IOUT = 1 mA to 300 mA
VIN = 2.1V
VIN = 5.0V
VIN = 6.0V
-45
-20
5
30
55
80
105
130
Temperature (°C)
ISHDN vs. Temperature.
FIGURE 2-17:
Temperature.
Load Regulation vs.
0.10
VOUT = 0.8V
VIN = 2.1V to 6.0V
IOUT = 1 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 200 mA
IOUT = 300 mA
IOUT = 1 mA to 300 mA
VOUT = 0.8V
0.05
Load Regulation (%)
Line Regulation (%/V)
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
55
Line Regulation vs.
Temperature (°C)
FIGURE 2-14:
30
Temperature (°C)
0.00
-0.05
VOUT = 2.5V
-0.10
-0.15
VOUT = 5.0V
-0.20
-0.25
-0.30
-45
-20
5
30
55
80
105
130
-45
-20
Temperature (°C)
FIGURE 2-15:
Temperature.
Line Regulation vs.
© 2007 Microchip Technology Inc.
5
30
55
80
105
130
Temperature (°C)
FIGURE 2-18:
Temperature.
Load Regulation vs.
DS22070A-page 13
MCP1824/MCP1824S
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
10.000
VR=3.0V, VIN=3.8V
Noise (mV/√Hz)
Dropout Voltage (V)
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
VOUT = 5.0V
VOUT = 2.5V
0
50
100
150
200
250
1.000
IOUT=200 mA
VR=0.8V, VIN=2.1V
0.100
0.010
0.01
300
0.1
Load Current (mA)
FIGURE 2-19:
Current.
Dropout Voltage vs. Load
100
1000
0.0
IOUT = 300 mA
-10.0
0.22
-20.0
0.20
VOUT = 5.0V
PSRR (dB)
Dropout Voltage (V)
1
10
Frequency (kHz)
FIGURE 2-22:
Output Noise Voltage
Density vs. Frequency.
0.24
0.18
0.16
VOUT = 2.5V
0.14
-30.0
-40.0
VR=1.2V Adj
VIN=2.5V
VINAC = 200 mV p-p
CIN=0 μF
IOUT=10 mA
-50.0
-60.0
-70.0
0.12
-45
-20
5
30
55
80
105
-80.0
0.01
130
0.1
Temperature (°C)
FIGURE 2-20:
Temperature.
Dropout Voltage vs.
1
10
Frequency (kHz)
100
1000
FIGURE 2-23:
Power Supply Ripple
Rejection (PSRR) vs. Frequency (Adj.).
0.0
600.00
-10.0
VOUT = 0.8V
500.00
-20.0
400.00
-30.0
PSRR (dB)
Short Circuit Current (mA)
COUT=10 μF cer
CIN=4.7 μF cer
300.00
200.00
-40.0
VR=3.0V (Fixed)
VIN=3.5V
VINAC=200 mV p-p
CIN=0 μF
IOUT=10 mA
-50.0
-60.0
-70.0
100.00
-80.0
0.00
0
1
2
3
4
5
6
Input Voltage (V)
FIGURE 2-21:
Input Voltage.
DS22070A-page 14
Short Circuit Current vs.
-90.0
0.01
0.1
1
10
Frequency (kHz)
100
1000
FIGURE 2-24:
Power Supply Ripple
Rejection (PSRR) vs. Frequency.
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
FIGURE 2-25:
Startup from VIN
(Adjustable Version).
FIGURE 2-28:
Timing.
Power Good (PWRGD)
FIGURE 2-26:
Startup from Shutdown
(Adjustable Version).
FIGURE 2-29:
Dynamic Line Response.
FIGURE 2-27:
Timing.
FIGURE 2-30:
Dynamic Line Response.
Power Good (PWRGD)
© 2007 Microchip Technology Inc.
DS22070A-page 15
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
PWRGD Voltage (mV)
900
800
700
600
VR = 0.8V
500
VR = 3.0V
400
300
200
100
VR = 5.0V
0
0
2
4
6
8
10 12 14 16 18 20
PWRGD Sink Current (mA)
FIGURE 2-31:
Dynamic Load Response.
FIGURE 2-33:
Voltage Vs Load.
Power Good Pulldown
FIGURE 2-32:
Dynamic Load Response.
FIGURE 2-34:
Startup Current.
DS22070A-page 16
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
SOT-223
SOT-23
Name
Description
3
SHDN
Shutdown Control Input (active-low)
1
1
VIN
3
2
2
GND
Ground
4
4
5
5
VOUT
Regulated Output Voltage
—
5
—
4
—
PWRGD
—
—
5
—
4
ADJ
Output Voltage Adjust/Sense Input
—
—
EP
Exposed Pad of the Package (ground potential)
3-Pin
Fixed
5-Pin
Fixed
5-Pin
Adj
5-Pin
Fixed
5-Pin
Adj
—
1
1
3
1
2
2
2
3
3
Exposed Exposed Exposed
Pad
Pad
Pad
3.1
Shutdown Control Input (SHDN)
Input Voltage Supply
Power Good Output
3.4
Regulated Output Voltage (VOUT)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1824/MCP1824S is
stable with ceramic, tantalum, and aluminumelectrolytic capacitors. See Section 4.3 “Output
Capacitor” for output capacitor selection guidance.
3.2
For fixed applications, the PWRGD output is an opendrain output used to indicate when the LDO output
voltage is within 92% (typically) of its nominal
regulation value. The PWRGD threshold has a typical
hysteresis value of 2%. The PWRGD output is delayed
by 110 µs (typical) from the time the LDO output is
within 92% + 3% (maximum hysteresis) of the
regulated output value on power-up. This delay time is
internally fixed.
Input Voltage Supply (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications. The
type of capacitor used can be ceramic, tantalum, or
aluminum electrolytic. The low ESR characteristics of
the ceramic capacitor will yield better noise and PSRR
performance at high frequency.
3.3
Ground (GND)
For the optimal Noise and Power Supply Rejection
Ratio (PSRR) performance, the GND pin of the LDO
should be tied to an electrically quiet circuit ground.
This will help the LDO power supply rejection ratio and
noise performance. The ground pin of the LDO only
conducts the ground current of the LDO, so a heavy
trace is not required.
For applications that have
switching or noisy inputs, tie the GND pin to the return
of the output capacitor. Ground planes help lower
inductance and voltage spikes caused by fast transient
load currents and are recommended for applications
that are subjected to fast load transients.
© 2007 Microchip Technology Inc.
3.5
3.6
Power Good Output (PWRGD)
Output Voltage Adjust Input (ADJ)
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the users the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.7
Exposed Pad (EP)
The SOT-223 package has an exposed metal pad on
the bottom of the package. The exposed metal pad
gives the device better thermal characteristics by
providing a good thermal path to either the PCB or
heatsink to remove heat from the device. The exposed
pad of the package is at ground potential.
DS22070A-page 17
MCP1824/MCP1824S
4.0
DEVICE OVERVIEW
The MCP1824/MCP1824S is a 300 mA output current,
Low Dropout (LDO) voltage regulator. The low dropout
voltage of 200 mV typical at 300 mA of current makes
it ideal for battery-powered applications. The input
voltage range is 2.1V to 6.0V. Unlike other high output
current LDOs, the MCP1824/MCP1824S only draws a
maximum of 220 µA of quiescent current. The
MCP1824 adds a shutdown control input pin and a
power good output pin. The two output voltage options
are fixed or adjustable. The adjustable option is
available on the MCP1824 devices. The adjustable output voltage is set using two external resistors.
4.1
LDO Output Voltage
ADJUST INPUT
The adjustable version of the MCP1824 uses the ADJ
pin to get the output voltage feedback for output voltage
regulation. This allows the user to set the output voltage of the device with two external resistors. The nominal voltage for ADJ is 0.41V.
Figure 4-1 shows the adjustable version of the
MCP1824. Resistors R1 and R2 form the resistor
divider network necessary to set the output voltage.
With this configuration, Equation 4-1 represents the
equation for setting VOUT.
EQUATION 4-1:
CALCULATING VOUT
R1 + R 2
V OUT = V ADJ ⎛⎝ ------------------⎞⎠
R2
Where:
VOUT
=
LDO Output Voltage
VADJ
=
ADJ Pin Voltage
(typically 0.41V)
EQUATION 4-2:
CALCULATING ADJ PIN
RESISTOR VALUES
V OUT
R 1 = R 2 ⎛⎝ ------------- – 1⎞⎠
V ADJ
Where:
4.2
The MCP1824 LDO is available with either a fixed
output voltage or an adjustable output voltage. The
output voltage range is 0.8V to 5.0V for either version.
The MCP1824S LDO is available as a fixed voltage
device.
4.1.1
The allowable resistance value range for resistor R2 is
from 10 kΩ to 200 kΩ. Solving Equation 4-1 for R1
yields Equation 4-2.
VOUT
=
LDO Output Voltage
VADJ
=
ADJ Pin Voltage
(typically 0.41V)
Output Current and Current
Limiting
The MCP1824/MCP1824S LDO is tested and ensured
to supply a minimum of 300 mA of output current. The
MCP1824/MCP1824S has no minimum output load, so
the output load current can go to 0 mA and the LDO will
continue to regulate the output voltage to within
tolerance.
The MCP1824/MCP1824S also incorporates an output
current limit. If the output voltage falls below 0.7V due
to an overload condition (usually represents a shorted
load condition), the output current is limited to 720 mA
(typical). If the overload condition is a soft overload, the
MCP1824/MCP1824S will supply higher load currents
of up to 900 mA. The MCP1824/MCP1824S should not
be operated in this condition continuously as it may
result in failure of the device. However, this does allow
for device usage in applications that have higher
pulsed load currents having an average output current
value of 300 mA or less.
Output overload conditions may also result in an overtemperature shutdown of the device. If the junction
temperature rises above 150°C (typical), the LDO will
shut down the output voltage. See Section 4.8 “Overtemperature Protection” for more information on
overtemperature shutdown.
MCP1824-ADJ
VOUT
On
Off
R1
1 2 3 4 5
SHDN
ADJ
C2
1 µF
VIN
C1
4.7 µF
GND
R2
FIGURE 4-1:
Typical Adjustable Output
Voltage Application Circuit.
DS22070A-page 18
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
4.3
Output Capacitor
The MCP1824/MCP1824S requires a minimum output
capacitance of 1 µF for output voltage stability. Ceramic
capacitors are recommended because of their size,
cost, and environmental robustness qualities.
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capacitor has an ESR of 50 milli-ohms.
Larger LDO output capacitors can be used with the
MCP1824/MCP1824S
to
improve
dynamic
performance and power supply ripple rejection
performance. A maximum of 22 µF is recommended.
Aluminum-electrolytic capacitors are not recommended for low temperature applications of < -25°C.
4.4
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 200 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA minimum (VPWRGD < 0.4V maximum).
Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from, in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5
delay is fixed at 110 µs (typical). After the time delay
period, the PWRGD output will go high, indicating that
the output voltage is stable and within regulation limits.
Power Good Output (PWRGD)
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
Section 1.0 “Electrical Characteristics” for Minimum
and Maximum specifications) of its nominal regulation
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as TPG in the
Electrical Characteristics table). The power good time
© 2007 Microchip Technology Inc.
VPWRGD_TH
VOUT
TPG
VOH
TVDET_PWRGD
PWRGD
VOL
FIGURE 4-2:
VIN
Power Good Timing.
TOR
30 µs
SHDN
70 µs
TPG
VOUT
PWRGD
FIGURE 4-3:
Shutdown.
Power Good Timing from
DS22070A-page 19
MCP1824/MCP1824S
4.6
Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of VIN, with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 100 µs. See Figure 4-4 for a timing diagram of
the SHDN input.
TOR
400 ns (typ)
30 µs
70 µs
VOUT
DS22070A-page 20
Shutdown Input Timing
Dropout Voltage and Undervoltage
Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR + 0.5V differential applied. The MCP1824/
MCP1824S LDO has a very low dropout voltage
specification of 210 mV (typical) at 300 mA of output
current. See Section 1.0 “Electrical Characteristics”
for maximum dropout voltage specifications.
The MCP1824/MCP1824S LDO operates across an
input voltage range of 2.1V to 6.0V and incorporates
input Undervoltage Lockout (UVLO) circuitry that keeps
the LDO output voltage off until the input voltage
reaches a minimum of 2.00V (typical) on the rising
edge of the input voltage. As the input voltage falls, the
LDO output will remain on until the input voltage level
reaches 1.82V (typical).
Since the MCP1824/MCP1824S LDO undervoltage
lockout activates at 1.82V as the input voltage is falling,
the dropout voltage specification does not apply for
output voltages that are less than 1.8V.
For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with input voltages near 2.1V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervoltage lockout.
4.8
SHDN
FIGURE 4-4:
Diagram.
4.7
Overtemperature Protection
The MCP1824/MCP1824S LDO has temperaturesensing circuitry to prevent the junction temperature
from exceeding approximately 150°C. If the LDO
junction temperature does reach 150°C, the LDO
output will be turned off until the junction temperature
cools to approximately 140°C, at which point the LDO
output will automatically resume normal operation. If
the internal power dissipation continues to be
excessive, the device will again shut off. The junction
temperature of the die is a function of power
dissipation, ambient temperature and package thermal
resistance. See Section 5.0 “Application Circuits/
Issues” for more information on LDO power
dissipation and junction temperature.
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
5.0
APPLICATION CIRCUITS/
ISSUES
5.1
Typical Application
In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1824/
MCP1824S as a result of quiescent or ground current.
The power dissipation as a result of the ground current
can be calculated using the following equation:
The MCP1824/MCP1824S is used for applications that
require high LDO output current and a power good
output.
EQUATION 5-2:
P I ( GND ) = VIN ( MAX ) × I VIN
Where:
VOUT = 2.5V @ 300 mA
MCP1824-2.5
R1
10 kΩ
On
Off
1 2 3 4 5
SHDN
C2
10 µF
VIN
3.3V
PI(GND
=
Power dissipation due to the
quiescent current of the LDO
VIN(MAX)
=
Maximum input voltage
IVIN
=
Current flowing in the VIN pin
with no LDO output current
(LDO quiescent current)
C1
4.7 µF
PWRGD
GND
FIGURE 5-1:
5.1.1
Typical Application Circuit.
APPLICATION CONDITIONS
Package Type
=
SOT-223-5
Input Voltage Range
=
3.3V ± 5%
VIN maximum
=
3.465V
VIN minimum
=
3.135V
VDROPOUT (max)
=
0.350V
VOUT (typical)
=
2.5V
IOUT
=
300 mA maximum
PDISS (typical)
=
0.240W
Temperature Rise
=
14.88°C
5.2
Power Calculations
5.2.1
POWER DISSIPATION
The internal power dissipation within the MCP1824/
MCP1824S is a function of input voltage, output
voltage, output current and quiescent current.
Equation 5-1 can be used to calculate the internal
power dissipation for the LDO.
EQUATION 5-1:
P LDO = ( VIN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) )
The total power dissipated within the MCP1824/
MCP1824S is the sum of the power dissipated in the
LDO pass device and the P(IGND) term. Because of the
CMOS construction, the typical IGND for the MCP1824/
MCP1824S is 120 µA. Operating at a maximum VIN of
3.465V results in a power dissipation of 0.12 milli-Watts
for a 2.5V output. For most applications, this is small
compared to the LDO pass device power dissipation
and can be neglected.
The maximum continuous operating junction
temperature specified for the MCP1824/MCP1824S is
+125°C. To estimate the internal junction temperature
of the MCP1824/MCP1824S, the total internal power
dissipation is multiplied by the thermal resistance from
junction to ambient (RθJA) of the device. The thermal
resistance from junction to ambient for the SOT-223-5
package is estimated at 62° C/W.
EQUATION 5-3:
T J ( MAX ) = P TOTAL × Rθ JA + T AMAX
TJ(MAX) = Maximum continuous junction
temperature
PTOTAL = Total device power dissipation
RθJA = Thermal resistance from junction to
ambient
TAMAX = Maximum ambient temperature
Where:
PLDO
=
LDO Pass device internal
power dissipation
VIN(MAX)
=
Maximum input voltage
VOUT(MIN)
=
LDO minimum output voltage
© 2007 Microchip Technology Inc.
DS22070A-page 21
MCP1824/MCP1824S
The maximum power dissipation capability for a
package can be calculated given the junction-toambient thermal resistance and the maximum ambient
temperature for the application. Equation 5-4 can be
used to determine the package maximum internal
power dissipation.
EQUATION 5-4:
P D ( MAX )
( T J ( MAX ) – T A ( MAX ) )
= --------------------------------------------------Rθ JA
PD(MAX) = Maximum device power dissipation
TJ(MAX) = maximum continuous junction
temperature
TA(MAX) = maximum ambient temperature
5.3
Typical Application
Internal power dissipation, junction temperature rise,
junction temperature, and maximum power dissipation
is calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
5.3.1
POWER DISSIPATION EXAMPLE
Package
Package Type = SOT-223-5
Input Voltage
VIN = 3.3V ± 5%
LDO Output Voltage and Current
VOUT = 2.5V
RθJA = Thermal resistance from junction-toambient
IOUT = 300 mA
Maximum Ambient Temperature
TA(MAX) = 60°C
EQUATION 5-5:
T J ( RISE ) = P D ( MAX ) × Rθ JA
Internal Power Dissipation
PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX)
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
x 300 mA
PD(MAX) = Maximum device power dissipation
PLDO = 0.308 Watts
RθJA = Thermal resistance from junction-toambient
EQUATION 5-6:
T J = T J ( RISE ) + T A
TJ = Junction temperature
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
TA = Ambient temperature
5.3.1.1
Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (RθJA) is
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
JESD51. The standard describes the test method and
board specifications for measuring the thermal
resistance from junction to ambient. The actual thermal
resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
TJ(RISE) = PTOTAL x RθJA
TJRISE = 0.308 W x 62° C/W
TJRISE = 19.1°C
DS22070A-page 22
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
5.3.1.2
Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
TJ = TJRISE + TA(MAX)
TJ = 19.1°C + 60.0°C
TJ = 79.1°C
5.3.1.3
Maximum Package Power
Dissipation at 60°C Ambient
Temperature
SOT-223-5 (62°C/W RθJA):
PD(MAX) = (125°C – 60°C) / 62°C/W
PD(MAX) = 1.048W
SOT-23-5 (256°C/Watt RθJA):
PD(MAX) = (125°C – 60°C)/ 256°C/W
PD(MAX) = 0.254W
From this table, you can see the difference in maximum
allowable power dissipation between the SOT-223-5
package and the SOT-23-5 package.
© 2007 Microchip Technology Inc.
DS22070A-page 23
MCP1824/MCP1824S
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
3-Lead SOT-223 (MCP1824S)
XXXXXXX
XXXYYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS22070A-page 24
Example:
Part Number
Marking
Code
MCP1824ST-0802E/DB
MCP1824ST-1202E/DB
MCP1824ST-1802E/DB
MCP1824ST-2502E/DB
MCP1824ST-3002E/DB
MCP1824ST-3302E/DB
MCP1824ST-5002E/DB
1824S08
1824S12
1824S18
1824S25
1824S30
1824S33
1824S50
1824S08
EDB0710
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
Package Marking Information (Continued)
5-Lead SOT-223 (MCP1824)
XXXXXXX
XXXYYWW
NNN
Example:
Part Number
Marking
Code
MCP1824T-0802E/DC
MCP1824T-1202E/DC
MCP1824T-1802E/DC
MCP1824T-2502E/DC
MCP1824T-3002E/DC
MCP1824T-3302E/DC
MCP1824T-5002E/DC
MCP1824T-ADJE/DC
1824082
1824122
1824182
1824252
1824302
1824332
1824502
1824ADJ
5-Lead SOT-23
XXNN
1
© 2007 Microchip Technology Inc.
1824082
EDC0710
256
Example:
Part Number
Marking
Code
MCP1824T-0802E/OT
MCP1824T-1202E/OT
MCP1824T-1802E/OT
MCP1824T-2502E/OT
MCP1824T-3002E/OT
MCP1824T-3302E/OT
MCP1824T-5002E/OT
MCP1824T-ADJE/OT
ULNN
UMNN
UPNN
UQNN
URNN
USNN
UTNN
UKNN
UL25
1
DS22070A-page 25
MCP1824/MCP1824S
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DS22070A-page 26
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
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0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2007 Microchip Technology Inc.
DS22070A-page 27
MCP1824/MCP1824S
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1RWH
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KWWSZZZPLFURFKLSFRPSDFNDJLQJ
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0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
DS22070A-page 28
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
APPENDIX A:
REVISION HISTORY
Revision A (November 2007)
• Original Release of this Document.
© 2007 Microchip Technology Inc.
DS22070A-page 29
MCP1824/MCP1824S
NOTES:
DS22070A-page 30
© 2007 Microchip Technology Inc.
MCP1824/MCP1824S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
XX
X
X
X/
XX
Output Feature Tolerance Temp. Package
Voltage Code
Device:
MCP1824: 300 mA Low Dropout Regulator
MCP1824T: 300 mA Low Dropout Regulator
Tape and Reel
MCP1824S: 300 mA Low Dropout Regulator
MCP1824ST: 300 mA Low Dropout Regulator
Tape and Reel
Output Voltage *:
08
12
18
25
30
33
50
ADJ
=
=
=
=
=
=
=
=
0.8V “Standard”
1.2V “Standard”
1.8V “Standard”
2.5V “Standard”
3.0V “Standard”
3.3V “Standard”
5.0V “Standard”
Adjustable Output Voltage ** (MCP1824 Only)
*Contact factory for other output voltage options
** When ADJ is used, the “extra feature code” and
“tolerance” columns do not apply. Refer to examples.
Extra Feature Code:
0
= Fixed
Tolerance:
2
= 2.5% (Standard)
Temperature:
E
= -40°C to +125°C
Package Type:
DB = Plastic Small Transistor Outline, SOT-223, 3-lead
DC = Plastic Small Transistor Outline, SOT-223, 5-lead
OT = Plastic Small Transistor Outline, SOT-23, 5-lead
Examples:
a)
b)
c)
d)
e)
f)
g)
h)
i)
MCP1824-0802E/XX:
MCP1824-1002E/XX:
MCP1824-1202E/XX:
MCP1824-1802E/XX:
MCP1824-2502E/XX:
MCP1824-3002E/XX:
MCP1824-3302E/XX:
MCP1824-5002E/XX:
MCP1824-ADJE/XX:
a)
b)
c)
d)
e)
f)
g)
h)
MCP1824S-0802E/XX:0.8V LDO Regulator
MCP1824S-1002E/XX:1.0V LDO Regulator
MCP1824S-1202E/XX:1.2V LDO Regulator
MCP1824S-1802E/XX:1.8V LDO Regulator
MCP1824S-2502E/XX:2.5V LDO Regulator
MCP1824S-2502E/XX:3.0V LDO Regulator
MCP1824S-3302E/XX:3.3V LDO Regulator
MCP1824S-5002E/XX:5.0V LDO Regulator
XX =
=
=
0.8V LDO Regulator
1.0V LDO Regulator
1.2V LDO Regulator
1.8V LDO Regulator
2.5V LDO Regulator
3.0V LDO Regulator
3.3V LDO Regulator
5.0V LDO Regulator
ADJ LDO Regulator
DB for 3LD SOT-223 package
DC for 5LD SOT-223 package
OT for 5LD SOT-23 package
Note: ADJ (Adjustable) only available in 5-lead version.
© 2007 Microchip Technology Inc.
DS22070A-page 31
MCP1824/MCP1824S
NOTES:
DS22070A-page 32
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS22070A-page 33
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AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
Fax: 852-2401-3431
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Tel: 91-11-4160-8631
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Tel: 886-2-2500-6610
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Tel: 86-27-5980-5300
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Italy - Milan
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Tel: 34-91-708-08-90
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Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
10/05/07
DS22070A-page 34
© 2007 Microchip Technology Inc.