E7765
1.3 GHz Quad
Pin Electronics Driver
TEST AND MEASUREMENT PRODUCTS
Features
Description
•
•
•
•
•
•
The E7765 four channel, monolithic ATE pin electronics
solutions manufactured in a high-performance
complementary bipolar process.
The E7765 power consumption can be minimized to accommodate the required performance and levels. The
E7765 has bias and other inputs that provide a means to
adjust performance versus power consumption. The
E7765 operates at data rates up to 1.3 GHz/2.6 Gbps.
The power supplies to the E7765 are specified over a wide
range to accommodate between –2V, +7V and –0.5V,
+4.2V output voltage ranges.
Four Fully Integrated, Three-Statable Drivers
Wide Choice of Range, Performance vs. Power
Differential Driver Mode
Programmable Driver Rise, Fall Times
–2V, +7V Driver Voltage Range
Small, 80-Pin LQFP Package
Functional Block Diagram
The E7765 driver is capable of generating 8V swings over
a –2 to +7V range. The driver minimum swing is 100 mV.
A differential driver mode configures pairs of adjacent drivers on-chip to drive differential signals from a single data
input. The driver pairs are DOUT[0]:DOUT[1] and
DOUT[2]:DOUT[3]. The on-chip distribution of the driving
signal and the close matching of performance on-chip will
result in very low skew for differential output to output.
Channel 0
DBIAS
DVH
DE
DEN
DEN*
DH
RADJ
DOUT
FADJ
DVL
PON
DHI
DHI*
SEL_DHI
SEL
DHI
DHI*
PON
DVL
FADJ
DH
DE
DEN
DEN*
DOUT
RADJ
DVH
DBIAS
Channel 1
CATHODE
ANODE
Applications
Channel 2
DBIAS
DVH
DE
DEN
DEN*
• Memory Testers
– Companion Chip to E7725 as Drive-Only
Channels
• Programmable Clock Drivers
• Test Instruments
DH
RADJ
DOUT
FADJ
DVL
PON
DHI
DHI*
SEL_DHI
SEL
DHI
DHI*
PON
DVL
FADJ
DH
DE
DEN
DEN*
DOUT
RADJ
DVH
DBIAS
Channel 3
Revision 11 / July 18, 2006
1
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E7765
TEST AND MEASUREMENT PRODUCTS
PIN Description
[0:3] R
ef
er
o Channels 0, 1
Ref
efer
erss tto
1,, 2 or 3
Pin #
Pin N ame
D escription
D river
56, 57; 44, 45;
4, 5; 16, 17
D OUT[0:3]
D ri ver output.
52, 49, 9, 12
53, 48, 8, 13
D HI[0:3]
D HI*[0:3]
70, 31, 71, 30
69, 32, 72, 29
D EN[0:3]
D EN*[0:3]
"Flex" di fferenti al i nput pi ns whi ch control the dri ver output bei ng acti ve
or i n a hi gh i mpedance state.
64, 37, 77, 24
65, 36, 76, 25
D VH[0:3]
D VL[0:3]
Hi gh i mpedance analog voltage i nputs whi ch determi ne the dri ver hi gh
and low levels.
67, 34, 74, 27
68, 33, 73, 28
RAD J[0:3]
FAD J[0:3]
66, 35, 75, 26
D BIAS[0:3]
Analog current i nput that sets an i nternal bi as current for the dri ver and
i ts overall performance by adjusti ng the overall power.
47, 14
SEL_D HI[0:1]
TTL i nputs that select the D i fferenti al D ri ve mode when a logi cal hi gh.
SEL_D HI[0] wi ll enable D OUT[0] and D OUT[1] to di fferenti al mode.
SEL_D HI[1] enables D OUT[2] and D OUT[3] to di fferenti al mode.
60, 41, 1, 20
PON[0:3]
TTL i nput that powers the dri ver ON and OFF. Logi cal 1 wi ll power ON.
59, 58, 51;
50 43, 42; 2, 3, 10;
11, 18, 19
VC C [0:3]
Posi ti ve power supply to each of the four dri ver channels (Note 1).
62, 61, 55;
46, 40, 39;
79, 80, 6;
15, 21, 22
VEE[0:3]
Negati ve power supply to each of the four dri ver channels (Note 1).
63, 38, 78, 23
GND [0:3]
D evi ce ground to each of the four dri ver channels (Note 1).
"Flex" di fferenti al i nput di gi tal pi ns whi ch select the dri ver hi gh or low
level.
Input currents whi ch determi ne the dri ver output si gnal ri se and fall
ti mes.
C ontrol
Pow er Supplies
M iscellaneous
7, 54
Note 1:
C ATHOD E, ANOD E
Termi nals of the on-chi p thermal di ode stri ng.
All VEEs must be connected, externally, to the same supply.
All VCCs must be connected, externally, to the same supply.
All GNDs must be connected, externally.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
2
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E7765
TEST AND MEASUREMENT PRODUCTS
PIN Description (continued)
80 Lead LQFP P
ack
age
Pack
ackage
14 x 1
4x1
.4mm
14
1.4mm
PON[2]
1
60
PON[0]
VCC[2]
VCC[2]
2
59
VCC[0]
3
58
VCC[0]
DOUT[2]
4
57
DOUT[0]
DOUT[2]
5
56
DOUT[0]
VEE[2]
6
55
VEE[0]
CATHODE
DHI*[2]
7
54
ANODE
8
53
DHI*[0]
DHI[2]
9
52
DHI[0]
VCC[2]
10
51
VCC[0]
VCC[3]
DHI[3]
11
50
VCC[1]
49
DHI[1]
DHI*[3]
13
48
DHI*[1]
SEL_DHI[1]
14
47
SEL_DHI[0]
VEE[3]
DOUT[3]
15
46
VEE[1]
16
45
DOUT[1]
DOUT[3]
17
44
DOUT[1]
VCC[3]
18
43
VCC[1]
VCC[3]
PON[3]
19
42
VCC[1]
20
41
PON[1]
12
© 2006 Semtech Corp. , Rev. 11, 7/18/06
80 Lead MQFP
14 x 14 x 1.4 mm
Top Side
3
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E7765
TEST AND MEASUREMENT PRODUCTS
Circuit Description
Introduction
Figure 1 shows a detailed block diagram of the E7765.
Channel 0
DBIAS[0]
DVH[0]
Each of the four drivers has independent signal control
and voltage inputs. In addition, each driver has
independent power-down ability as well as adjustability
for output rising and falling edge speeds.
Refer to Table 1 for a truth table depicting the different
modes of operation of an individual channel. Table 2
expands on the independent operations with a description
of the differential drive mode operation. Differential pair[0]
consists of drive channels 0 and 1 and are controlled by
SEL_DHI[0]. Differential pair[1] consists of drive channels
2 and 3 and are controlled by SEL_DHI[1].
Channel 0 Control
X
DEN[0]
X
PON[0]
0
X
0
1
HiZ
0
1
1
D VL
1
SEL_DHI[0]
1
SEL
DHI[1]
DHI*[1]
PON[1]
DVL[1]
FADJ[1]
DH
DE
DEN[1]
DEN*[1]
DOUT[1]
RADJ[1]
DVH[1]
DBIAS[1]
Channel 1
CATHOD
ANODE
Channel 2
Low Power, HiZ State
DBIAS[2]
DVH[2]
Driver Disabled (HiZ)
DEN[2]
DEN*[2]
DE
DH
RADJ[2]
DOUT[2]
FADJ[2]
DVL[2]
Driver Enabled, Follow DHI
1
DOUT[0]
FADJ[0]
DVL[0]
DOUT[0]
Off
DH
RADJ[0]
PON[0]
DHI
DHI*[0]
Output
Comments
DHI[0]
DE
DEN[0]
DEN*[0]
PON[2]
DHI[2]
DHI*[2]
D VH
Channels 1, 2 and 3 similar. SEL_DHI[0] and [1] at logical low.
SEL_DHI[1]
SEL
DHI[3]
DHI*[3]
PON[3]
DVL[3]
Table 1. Driv
er Contr
ol TTruth
ruth TTable
able
Driver
Control
FADJ[3]
DH
DE
DEN[3]
DEN*[3]
DOUT[3]
RADJ[3]
DVH[3]
DBIAS[3]
Channel 3
Figure 1. E7
765 De
tailed Bloc
k Diagram
E77
Detailed
Block
© 2006 Semtech Corp. , Rev. 11, 7/18/06
4
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E7765
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
Channel 0 Control
Diff Mode
SEL_DHI[0]
Channel 1 Control
Output
DEN[0]
PON[0]
DOUT[0]
1
X
X
0
Off
X
0
1
HiZ
1
0
X
0
Off
X
1
1
DVH[1]
1
1
X
0
Off
X
1
1
DVL[1]
1
0
0
1
HiZ
X
X
0
Off
1
0
1
1
DVL[0]
X
1
1
DVH[1]
1
1
1
1
DVH[0]
X
1
1
DVL[1]
1
0
1
1
DVL[0]
X
0
1
HiZ
1
1
1
1
DVH[0]
X
0
1
HiZ
1
0
0
1
HiZ
X
1
1
DVH[1]
1
1
0
1
HiZ
X
1
1
DVL[1]
0
DHI[1]
DEN[1]
Output
DHI[0]
PON[1]
Comments
DOUT[1]
SEL_DHI[0]=0, Channel 0 and Channel 1 are independently controlled (see Table 1)
Differential mode, PON and DEN are independent per channel.
Differential mode, both channels enabled.
Differential mode, DOUT[0] logically follows DHI[0]
Differential mode, DOUT[1] logically follows the complement of DHI[0]
DHI[1] has no effect in differential mode since the Channel 1 output will follow the complemented state of DHI[0].
Channel 2 Control
Diff Mode
SEL_DHI[1]
Channel 3 Control
Output
DEN[2]
PON[2]
DOUT[2]
1
X
X
0
Off
X
0
1
HiZ
1
0
X
0
Off
X
1
1
DVH[3]
1
1
X
0
Off
X
1
1
DVL[3]
1
0
0
1
HiZ
X
X
0
Off
1
0
1
1
DVL[2]
X
1
1
DVH[3]
1
1
1
1
DVH[2]
X
1
1
DVL[3]
1
0
1
1
DVL[2]
X
0
1
HiZ
1
1
1
1
DVH[2]
X
0
1
HiZ
1
0
0
1
HiZ
X
1
1
DVH[3]
1
1
0
1
HiZ
X
1
1
DVL[3]
0
DHI[3]
DEN[3]
Output
DHI[2]
PON[3]
Comments
DOUT[3]
SEL_DHI[1]=0, Channel 2 and Channel 3 are independently controlled (see Table 1)
Differential mode, PON and DEN are independent per channel.
Differential mode, both channels enabled.
Differential mode, DOUT[2] logically follows DHI[2]
Differential mode, DOUT[3] logically follows the complement of DHI[2]
DHI[3] has no effect in differential mode since the Channel 3 output will follow the complemented state of DHI[2].
Table 2. Dif
ol – Driv
er S
tat
e TTruth
ruth TTables
ables
Diffferential Mode Contr
Control
Driver
Stat
tate
© 2006 Semtech Corp. , Rev. 11, 7/18/06
5
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E7765
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
Driv
er
Driver
The driver digital control inputs DHI/DHI* and DEN/DEN*
are “Flex Inputs” – wide voltage differential inputs capable
of receiving ECL, TTL, CMOS, or custom level signals.
Single-ended operation is supported by connecting the nondriven, differential input to the appropriate DC threshold
level. Differential input drive is recommended for highest
performance.
Drive Enable
The drive enable inputs (DEN / DEN*) control whether the
driver is forcing a voltage, or is placed in a high-impedance state. If DEN is more positive than DEN*, the output
will force either DVH or DVL. If DEN is more negative than
DEN*, the output goes into a high impedance state. The
DEN/DEN* inputs are independent per drive channel and
remain effective in the differential mode.
Do NO
T lea
NOT
leavve DEN / DEN* floating.
Driver Data
When the driver is enabled (Table 1) the drive data inputs
(DHI / DHI*) determine whether the driver output is forcing a high or a low. If DHI is more positive than DHI*, the
driver will force DVH when the driver is active. If DHI is
more negative than DHI*, the driver will force DVL when
active. The DHI/DHI* inputs are independent per drive
channel, but these input signals for drive channels 1 and
3 are not effective when differential mode is enabled.
SEL_DHI[0] = 1 is used for outputting a differential signal
where DOUT[1] is the inverse of DOUT[0] with the minimum of skew, and both drivers respond to the DHI/DHI*[0]
signal. More detail is shown in Table 2. Notice that poweron (PON) and drive enable (DEN) controls are all still in
effect for individual drivers. SEL_DHI[1] likewise controls
the second pair, channels 2 and 3.
Driver Levels
DVH and DVL are high input impedance voltage inputs
which establish the driver’s high and low output levels.
Driver Bias
The DBIAS pin is an analog current input which establishes
an on-chip bias current, from which other currents are
generated. This current, to some degree, also establishes
the overall power consumption and performance of the
drivers. Each driver is given its own DBIAS control to allow
for varying performance among the four drivers.
Ideally, an adjustable external current source would be
used to minimize any part-to-part performance variation
within a test system. However, a precision external resistor tied to a large positive voltage is typically acceptable.
(See figure below.) The optimal DBIAS current is a function of the RADJ and FADJ settings, and cannot be set independently.
The established bias current follows the equation:
DBIAS = (VCC - 0.7) / (Rext + 462Ω).
Do NO
T lea
NOT
leavve DHI / DHI* floating.
Driver Differential Mode Selection
Rext
The TTL input SEL_DHI will place a pair of drive channels
into a differential drive mode. Channels 0 and 1 are a
differential pair that is independent from the channel 2
and 3 differential pair.
SEL_DHI[0]
DH[0] from:
DH[1] from:
0
DHI/DHI*[0]
DHI/DHI*[1]
1
DHI/DHI*[0]
DHI*/DHI[0]
© 2006 Semtech Corp. , Rev. 11, 7/18/06
BIAS
VCC
462Ω
VEE
6
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E7765
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
Driver Slew Rate Adjustment
Thermal Monitor
The driver rising and falling transition times are independently adjustable. The RADJ and FADJ pins are analog
current inputs which establish the driver rise and fall times.
An on-chip thermal diode string of five diodes in series
exists (see figure below). This string allows accurate die
temperature measurements.
Ideally, an adjustable external current source would be
used for RADJ and FADJ. However, for applications where
the rise and fall times are fixed, precision external resistors to a positive voltage can be used. The currents into
RADJ and FADJ follow the equation:
An external bias current of 100 µA is injected through the
string, and the measured voltage corresponds to a specific junction temperature with the following equation:
Tj[°C] = {(ANODE – CATHODE) / 5 – 0.768} / (–0.00169).
RADJ, FADJ = (VCC - 0.7) / (Rext + 550Ω).
ANODE
Bias Current
Rext
RADJ, FADJ
VCC
550Ω
Temperature Coefficient =
-7.9 mV / °C
Rise/Fall
Adjust Current
CATHODE
VEE
The diagrams opposite show how driver rise and fall are
adjusted by RADJ, FADJ and DBIAS.
Power Supply Sequencing
In order to avoid the possibility of latch-up, the following
power-up requirements must be satisfied:
1.
2.
3.
Power Down of the Driver
Referring to Table 1, there are configurations in which a
driver can be put into a power down mode, and others in
which the driver is powered and ready for operation.
PON[0:3] are the TTL inputs controlling power to the individual driver circuits. A logical 1 will power up the driver.
The PON inputs remain effective on a per-driver basis in
differential mode.
VEE <= GND <= VCC at all times
VEE <= Analog Inputs <= VCC
VEE <= Digital Inputs <= input max voltage or
VCC, whichever is less
The following sequencing can be used as a guideline when
powering up the E7765:
1.
2.
3.
4.
VEE
VCC
Digital Inputs
Analog Inputs
The recommended power-down sequence is the reverse
order of the power-up sequence.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
7
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E7765
TEST AND MEASUREMENT PRODUCTS
Application Information
Computing the Driver Output Voltage Range
The output voltage range of the driver at the DOUT pin is
defined by two fundamental calculations. First is the relationship to the power supply voltages at the device (VCC
and VEE) and second to the range of programmability of
the DVH and DVL input voltages. Remaining in the calculated output voltage range is required to maintain all the
DC and AC accuracy specifications for the driver function.
The DOUT range relative to the power supply voltages is
straightforward and depicted in the following figure at the
output of the driver. The required DOUT range must comply with the noted headrooms to the VCC and VEE power
supplies. Headrooms larger than noted is also acceptable
but must remain within the power supply recommended
operating ranges.
D
V
H
To solve for the range of VIN, first select the Vout ranges
required. For example, if we choose -2.0V for the minimum
end and +6.5V for the maximum end of VDOUT, and an offset min/max of -100mV/+100mV and a minimum gain of
0.975 the equations solve as;
These resulting VIN values then need to meet the headroom requirements previously mentioned as well as the
absolute (relative to ground) voltage limitations specified
in the DC specifications data.
DVH
DOUT
or
D
O
U
T
Com
puting Maximum P
ower Consum
ption
Computing
Po
Consumption
DVL
T
4.0V
Solving for VIN;
VIN = [ VDOUT(MIN/MAX) + VOFFSET(MIN/MAX) ] / GAIN(MIN)
For +6.5V;
VIN(+6.5V) = [ +6.5V + 100mV ] / 0.975 = +6.769V
3.8V
4.0V
D
V
L
VDOUT(MIN/MAX) = VOFFSET(MIN/MAX) + [ VIN * GAIN(MIN) ]
For -2.0V;
VIN(-2V) = [ -2.0V – 100mV ] / 0.975 = -2.154V
VCC
3.5V
specifications require that the DVH/L input programming
range be greater than the required DOUT voltage range if
the worst case offset and gain figures are used. The equation for the resulting minimum and maximum voltage at
DOUT is;
The diagram below shows the power consumption of the
E7765 as a function of power supply and performance
bias settings.
3.7V
3.5V
Power Dissipation
Covers Complete Range of Supplies (All PON=1)
VEE
11.0
10.0
The DOUT range is also dependant on the allowable programming voltages at the DVH and DVL inputs. Each of
these inputs have similar requirements for power supply
headrooms as DOUT does. These headrooms are also
depicted in the figure. Furthermore, the DVH/L inputs will
have voltage offsets and gain error specifications. These
© 2006 Semtech Corp. , Rev. 11, 7/18/06
8
Power (W)
9.0
High Performance
8.0
7.0
6.0
Lower Performance
5.0
4.0
Min Supplies
Typ Supplies
Max Supplies
www.semtech.com
E7765
TEST AND MEASUREMENT PRODUCTS
Application Information (continued)
The power consumption goes up as the power supplies
are raised in voltage, and the RADJ, FADJ and DBIAS settings are increased for higher frequency performance.
There are specifications and graphs for the relationships
of these controls to overall performance in the DC Specifications section. Refer to them for choosing the settings
for a particular system performance. This section deals
with how to heatsink the various power dissipation levels.
Cooling Considerations
Depending on the applied power supply levels and bias
conditions the E7765 will use, various methods of
heatsinking will be required to keep the maximum die junction termperature within a safe range and below the specified maximum of 100°C.
the heatsink and at what angle the air is impacting the
heatsink. There are many options available in selecting a
heatsinking system. The formula below shows how to calculate the required maximum thermal impedance for the
entire heatsink system. Once this is known, the designer
can evaluate the options that best fit the system design
and meet the required Rθ.
Rθ(heatsink_system) = (TJmax - Tambient - P * θJC) / P
where, Rθ (heatsink_system) is the thermal resistance
of the entire heatsink system
TJmax is the maximum die temperature
(100°C)
Tambient is the maximum ambient air temp
expected at the heatsink (°C)
P is the maximum expected power
dissipation of the E7765 (Watts)
θJC is the thermal impedance of the
E7765 junction to case (0.8°C/W)
Another variable that needs to be determined is the maximum ambient air temperature that will be surrounding or
blowing on the device and/or the heatsink system in the
application (assuming an air cooled system). A heatsinking
solution should be chosen to be at or below a certain thermal impedance known as Rθ in units of °C/Watt. The
heatsinking system is a combination of factors including
the actual heatsink chosen and the selection of the interface material between the E7765 and the heatsink itself.
This could be thermal grease or thermal epoxy, and they
also have their own thermal impedances. The heatsinking
solution will also depend on the volume of air passing over
© 2006 Semtech Corp. , Rev. 11, 7/18/06
R Ξ of Heatsink System (° C/W)
The E7765 package has an integral heat slug located at
the top side of the package to efficiently conduct heat away
from the die to the package top. The thermal resistance of
the package to the top is the θJC (junction-to-case) and is The graph below uses the power estimates from the previspecified at 0.8°C/Watt.
ous graph and indicates the required maximum thermal
impedances required for the heatsinking system using the
In order to calculate what type of heatsinking should be above formula with Tambient at 35°C.
applied to the E7765, the designer needs to determine
o be tak
en when increasing the operating
taken
the worst case power dissipation of the device in the appli- Care needs tto
J, FFAD
AD
puts. Monit
oring the die ttem
em
peracation. The graph above gives a good visual relationship of DBIAS, RAD
RADJ,
ADJJ in
inputs.
Monitoring
emperauat
e heatsinking and air
flo
w is vver
er
o insure adeq
eryy
adequat
uate
airflo
flow
the range of power dissipation that can be expected from ture tto
por
tant.
impor
portant.
the E7765. The range of power covers the different modes im
.
of operation, power supply settings, and performance bias
adjustments available. Use the data and graphs in subseRequired Heatsinking Thermal Resistances
Covers Complete Range of Supplies (All PON=1)
quent sections to determine a particular applications power
16.0
dissipation.
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0.0
Min Supplies
Typ Supplies
Max Supplies
More information on heatsink system selections can be
read on heatsink vendors’ web sites and in the Semtech
Application Note #ATE-A2 Cooling High Power, High Density Pin Electronics.
9
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E7765
TEST AND MEASUREMENT PRODUCTS
Application Information (continued)
E7765 Hookup
VEE[2]
80,79,6
PON[2]
DVL/DVH, DBIAS,
RADJ, FADJ[2] DEN[0,2]
78
5
4
73-77
69-72
DVL/DVH, DBIAS,
RADJ, FADJ[0]
5
64-68
63
59,58
2,3
6
DHI[2]
DHI[3]
CH[2]
7
VCC[2,3]
2
SEL_DHI[1]
3pF
CH[0]
8,9
52,53
10,11
50,51
12,13
48,49
DHI[0]
2
VCC[0,1]
2
CH[3]
DHI[1]
SEL_DHI[0]
47
15
DOUT[1
46
CH[1]
VCC[1] 3pF
3pF VCC[3]
43,42
18, 19
PON[3]
ANODE
54
14
DOUT[3]
DOUT[0
55
3pF
2
PON[0]
VCC[0]
VCC[2]
CATHODE
61,62,55
60
1
DOUT[2]
VEE[0]
41
20
15,21,22
VEE[3]
23
24-28
29-32
33-37
5
4
5
DVL/DVH, DBIAS, DEN[3,1]
RADJ, FADJ[3]
38
DVL/DVH, DBIAS,
RADJ, FADJ[1]
PON[1]
46,40,39
VEE[1]
VEEs, VCCs and GNDs of all channels must be connected together.
All capacitors shown are 0.1µF unless otherwise noted.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
10
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E7765
TEST AND MEASUREMENT PRODUCTS
Package Information
14 x 1
4x1
.4 mm, 80-Pin LQFP P
ack
age (Die Do
wn)
14
1.4
Pack
ackage
Down)
(with Exposed Me
tal
Heat
Slug)
Metal
D
D1
N
EXPOSED HEAT SLUG
1
9.65± .50 DIA.
–A–
–B–
E1
TOL.
A
MAX
A1
E
HEAT SLUG INTRUSION
.0127 MAX.
–D–
DIMS.
Top Vie
w
View
1.60
.05 m in/.15 m ax
A2
±.05
1.40
D
±.20
16.00
D1
±.05
14.00
E
±.20
16.00
E1
±.05
14.00
L
+.15/-.10
0.60
e
BASIC
0.65
b
±.05
0.30
θ
0° - 7°
ddd
MAX
0.13
ccc
MAX
0.10
STANDOFF
A
A1
A2
.25
SEATING PLAN
θ
–C–
b
ddd M
C A–B S
D S
LEAD COMPLANARITY
ccc
C
L
NOTES:
1)
All dimensions in mm.
2)
Dimensions shown are nominal
with tol. as indicated.
3)
L/F: EFTEC 64T copper or
equivalent, 0.127 mm (.005”) or
0.15 mm (.006”) THICK.
4)
Foot length “L” is measured at
gage plane at 0.25 above the
seating plane.
5)
Lead finish 85/15 Sn/Pb.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
11
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E7765
TEST AND MEASUREMENT PRODUCTS
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
VCC (relative to GND)
VCC
0
11.75
V
AM1
VEE (relative to GND)
VEE
–6.5
0
V
AM2
18.25
V
AM3
Total Power Supply
VCC – VEE
Digital Input Voltages
DHI(*), DEN(*)
VEE
VCC
V
AM5
Digital Differential Input Voltages
DHI(*), DEN(*)
–2.5
2.5
V
AM6
Digital TTL Inputs
SEL_DHI, PON
–2.5
VCC
V
AM7
Input Voltages
DVH, DVL
VEE
VCC
V
AM8
Current Inputs
RADJ, FADJ, DBIAS
–0.5
2.5
V
AM10
Analog Input Currents
RADJ, FADJ, DBIAS
0
2
mA
AM12
Driver Output Current
Iout
–40
40
mA
AM15
DVH – DVL
0
11.5
V
AM16
Storage Temperature
TS
–65
150
ûC
AM18
Junction Temperature
TJ
125
ûC
AM19
Soldering Temperature
TSOL
260
ûC
AM20
Driver Swing
(5 seconds, .25" from the pin)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only, and functional operation of the device at these, or any other conditions beyond those “recommended”, is not implied. Exposure to conditions above those “recommended” for extended periods may affect device
reliability.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
12
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E7765
TEST AND MEASUREMENT PRODUCTS
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Positive Power Supply
VCC
8
10
11.6
V
Negative Power Supply (Note 1)
VEE
–6.25
–5
–4.2
V
VCC – VEE
12.2
15
17.85
V
Total Analog Supply
Analog Inputs
Driver Bias Current
Driver Slew Rate Adjustments
DBIAS
0.6
mA
RADJ, FADJ
0.9
mA
0.8
ûC/W
Thermal Resistance of Package (Note 2)
Junction Temperature
TJ
40
100
ûC
Note 1: For ‘Negative’ ECL “Flex” inputs (DHI, DEN) with range down to –2V input voltage, VEE - –4.75V.
Note 2: Measured at top of package on exposed heat slug.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
13
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E7765
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
Parameter
Symbol
Min
Input Low Level
VIL
Input High Level
Input Bias Current
Typ
Max
Units
0
0.8
V
VIH
2
5
V
IIN
–50
50
µA
Symbol
Min
Max
Units
DOUT
DOUT
–2.0
VEE + 3.7
+7.0
VCC – 3.8
V
V
DVH
DVH
VEE + 4.0
–1.5
VCC – 3.5
+7.4
V
V
DVL
DVL
VEE + 3.5
–2.25
VCC – 4.0
+6.5
V
V
DOUTSW
I_in
DBIAS
RADJ, FADJ
VDBIAS, VRADJ, VFADJ
0.1
–35
0.5
0.3
–0.2
8.0
+35
1.5
1.5
+2.0
V
µA
mA
mA
V
Imax
Rout
–35
4.0
–1
–500
+35
8.0
+1
+500
mA
Ω
µA
nA
DVH, DVL – DOUT
∆DOUT/C
∆DOUT/∆DVH,
∆DOUT/∆DVL
–265
+265
Control Inputs (SEL_DHI, PON)
Parameter
DRIVER Circuit
Output Range
Analog Inputs
High Level
Low Level
Driver Swing
Input Current
Driver Bias
Slew Rate Adjustments
RADJ, FADJ, DBIAS Voltage Compliance
Driver Output (Note 1)
DC Output Current
Output Impedance (@ ±25mA) (Note 3)
HiZ Leakage (Driver HiZ, Powered Up)
HiZ Leakage (Driver HiZ, Powered Down)
DC Accuracy (Note 1)
{DESIGN_SPEC: Determine Offset + Gain}
Offset Voltage (@ DVH = DVL = 0)
Offset Tempco (DVL = 0V, DVH = 3V)
Gain (Measured @ allowable –FS and +FS)
Linearity (Full Range @ 0V and 75% of DVH/L
max input calibration points) (Note 4)
Digital Inputs (DHI/DHI*, DEN/DEN*)
Input Voltage Range (Note 2)
Differential Input Swing
Input Current
Input Capacitance
© 2006 Semtech Corp. , Rev. 11, 7/18/06
Typ
4.7
0.965
1.0
mV
mV/C
V/V
DOUT INL
–10
+10
mV
DHI(*), DEN(*)
|Input – Input*|
Iin
–2.0
0.24
–300
+5.0
2.0
+300
3.0
V
V
µA
pF
Cin
14
0.5
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E7765
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
DC conditions (unless otherwise specified): Over the full "Recommended Operating Conditions".
Note 1:
Note 2:
Note 3:
Note 4:
See Applications Section describing the applicable “DRIVER OUTPUT RANGE” as a function of VCC and VEE.
Digital Input Voltage Range also > VEE + 2.75V.
The typical value for Rout should be used to calculate the external resistor for matching to the
application’s transmission line impedance.
The 2-point calibration for full range should be done at 0V and 75% of the maximum DVH and DVL
input. While the 1st calibration point (0V) will be the same for both DVH and DVL, the 2nd calibration
point will be different (ie. DVH: 75% * (VCC - 3.5), DVL: 75% * (VCC - 4.0)).
Parameter
Symbol
Min
Typ
Max
Units
All Drivers Powered ON (PON = 1)
Positive Supply
Negative Supply
ICC
IEE
390
–450
430
–490
mA
mA
All Drivers Powered Down (PON = 0)
Positive Supply
Negative Supply
ICC
IEE
340
–350
370
–420
mA
mA
Power Supply Currents
DC conditions: DVL = 0V, DVH = 3V, SEL_DHI[0:1] and DHI[0:3] at logical low.
DBIAS = 0.6mA, RADJ = FADJ = 0.9mA.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
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E7765
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
Highest Performance Total Power Curves
12
11
10
Power (W)
PON = 1
9
8
PON = 0
7
6
5
Minimum
Typical
Maximum
Power Supply Settings
Lower Performance Total Power Curves
8
Power (W)
7
PON=1
6
PON=0
5
4
3
Minimum
Typical
Maximum
Power Supply Settings
© 2006 Semtech Corp. , Rev. 11, 7/18/06
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E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics
AC TTest
est Cir
cuit
Circuit
45.3Ω
50Ω Transmission Line
(20 inches, ~2 ns)
(RL)
953Ω
DOUT
C
3pF
© 2006 Semtech Corp. , Rev. 11, 7/18/06
C
VSWING
3 pF
0.8V (ECL)
3 pF
0.3V (LVDS)
5 pF
3.0V (LVTTL)
8 pF
5.0V (CMOS/TTL)
17
Oscilloscope
50Ω
www.semtech.com
E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
Parameter
DRIVER Circuit (DBIAS = 0.6mA)
(RADJ = FADJ = 0.9 mA unless otherwise noted)
Output Impedance (@ ±25mA over temperature and
power supplies)
Propagation Delay (0 to 1V Output) (Note 1)
Data (DHI) to Output (Figure 5)
Output Active to HiZ (Figure 4)
HiZ to Output Active (Figure 4)
Rise/Fall Times (Figure 6)
0 to 1V (20% - 80%)
0 to 3V (10% - 90%)
Crossover Voltage Error (Figure 9)
Fmax (RL=50Ω, swing=programmed value) (Note 2)
(Figure 7)
Symbol
Min
Typ
Max
Units
Rout
4.0
6.0
8.0
Ω
TPLH, TPHL
TPAZ
TPZA
0.5
0.75
1.0
1.5
1.5
2.0
ns
ns
ns
0.25
0.6
55
ns
ns
%
Tr/Tf
Tr/Tf
VXOVER
0 to 1V
0 to 3V
Pulse Width (RL=50Ω, swing=programmed value) (Note
2) (Figure 3)
Fmax
Fmax
Tpw
0.13
0.55
45
1200
600
1300
700
0 to 1V
0 to 3V
Pulse Width Dispersion to Minimum Pulse Width
(PWmin = 0.5 ns, 50Ω terminated) (Figure 2)
Driver-to-Driver Skew (Diff. Driver Mode) (Note 3)
Output Capacitance
Delay Tempco (Figure 5) (Switching DVH and DVL)
Delay Symmetry (same driver, 1.0V swing) (Figure 5)
Trans. Time Matching (same driver) (Figure 6)
DOUT = 1.0V
DOUT = 3.0V
Overshoot/Undershoot (Figure 8)
DOUT = 1.0V
DOUT = 3.0V
Ringback (Figure 8)
DOUT = 1.0V
DOUT = 3.0V
Voltage Crosstalk (when switching adjacent channel)
DOUT = 1.0V
DOUT = 3.0V
Timing Crosstalk
DOUT = 1.0V
DOUT = 3.0V
∆Tpw
10
4.6
1
Cout
∆Tpd/ûC
|TPHL – TPLH|
∆Tr,f
∆Tr,f
0
0
±9
±12
MHz
MHz
0.6
0.9
ns
ns
50
ps
30
1.5
50
ps
pF
ps/ûC
ps
50
100
ps
ps
300
250
mV
mV
250
150
mV
mV
±20
±30
mV
mV
±12
±30
ps
ps
AC test conditions (unless otherwise specified): "Recommended Operating Conditions". VCC = +10V, VEE = –5V.
Note 1: Propagation delays for LV_PECL differential logic inputs.
Note 2: At 10% output amplitude attenuation. CLOAD in AC test circuit = 0 pF.
Note 3: 0 to 800 mV outputs.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
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E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Units
50
ns
Control Logic
SEL_DHI (Note 1)
Note 1:
TDIFF_D
Includes the time needed to settle new drive levels to within 10% of programmed values.
© 2006 Semtech Corp. , Rev. 11, 7/18/06
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E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
Period = 50 ns
Tpw, in1 = 50 ns - PWmin
Tpw, in2 = PWmin
Tpw,in1
(DHI - DHI*)
Tpw,in2
0.0V
Time
OUT
OUTPUT: OUT(H) = 0.8V; OUT(L) = 0.0V
0.4V
Time
0.0V
Tpw,out2
Tpw,out1
∆Tpw = |(Tpw,in1 - Tpw,out1) - (Tpw,in2 - Tpw,out2)|
The measured result is the absolute value of the change in [Tpw,in – Tpw,out] as
the P.W. changes from 25 ns to the end points of PWmin and [50ns – PWmin].
Figure 2. Driv
er DIN tto
o OUT Disper
sion Measurement Def
inition
Driver
Dispersion
Definition
Period = 100 ns
OUT
Tpw+
Tpw–
VOH
VOL + 0.9 * (VOH–VOL)
Output
Signal
(VOH+VOL)/2
VOL + 0.1 * (VOH–VOL)
VOL
Time
Figure 3. Driv
er Minimum Pulse Width Measurement Def
inition
Driver
Definition
© 2006 Semtech Corp. , Rev. 11, 7/18/06
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E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
(DEN - DEN*)
0.0V
Time
OUTPUT: DVH = 0.8V, DVL =
0.8V
OUT
TPZA
DVH
TPAZ
+800mV
90%
10%
0.0V
10%
DVL
Time
90%
800mV
(RLOAD at DOUT = 50Ω to GND)
Figure 4. Driv
er HiZ Enable/Disable Dela
inition
Driver
Delayy Measurement Def
Definition
OUTPUT: OUT(H) = 0.8V; OUT(L) = 0.0V
(DHI – DHI*)
0.0V
Time
OUT
TPLH
TPHL
+0.8V
+0.4V
0.0V
Time
Figure 5. Driv
er Tpd: DHI tto
o OUT
tr
rac
king Sk
ew Measurement Def
inition
Driver
OUT,, Symme
Symmetr
tryy, and TTrac
racking
Ske
Definition
© 2006 Semtech Corp. , Rev. 11, 7/18/06
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E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
OUT
Tr
OUT(H)
V1
Tf
V2
0.0V
Time
V2 is 0.1 * OUT(H) for 3V and 5V, 0.2* OUT(H) for 0.8V and lower
V1 is 0.9 * OUT(H) for 3V and 5V, 0.8* OUT(H) for 0.8V and lower
Figure 6. Driv
er TTransition
ransition Times and TTransition
ransition Time Matc
hing Measurement Def
inition
Driver
Matching
Definition
OUT
1 / Fmax
OUT(H)
0.90 OUT(H)
Time
0.0V
Figure 7
er Fmax Measurement Def
inition
7.. Driv
Driver
Definition
© 2006 Semtech Corp. , Rev. 11, 7/18/06
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E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
OUT
overshoot
V2
V1
ringback
ringback
0.0V
undershoot
Test Cases: V1:V2 = DVL:DVH = DVT:DVH = DVL:DVT
Figure 8. Driv
er Ov
er
shoo
t, U
nder
shoo
t, and Ringbac
k
Driver
Over
ershoo
shoot,
Under
ndershoo
shoot,
Ringback
DVH to DVL
800 mV
XOVER
0V
DVL to DVH
Figure 9. Driv
er Output Cr
osso
oltage Measurement
Driver
Crosso
ossovver V
Voltage
© 2006 Semtech Corp. , Rev. 11, 7/18/06
23
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E7765
TEST AND MEASUREMENT PRODUCTS
Ordering Information
Model Number
P ackag e
E 7765A X F
14 x 14 x 1.4mm, 80-Pin LQFP
with Exposed Heat Slug
EVM7765AXF
Edge7765 Evaluation Board
Contact Information
Semtech Corporation
Test and Measurement Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
© 2006 Semtech Corp. , Rev. 11, 7/18/06
24
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