TI UCC38500N

 SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
FEATURES
D Combines PFC and Downstream Converter
D
D
D
D
D
D
D
D
D
Controls
Controls Boost Preregulator to Near-Unity
Power Factor
Accurate Power Limiting
Improved Feedforward Line Regulation
Peak Current-Mode Control in Second Stage
Programmable Oscillator
Leading-Edge/Trailing-Edge Modulation for
Reduced Output Ripple
Low Start-up Supply Current
Synchronized Second Stage Start-Up, with
Programmable Soft-start
Programmable Second Stage Shutdown
DESCRIPTION
The UCC2850x family provides all of the control
functions necessary for an active power-factorcorrected preregulator and a second-stage dc-to- dc
converter. The controller achieves near-unity power
factor by shaping the ac input line current waveform to
correspond to the ac input-line voltage using average
current-mode control. The dc-to-dc converter uses
peak current-mode control to perform the step-down
power conversion.
The PFC stage is leading-edge modulated while the
second stage is trailing-edge synchronized to allow for
minimum overlap between the boost and PWM
switches. This reduces ripple current in the bulk-output
capacitor.In order to operate with over three-to-one
range of input-line voltages, a line feedforward (VFF) is
used to keep input power constant with varying input
voltage. Generation of VFF is accomplished using IAC in
conjunction with an external single-pole filter. This not
only reduces external parts count, but also avoids the
use of high-voltage components, offering a lower-cost
solution. The multiplier then divides the line current by
the square of VFF.
The UCC2850x PFC section incorporates a low
offset-voltage amplifier with 7.5-V reference, a
highly-linear multiplier capable of a wide current range,
a high-bandwidth, low offset-current amplifier, with a
novel
noise-attenuation
configuration,
PWM
comparator and latch, and a high-current output driver.
Additional PFC features include over-voltage
protection, zero-power detection to turn off the output
when VAOUT is below 0.33 V and peak current and
power limiting.
The dc-to-dc section relies on an error signal generated
on the secondary-side and processes it by performing
peak current mode control. The dc-to-dc section also
features current limiting, a controlled soft-start, preset
operating range with selectable options, and 50%
maximum duty cycle.
The UCC28500 and UCC28502 have a wide UVLO
threshold (16.5 V/10 V) for bootstrap bias supply
operation. The UCC28501 and UCC28503 are
designed with a narrow UVLO range (10.5 V/10 V) more
suitable for fixed bias operation. The UCC28500 and
UCC28501 have a narrow UVLO threshold for PWM
stage (to allow operation down to 75% of nominal bulk
voltage), while the UCC28502 and UCC38503 are
configured for a much wider operation range for the
PWM stage (down to 50% of bulk nominal voltage).
Available in 20-pin N and DW packages.
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Copyright  2001, Texas Instruments Incorporated
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1
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Gate Drive Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 A
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 A
Input Voltage
ISENSE1, ISENSE2, MOUT, VSENSE, OVP/ENBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V
CAI, MOUT, CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
PKLMT, VERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V
Input Current
RSET, RT, IAC, PKLMT, ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
VCC (no switching) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Maximum Negative Voltage GT1, GT2, PKLMT, MOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Storage temperature Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Junction temperature TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Lead temperature (soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and
considerations of packages. All voltages are referenced to GND.
AVAILABLE OPTIONS
PFC THRESHOLD
TJ
–40°C to 85°C
0°C to 70°C
PACKAGED DEVICES
UVLO TURN−ON
THRESHOLD (V)
UVLO2
HYSTERESIS
(V)
PLASTIC DIP
(N)
SMALL OUTLINE
(DW)
16
1.2
UCC28500N
UCC28500DW
10.5
1.2
UCC28501N
UCC28501DW
16
3.0
UCC28502N
UCC28502DW
10.5
3.0
UCC28503N
UCC28503DW
16
1.2
UCC38500N
UCC38500DW
10.5
1.2
UCC38501N
UCC38501DW
16
3.0
UCC38502N
UCC38502DW
10.5
3.0
UCC38503N
UCC38503DW
The DW package is available taped and reeled. Add TR suffix to device type (e.g. UCC38500DWTR)
to order quantities of 2000 devices per reel.
N PACKAGE
(TOP VIEW)
VAOUT
RT
VSENSE
OVP/ENBL
CT
GND
VERR
ISENSE2
VCC
GT2
2
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
DW PACKAGE
(TOP VIEW)
VREF
VFF
IAC
MOUT
ISENSE1
CAOUT
PKLMT
SS2
GT1
PWRGND
VAOUT
RT
VSENSE
OVP/ENBL
CT
GND
VERR
ISENSE2
VCC
GT2
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1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VREF
VFF
IAC
MOUT
ISENSE1
CAOUT
PKLMT
SS2
GT1
PWRGND
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
electrical characteristics TA = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X,
TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted)
supply current
PARAMETER
TEST CONDITIONS
Supply current, off
VCC turn-on threshold –300 mV
Supply current, on
VCC = 12 V (no load on GT1 or GT2)
MIN
TYP
MAX
UNITS
150
300
µA
4
6
mA
undervoltage lockout
PARAMETER
TEST CONDITIONS
VCC turn-on threshold (UCCx8500/502)
MIN
15.4
UVLO hysteresis (UCCx8500/502)
TYP
MAX
16
UNITS
16.6
V
5.8
6.3
15.4
16.2
17.0
V
VCC turn-on threshold (UCCx8501/503)
9.7
10.2
10.8
V
VCC turn-off threshold
9.4
9.7
V
UVLO hysteresis (UCCx8501/503)
0.3
0.5
V
Shunt voltage (UCCx8500/502)
IVCC = 10 mA
V
voltage amplifier
PARAMETER
TEST CONDITIONS
0°C ≤ TA ≤ 70°C
Input voltage
–40°C ≤ TA ≤ 85°C
VSENSE bias current
Open loop gain
High-level output voltage
Low-level output voltage
MIN
TYP
MAX
UNITS
7.387
7.500
7.613
7.35
7.50
7.65
V
50
200
nA
V
VAOUT = 2 V to 5 V
50
90
ILOAD = –150 µA
ILOAD = 150 µA
5.3
5.5
5.6
dB
V
0.00
0.05
0.15
V
PFC overvoltage protection and enable
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VREF
+ 0.480
VREF
+ 0.500
VREF
+ 0.520
V
Hysteresis
300
500
600
mV
Enable threshold
1.7
1.9
2.1
V
Enable hysteresis
0.1
0.2
0.3
V
Over voltage reference
current amplifier
PARAMETER
Input offset voltage
Input bias current
Input offset current
Open loop gain
Common−mode rejection ratio
High-level output voltage
Low-level output voltage
Gain bandwidth product
TEST CONDITIONS
VCM = 0 V,
VCM = 0 V,
VCAOUT = 3 V
VCAOUT = 3 V
VCM = 0 V,
VCM = 0 V,
VCAOUT = 3 V
VCAOUT = 2 V to 5 V
VCM = 0 V to 1.5 V, VCAOUT = 3 V
ILOAD = –120 µA
ILOAD = 1 mA
See Note 1
MIN
–6
TYP
MAX
UNITS
0
6
mV
−50
−100
nA
25
100
nA
90
dB
90
dB
5.6
7.0
7.5
0.1
0.2
0.5
2.5
V
V
MHz
NOTES: 1. Ensured by design. Not production tested.
2. See Figure 6 for reference variation.
3. See Figure 5 for reference variation for VCC < 10.8 V.
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3
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
electrical characteristics TA = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X,
TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted)
voltage reference
PARAMETER
TEST CONDITIONS
TA = 0°C to 70°C
TA = –40°C to 85°C
Input voltage
Load regulation
Line regulation
IREF = −1 mA to −2 mA,
VCC = 10.8 V to 15 V,
Short circuit current
VREF = 0V
MIN
TYP
MAX
UNITS
7.387
7.500
7.613
V
7.35
7.50
7.65
V
See Note 2
0
10
mV
See Note 3
0
10
mV
−50
mA
−20
–25
oscillator
PARAMETER
Frequency, initial accuracy
TEST CONDITIONS
Frequency, voltage stability
TA = 25°C
VCC = 10.8 V to 15 V
Frequency, total variation
Line, Temp
MIN
TYP
85
MAX
100
115
UNITS
kHz
−1%
1%
80
120
kHz
Ramp peak voltage
4.5
5
5.5
V
Ramp amplitude voltage (peak to peak)
3.5
4
4.5
V
peak current limit
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PKLMT reference voltage
–15
0
15
mV
PKLMT propagation delay
150
300
500
ns
multiplier
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IMOUT, high-line low-power output current
IAC = 500 µA, VFF = 4.7 V,
0°C ≤ TA ≤ 85°C
VAOUT = 1.25 V,
IMOUT, high-line low-power output current
IAC = 500 µA, VFF = 4.7 V,
–40°C ≤ TA ≤ 85°C
VAOUT = 1.25 V,
IMOUT, high-line high-power output current
IMOUT, low-line low-power output current
IAC = 500 µA, VFF = 4.7 V,
IAC = 150 µA, VFF = 1.4 V,
VAOUT = 5 V
−10
–19
−50
IMOUT, low-line high-power output current
IMOUT, IAC-limited output current
IAC = 150 µA, VFF = 1.4 V,
IAC = 150 µA, VFF = 1.3 V,
VAOUT = 5 V
−268
–300
−345
VAOUT = 5 V
−250
–300
−400
Gain constant (K)
IAC = 300 µA, VFF = 2.8 V,
IAC = 150 µA, VFF = 1.4 V,
VAOUT = 2.5 V
0.5
1
1.5
VAOUT = 0.25 V
0
–2
IAC = 500 µA, VFF = 4.7 V,
IAC = 500 µA, VFF = 4.7 V,
0°C ≤ TA ≤ 85°C
VAOUT = 0.25 V
0
–2
µA
0
–3
µA
IAC = 500 µA, VFF = 4.7 V,
−40°C ≤ TA ≤ 85°C
VAOUT = 0.5 V,
0
–3.5
µA
IAC = 150 µA, VFF = 1.4 V,
VAOUT = 5 V
–420
−485
µW
IMOUT, zero current
Power limit (IMOUT × VFF)
VAOUT = 1.25 V
0
–6
−20
0
–6
−23
−70
–90
−105
VAOUT = 0.5 V,
−375
µA
A
1/V
zero power
PARAMETER
Zero power comparator threshold
TEST CONDITIONS
Measured on VAOUT
NOTES: 1. Ensured by design. Not production tested.
2. See Figure 6 for reference variation.
3. See Figure 5 for reference variation for VCC < 10.8 V .
4
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MIN
0.175
TYP
0.330
MAX
0.500
UNITS
V
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
electrical characteristics TA = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X,
TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted)
PFC gate driver
PARAMETER
GT1 pull up resistance
GT1 pull down resistance
GT1 output rise time
GT1 output fall time
TEST CONDITIONS
TYP
CLOAD = 1 nF,
VGT1 from 0.7 V to 9.0 V
CLOAD = 1 nF,
VGT1 from 9.0 V to 0.7 V
MAX
UNITS
5
12
Ω
2
10
Ω
RLOAD = 10 Ω
25
50
ns
RLOAD = 10 Ω
10
50
ns
95%
100%
IOUT from −100 mA to –200 mA
IOUT = 100 mA
Maximum duty cycle
Minimum controlled duty cycle
MIN
93%
f = 100 kHZ
2%
second stage undervoltage lockout (UVLO2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM turn-on reference (UCCx8500/501)
6.30
6.75
7.30
V
Hysteresis (UCCx8500/501)
0.96
1.20
1.44
V
PWM turn−on reference (UCCx8502/503)
6.30
6.75
7.30
V
2.4
3
3.6
V
Hysteresis (UCCx8502/503)
second stage soft-start
PARAMETER
TEST CONDITIONS
SS2 charge current
Input voltage (VERR)
SS2 discharge current
MIN
TYP
–7.3
IVERR = 2 mA,UVLO = Low
ENBL = High, UVLO = Low, SS2 = 2.5 V
MAX
–10
3
UNITS
–12.5
µA
300
mV
10
mA
second stage duty cycle clamp
PARAMETER
TEST CONDITIONS
Maximum duty cycle
MIN
TYP
MAX
44%
UNITS
50%
second stage pulse-by-pulse current sense
PARAMETER
Current sense comparator threshold
TEST CONDITIONS
VERR = 2.5 V measured on ISENSE2
MIN
0.94
TYP
MAX
1.05
1.15
UNITS
V
second stage overcurrent limit
PARAMETER
TEST CONDITIONS
Peak current comparator threshold
MIN
1.15
Input bias current
TYP
MAX
1.30
1.45
50
UNITS
V
nA
second stage gate driver
PARAMETER
GT2 pull up resistance
GT2 pull down resistance
TEST CONDITIONS
IOUT from −100 mA to –200 mA
IOUT = 100 mA
CLOAD = 1 nF,RLOAD = 10 Ω
VGT2 from 0.7 V to 9.0 V
GT2 output fall time
CLOAD = 1 nF,RLOAD = 10 Ω
VGT2 from 9.0 V to 0.7 V
NOTES: 1. Ensured by design. Not production tested.
2. See Figure 6 for reference variation.
3. See Figure 5 for reference variation for VCC < 10.8 V .
GT2 output rise time
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MIN
TYP
MAX
UNITS
Ω
5
12
3
10
Ω
25
50
ns
25
50
ns
5
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
pin assignments
CAOUT: (current amplifier output) This is the output of a wide bandwidth operational amplifier that senses line
current and commands the PFC pulse width modulator (PWM) to force the correct duty cycle. This output can
swing close to GND, allowing the PWM to force zero duty cycle when necessary.
CT: (oscillator timing capacitor) A capacitor from CT to GND sets the oscillator frequency according to:
f+
0.725
ǒRT
C
T
Ǔ
GND: (ground) All voltages measured with respect to ground. VCC and VREF should be bypassed directly to
GND with a 0.1-µF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin,
so the lead from the oscillator timing capacitor to GND should be as short and direct as possible.
GT1: (gate drive) The output drive for the PFC stage is a totem pole MOSFET gate driver on GT1. Use a series
gate resistor of at least 10.5 Ω to prevent interaction between the gate impedance and the GT1 output driver
that might cause the GT1 to overshoot excessively. Some overshoot of the GT1 output is always expected when
driving a capacitive load. Refer to Figure 4 for gate drive resistor selections.
GT2: (gate drive) Same as output GT1 for the second stage output drive. Limited to 50% maximum duty cycle.
IAC: (input ac current) This input to the analog multiplier is a current. The multiplier is tailored for very low
distortion from this current input (IAC) to MOUT, so this is the only multiplier input which should be used for
sensing instantaneous line voltage. Recommended maximum IAC is 500 µA.
ISENSE1: (current sense) This is the non-inverting input to the current amplifier. This input and the inverting
input MOUT remain functional down to and below GND.
ISENSE2: (current sense) A resistor from the source of the lower FET to ground generates the input signal for
the peak limit control of the second stage. The oscillator ramp can also be summed into this pin, for slope
compensation.
MOUT: (multiplier output and current sense amplifier inverting input) The output of the analog multiplier and the
inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this
is a high impedance input so the amplifier can be configured as a differential amplifier to reject ground noise.
Multiplier output current is given by:
I
MOUT
+
ǒVVAOUT * 1.0Ǔ
K
ǒVVFFǓ
I
IAC
2
Connect current loop compensation components between MOUT and CAOUT.
OVP/ENBL: (over-voltage/enable) A window comparator input which disables the PFC output driver if the boost
output is 6.67% above nominal or disables both the PFC and second stage output drivers and reset SS2 if pulled
below 1.9 V. This input is also used to determine the active range of the second stage PWM.
PKLMT: (PFC peak current limit) The threshold for peak limit is 0 V. Use a resistor divider from the negative side
of the current sense resistor to VREF to level-shift this signal to a voltage corresponding to the desired
overcurrent threshold across the current sense resistor.
PWRGND: Ground for totem pole output drivers.
RT: (oscillator charging current) A resistor from RT to GND is used to program oscillator charging current. A
resistor between 10 kΩ and 100 kΩ is recommended. Nominal voltage on this pin is 3 V.
6
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
pin assignments (continued)
SS2: (soft-start for PWM) SS2 is at ground for either enable low or OVP/ENBL below the UVLO2 threshold
conditions. When enabled, SS2 charges an external capacitor with a current source. This voltage is used as
the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a disable
command or a UVLO2 dropout, SS2 quickly discharges to disable the PWM.
VAOUT: (voltage amplifier output) This is the output of the operational amplifier that regulates output voltage.
The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot.
VCC: (positive supply voltage) Connect to a stable source of at least 20 mA between 12 V and 17 V for normal
operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET
gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless VCC
exceeds the upper under-voltage lockout threshold and remains above the lower threshold.
VERR: (voltage amp error signal for the second stage) The error signal is generated by an external amplifier
which drives this pin. This pin has an internal 4.5-V voltage clamp that limits GT2 to less than 50% duty cycle
to ensure transformer reset in the typical application.
VFF: (RMS feed forward signal) VFF signal is generated at this pin by mirroring one-half of IAC into a single pole
external filter. At low line, the VFF voltage should be 1.4 V.
VSENSE: (voltage amplifier inverting input) This is normally connected to a compensation network and to the
boost converter output through a divider network.
VREF: (voltage reference output) VREF is the output of an accurate 7.5-V voltage reference. This output is
capable of delivering 10 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled
and remains at 0 V when VCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger
ceramic capacitor for best stability.
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7
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
block diagram
VERR
ISENSE2
7
8
SS2
VCC
GND
9
6
13
7.5 V
REFERENCE
SECOND STAGE
SOFT START
OVP/ENBL
+
4
1.9 V
ILIMIT
4.5 V
1.5 V
R
R
+
1.3 V
PWM
+
8.0 V
+
3
0.33 V
÷
MULT
OSC
CLK1
X
+
Q
PWM
LATCH
R
R
CLK2
(VFF )2
CLK2
12
GT1
11
PWRGND
14
PKLMT
CLK1
OSCILLATOR
ILIMIT
+
18
17
16
MOUT ISENSE1
8
PWM 2ND STAGE
SECTION
S
+
MIRROR
2:1
IAC
S
PFC SECTION
CURRENT
AMP
7.5 V
19
GT2
Q
VCC
PWM
+
X
+
VFF
10
VCC
PFCOVP
ZERO
POWER
1
VOLTAGE
ERROR AMP
VSENSE
VREF
CLK2
PWM 2ND STAGE
SECTION
PFC SECTION
UVLO
16 V/10 V
10.5 V/10 V
ENABLE
+
VAOUT
20
UVLO2
6.75 V
15
2
5
CAOUT
RT
CT
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UDG−98189
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL CHARACTERISTICS
MULTIPLIER OUTPUT CURRENT
vs.
VOLTAGE ERROR AMPLIFIER OUTPUT
MULTIPLIER GAIN
vs.
VOLTAGE ERROR AMPLIFIER OUTPUT
1.5
300
1.3
IAC = 150 µ A
IAC = 150 µ A
250
Multiplier Gain − K
IMOUT - Multiplier Output Current − µA
350
200
IAC = 300 µ A
150
100
1.1
0.9
IAC = 300 µ A
IAC = 500 µ A
0.7
50
IAC = 500 µ A
0.5
0
0
1
2
3
4
1
5
2
Figure 1
(VFF × IMOUT) − µW
400
VAOUT = 5 V
300
VAOUT = 4 V
200
VAOUT = 3 V
100
VAOUT = 2 V
0
3
4
5
RGATE - Recommended Minimum Gate Resistance − Ω
500
2
5
Figure 2
MULTIPLIER CONSTANT POWER PERFORMANCE
1
4
VAOUT − Voltage Error Amplifier Output − V
VAOUT − Voltage Error Amplifier Output − V
0
3
RECOMMENDED MINIMUM GATE RESISTANCE
vs.
SUPPLY VOLTAGE
17
16
15
14
13
12
11
10
9
8
10
12
14
16
18
20
VCC − Supply Voltage − V
VFF − Feedforward Voltage − V
Figure 3
Figure 4
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9
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
REFERENCE VOLTAGE
vs.
REFERENCE CURRENT
REFERENCE VOLTAGE
vs.
SUPPLY VOLTAGE
7.510
VREF − Reference Voltage − V
VREF − Reference Voltage − V
7.60
7.55
7.50
7.45
7.505
7.500
7.495
7.490
7.40
9
10
11
12
13
14
5
10
15
20
IVREF − Reference Current − mA
VCC − Supply Voltage − V
Figure 5
10
0
Figure 6
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25
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
The UCC38500 series is designed to incorporate all the control functions required for a power factor correction
circuit and a second stage dc-to-dc converter. The PFC function is implemented as a full-feature,
average-current-mode controller integrated circuit. In addition, the input voltage feedforward function is
implemented in a simplified manner. Current from IAC input is mirrored over to the VFF pin. By simply adding
a resistor and capacitor (to attenuate 120-Hz ripple) a voltage is developed which is proportional to RMS line
voltage, eliminating the need for several components normally connected to the line.
The UCC3850x uses leading-edge modulation for the PFC stage and trailing-edge modulation for the dc-to-dc
stage. This reduces ripple current in the output capacitor by reducing the overlap in conduction time of the PFC
and dc-to-dc switches. Figures 7 and 8 depict the ripple current reduction in the boost switch. In addition to the
reduced ripple current, noise immunity is improved through the current error amplifier implementation. Please
refer to the UCC3817 datasheet (TI Literature No. SLUS395) for a detailed explanation of current error amplifier
implementation.
UDG−97130−1
Figure 7. Simplified Representation of a 2−Stage PFC Power Supply
iCBST
iCBST = iD1 − iQ2
Figure 8. Timing Waveforms for Synchronization Scheme
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11
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
The UCC3850x is optimized to control a boost PFC stage operating in continuous conduction mode, followed
by a dc-to-dc converter (typically a forward topology). The dc-to-dc converter is transformer isolated and
therefore its error amplifier is located on the secondary side. For this reason the UCC3850x is configured without
an internal error amplifier for the second power stage. The externally generated error signal is fed into the VERR
pin typically through an opto coupler.
The UCC3850x can be configured for voltage-mode control or current-mode control of the second stage. The
application figure shows a typical current-mode configuration. For voltage-mode control, the ramp generated
by CT can be fed back into the ISENSE2 pin through a voltage divider.
One of the main system challenges in designing systems with a PFC front end is coordinating the turn-on and
turn-off on the dc-to-dc converter. If the dc-to-dc converter is allowed to turn on before the boost converter is
operational, it must operate at a much-reduced voltage and therefore represents a large current draw to the
boost converter. This start-up sequencing is handled internally by the UCC3850x. The UCC3850x monitors the
output voltage of the PFC converter and holds the dc-to-dc converter off until the output is within 10% of its
regulation point. Once the trip point is reached the dc-to-dc section goes through a soft start sequence for a
controlled, low stress start-up. Similarly, if the output voltage drops too low (two voltage options are available)
the dc-to-dc converter shuts down thereby preventing overstress of the converter. For the UCC38500 and
UCC38501, the dc-to-dc converter shuts down when the PFC output falls below 74% of its nominal value, while
for the UCC38502 and UCC38503, the threshold is lowered to 50%.
design example: an off-line, 100-W, power converter
The following design example shows how to implement the UCC38500 in an off-line 100-W power converter.
The system requires the converter to operate from a universal input of 85 VRMS to 265 VRMS with a 12-V, 100-W,
dc output. This design example is divided into two parts. The first part is the PFC stage design and the second
section is the dc-to-dc power stage design. The design goal of the system is to achieve an efficiency of
approximately 80%. This is accomplished by requiring the boost regulator to be designed for an efficiency of
95% and the dc-to-dc power stage to be designed for 85% efficiency. The efficiency of the boost converter is
designated by variable η1 and the efficiency of the dc-to-dc converter is designated by variable η2. Figure 9
shows the schematic of the typical application upon which this design example is based. The UCC38500 control
device is chosen for this design because of it’s self-biasing scheme and minimum input voltage requirements
of the dc-to-dc power stage.
12
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AC−N
AC−L
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D15
R3
L1
VCCBIAS
CIRCUIT
C26
VAC
85−265V RMS
Q5
D7
R39
D11
D5
R24
R18
VCC BIAS
CIRCUIT
C20
C12
D12
C22
R10
R29
PKLIMIT
R14
VREF
R19
R5
GT1
L1
D1
C19
R17
R15
C6
R21
R20
SGND
R30
C27
VREF
20 VREF
GND
RT
6
2
5
ISENSE2
VERR
8
7
SS2 13
PWRGND 11
14 PKLIMIT
19 VFF
18 IAC
15 CAOUT
17 MOUT
CT
16 ISENSE
9
GT2 10
GT1 12
T2
VCC
VSENSE
OVP/ENBL
UCC38500
U1
C5
VAOUT
1
3
4
PWR
GND
SGND
D16
PKLIMIT
R28
C23
R34
R23
R33
R22
C25
C28
C2
VCC
C24
PGND
Q3
D3
GT2
D4
D2
R1
C21
SGND
C13
SGND
R38
ISENSE2
4
5
6
R13
U3
3
C29
D10
R16
R36
C30
D14
Q5
GT2
GT1
PGND2
R35
C15
PGND2
C14
R7
ISENSE2
PGND
L2
PGND2
D13
2
1
PGND
D9
R6
PGND
C7
R11
D8
PGND
C3
H11AV1
C18
VCC
PGND
R4
R12
T1
Q2
Q1
SGND
R2
VREF
D6
GT2
C17
C16
PGND
R25
C4
Vout −
12V
10A
R27
R31
−
+
Vout +
C8
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
UDG−99138
Figure 9. Typical Application Circuit
13
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
I. PFC Boost Power Stage
LBOOST (L1 in Figure 9)
The boost inductor value is determined by the following equations:
P
DI +
ǒ0.25Ǔ
OUT
h1 h2
D+1*
Ǹ2
,
V IN (min)
(1)
Ǹ2
V IN (min)
L BOOST +
V BOOST
,
(2)
V IN (min)
Ǹ2
DI
fS
D
(3)
where ∆I, the inductor current ripple was set to approximately 25% of the peak inductor current.
In this design example ∆I is approximately 505 mA. D represents the duty cycle at the peak of low line voltage,
VIN(min) is the minimum RMS input voltage, and VBOOST is the controlled output voltage of the PFC stage.
VBOOST for this design is selected to be 385 V to ensure the PFC stage regulates for the full input voltage range.
Variable fS represent the switching frequency. The switching frequency was selected to be 100 kHz for this
design. The calculated boost inductor required for this design is approximately 1.7 mH.
CBOOST (C2 in Figure 9)
Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. The value
of capacitance is determined by the holdup time required for supporting the load after the input ac voltage is
removed. Holdup is the amount of time that the output stays in regulation after the input has been removed. For
this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output
power, output voltage, and holdup time is described in equation (4):
C BOOST +
2
P OUT
Dt
ǒVBOOSTǓ 2 * ǒVBOOST (min)Ǔ 2
(4)
In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage
specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often
necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR
allowed is determined by dividing the maximum specified output ripple voltage by the capacitor ripple current.
In this design, holdup time is the dominant determining factor and a 100 µF, 450 V aluminum electrolytic
capacitor from Panasonic, part number ECOS2TB101BA, is used. The voltage rating and the low ESR of
0.663 Ω make it an ideal choice for this design.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
power switch selection (Q3 in Figure 9)
As in any power supply design, tradeoffs between performance, cost and size are necessary. When selecting
a power switch, it is useful to calculate the total power dissipation in the switch for several different devices at
the switching frequencies being considered for the converter. Total power dissipation in the switch is the sum
of switching loss and conduction loss. Switching losses are the combination of the gate charge loss, drain
source capacitance of the MOSFET loss and turnon and turnoff losses:
P GATE + Q GATE
V GATE
P COSS + 1 C OSS ǒV OFFǓ
2
P SW + 1 V OFF
2
2
fS
(5)
fS
(6)
ǒt ON ) tOFFǓ
IL
fS
(7)
Where QGATE is the total gate charge, VGATE is the gate drive voltage, fs is the switching frequency, COSS is
the drain source capacitance of the MOSFET, tON and tOFF are the switching times (estimated using device
parameters RGATE, QGD and VTH) and VOFF is the voltage across the switch during the off time, in this case VOFF
= VBOOST.
Conduction loss is calculated as the product of the RDS(on) of the switch (at the worst case junction temperature)
and the square of RMS current:
P COND + R DS(on)
K
ǒI RMSǓ
2
(8)
where K is the temperature factor found in the manufacturer’s RDS(on) vs junction temperature curves.
Calculating these losses and plotting against frequency gives a curve that enables the designer to determine
either which manufacturer’s device has the best performance at the desired switching frequency, or which
switching frequency has the least total loss for a particular power switch. For this design example an IRFP450
HEXFET from International Rectifier is chosen because of its low RDS(on) and its VDSS rating. The IRFP450’s
RDS(on) of 400 mΩ and the maximum VDSS of 500 V makes it an ideal choice. A comprehensive review of this
procedure can be found in the Unitrode Power Supply Design Seminar SEM−1200, Topic 6, TI Literature No.
SLUP117.
More recently, faster switching insulated gate bipolar transistors (IGBTs) have become widely available.
Depending on the system power level (and the switching frequency), use of IGBTs may make sense for the
power switch.
boost diode selection (D3 in Figure 9)
In order to keep the switching losses to a minimum and meet the voltage and current requirements, a
HFA08TB60 fast recovery diode from International Rectifier is selected for the design. This diode is rated for
a maximum reverse voltage of 600 V and a maximum forward current of 8 A. The typical reverse recovery of
18 ns made this diode ideal for this design.
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15
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
peak current limit
Resistor divider R14 and R29 along with current sense resistor R5, devise the peak-limit comparator of the
UCC38500 and are used to protect the boost switch Q3 from excessive currents. Proper preparation of this
comparator requires that it not interfere with the boost converter’s power limit or the forward converter’s
pulse-by-pulse current limiting. For this design example the forward converter is selected to go into
pulse-by-pulse current limiting at approximately 130% of maximum output power. The power limit of the boost
converter is set at 140% of the maximum output power. The peak current limit for the boost stage was selected
to engage at 150% of the maximum output power to ensure circuit stability.
The following equation is used to select the current-sense resistor R5, where the current-sense resistor is
selected to operate over a 1-V dynamic range (VDYNAMIC). The current-sense resistor required for the design
needed to be approximately 0.43 Ω.
R5 + R SENSE +
V DYNAMIC
^ 0.43 W
I PK ) (0.5) DI
(9)
The following equation is used to size resistor R14 properly by first selecting R29 to be a standard resistance
value. For this design resistor R29 was selected to be 10 kΩ. With a typical reference voltage (VREF) of 7.5 V
gives a calculated value of approximately 1.91 kΩ for resistor R14.
R14 +
ǒ
Ǔ
P OUT 1.5 Ǹ2
) DI
V IN (min) h1 h2
R5
R29
V REF
(10)
multiplier
The output of the multiplier of the UCC38500 is a signal representing the desired input line current. It is an input
to the current amplifier, which programs the current loop to control the input current to give high power-factor
operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the
multiplier are VVAOUT, the voltage amplifier output, IIAC, a representation of the input rectified ac line voltage,
and an input voltage feed forward signal, VVFF. The output of the multiplier, IMOUT, can be expressed:
I MOUT +
ǒVVAOUT * 1Ǔ
I IAC
K
ǒVVFFǓ
2
(11)
Where K is a constant typically equal to 1 / V.
The IIAC signal is obtained through a high-value resistor connected between the rectified ac line and the IAC
pin of the UCC3850X. This resistor (RIAC) is sized to provide the maximum IIAC current at high line. For the
UCC3850X the maximum IIAC current is about 500 µA, and a higher current can drive the multiplier out of its
linear range. A smaller current level is functional, but noise can become an issue, especially at low input line.
Assuming a universal line operation of 85 VRMS to 265 VRMS gives a RIAC value of 750 kΩ. Because of voltage
rating constraints of the standard 1/4-W resistor, this application requires a combination of lower value resistors
connected in series to give the required resistance and distribute the high voltage amongst the resistors. For
this design example two 383 kΩ resistors are used in series.
16
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed
forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant and
to providing input power limiting. Please refer to Texas instruments Application Note on Power Limiting with
Sinusoidal Input TI Literature No. SLUA196, for detailed explanation on how the VFF pin provides power
limiting. The following equation is used to determine the VFF resistor size (RVFF) to provide power limiting where
VIN(min) is the minimum RMS input voltage and RIAC is the total resistance connected between the IAC pin and
the rectified line voltage.
R VFF +
ǒ
1.4 V
Ǔ
V IN (min) 0.9
2 R IAC
^ 28.7 kW
(12)
Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total
harmonic distortion caused by the 120-Hz rectified line voltage. Refer to Unitrode Power Supply Design
Seminar, SEM−700 Topic 7, Optimizing a High Power Factor Switching Preregulator, TI Literature No.
SLUP093. A single pole filter is adequate for this design. Assuming that an allocation of 1.5% total harmonic
distortion from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the
amount of attenuation required by this filter is:
1.5% + 0.022
66%
(13)
With a ripple frequency (fR) of 120-Hz and an attenuation of 0.022 requires that the pole of the filter (fP) be placed
at:
f P + 120 Hz
0.022 ^ 2.6 Hz
(14)
The following equation is used to select the filter capacitor (CVFF) required to produce the desired low pass filter.
C VFF +
2p
1
R VFF
fP
^ 2.2 mF
(15)
This results in a single-pole filter, which adequately attenuates the harmonic distortion and provides power
limiting.
The RMOUT resistor is sized to provide power limiting for the circuit. The power limit is set to 140% of the
maximum output power. This is done so that the power limit of the PFC stage does not interfere with power
limiting of the dc-to-dc converter, which is set to 130% of the maximum output power. The following equations
are used to size the RMOUT resistor, R19. In these equations PLIMIT is the power limit level, POUT is the maximum
output power. IMOUT(max) is the maximum multiplier output current, [email protected](min) is the minimum current into
the IAC pin at low line and VVAOUT(max) is the maximum voltage amplifier output voltage. For this design R19
and R15 need to be approximately 3.57 kΩ.
P LIMIT +
P OUT 1.4
h1 h2
I MOUT(max) +
(16)
I IAC @ V IN(min)
K
ǒVVAOUT(max) * 1 VǓ
ǒVFFǓ
2
(17)
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17
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
R MOUT +
P LIMIT Ǹ2 R SENSE
V IN (min)
I MOUT(max)
(18)
current loop
The UCC38500 current amplifier has the input from the multiplier applied to the inverting input. This change in
architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier.
It also adds a phase inversion into the control loop. The UCC38500 takes advantage of this phase inversion
to implement leading-edge duty cycle modulation. Please refer to Figure 10 for the typical configuration of the
current amplifier.
The following equation defines the gain of the power stage, where VP is the voltage swing of the oscillator ramp,
4 V for the UCC38500.
G ID(s) +
V BOOST R SENSE
s L BOOST V P
(19)
In order to have a good dynamic response the crossover frequency of the current loop was set to 10% of the
switching frequency. This can be achieved by setting the gain of the current amplifier (GCA) to the inverse of
the current loop power stage gain at the crossover frequency. This design requires that the current amplifier
have a gain of 2.581 at 10 kHz.
G CA +
1 + 2.581
G ID(s)
(20)
RI is the RMOUT resistor, previously calculated to be 3.57 kΩ (refer to Figure 10). The gain of the current amplifier
is RF/RI, so multiplying RI by GEA gives the value of RF, in this case approximately 9.09 kΩ. Setting a zero at
the crossover frequency and a pole at half the switching frequency to roll off the high-frequency gain completes
the current loop compensation.
CZ +
2p
1
CP +
2p
18
1
RF
RF
fC
(21)
ǒf2 Ǔ
s
(22)
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
C
P
C
Rf
Z
RI
−
CAOUT
+
Figure 10. Current Loop Compensation
voltage loop
The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic
of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple
at the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate
the contribution of this ripple to the total harmonic distortion of the system (refer to Figure 11).
Cf
VOUT
CZ
Rf
R IN
−
+
RD
VREF
Figure 11. Voltage Amplifier Configuration
The gain of the voltage amplifier, GVA, can be determined by first calculating the amount of peak ripple present
on the output capacitor VOPK. The peak value of the second harmonic voltage is given by equation (23), where
fR is the frequency of the rectified line voltage. For this design fR is equal to 120 Hz.
V OPK +
ǒ2 p
P IN
fR
C BOOST
V BOOSTǓ
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(23)
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
In this example VOPK is equal to 4 V. Assuming an allowable contribution of 0.75% (1.5% peak-to-peak) from
the voltage loop to the total harmonic distortion budget sets the gain equal to:
G VA +
ǒDVVAOUTǓ (0.015)
2
V OPK
(24)
Where ∆VVAOUT is the effective output voltage range of the error amplifier (5 V for the UCC38500). The network
needed to realize this filter is comprised of an input resistor, RIN, and feedback components CF, CZ, and RF. The
value of RIN is already determined because of its function as one-half of a resistor divider from VOUT feeding
back to the voltage amplifier for output voltage regulation. In this case the value is 1.12 MΩ. This high value was
chosen to reduce power dissipation in the resistor. In practice, the resistor value would be realized by the use
of two 560-kΩ resistors in series because of the voltage rating constraints of most standard 1/4 W resistors. The
value of CF is determined by the equation:
C +
F
ǒ2 p
1
f
R
G
VA
R
Ǔ
IN
(25)
In this example CF equals 150 nF. Resistor RF and CF generate a pole in the voltage amplifier feedback to reduce
total harmonic distortion (THD). The location of the pole is found by setting the gain of the loop equation to one
and solving for the crossover frequency. The frequency, expressed in terms of input power, is calculated by the
equation:
f VI +
ǸPIN
2p ǸDV VAOUT
V OUT
R IN
C BOOST
CF
(26)
fVI for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design
Seminar SEM−1000, Topic 1, Power Factor Correction Circuit, TI Literature No. SLUP106.
Solving for RF becomes:
R +
F
ǒ2 p
1
f
VI
C
F
Ǔ
(27)
Or RF equals approximately 118 kΩ.
Due to the low output impedance of the voltage amplifier, capacitor CZ is added to improve dc regulation. To
maintain good phase margin, the zero from CZ is set to 10% of fVI. For this design, CZ is a 2.2-µF capacitor. The
following equation is used to calculate CZ.
1
CZ +
2p
20
ǒ Ǔ
f
VI
10
R
F
(28)
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
II. Two Switch Forward DC−to−DC Power Stage
A two-switch forward converter topology was selected for the second stage of this design. The two-switch
forward power converter has two major advantages over a traditional forward converter, making it ideal for this
application. First, the FETs used in the two-switch forward required only one-half the maximum VDS as
compared to the traditional forward converter. Second, the transformer’s reset energy is returned to the input
through clamping diodes for higher efficiency.
transformer turns ratio
Equation (29) calculates the transformer turns ratio required for the two-switch forward power converter of this
design example. It can be derived from the dc transfer function of a forward converter. VOUT is the output voltage
of the forward converter and is 12-V for this design. VF is the forward voltage drop of the secondary rectifier diode
and is set to 1V. VBOOST(min) is the minimum input voltage to the forward converter. The level of this voltage is
determined by where the control device forces the dc-to-dc converter into undervoltage lockout (UVLO). The
UCC38500 control device is configured to drive the dc-to-dc power stage into UVLO at approximately 74% of
the nominal boost converters output voltage. VBOOST(min) for this design is approximately 285 V. DMAX is 0.44
and is the guaranteed maximum duty cycle of the forward converter. For this design example the calculated
turns ratio is approximately 0.101.
Transformer Turns +
N
V OUT ) V F
+ S
V BOOST(min) D MAX
NP
(29)
output inductor
The following equations can be used to calculate the inductor required for this design example. First, the
minimum duty cycle DMIN, which occurs at the maximum boost voltage, needs to be calculated. The maximum
boost voltage is limited by the OVP trip point, which is set to approximately 425 V. For this design DMIN is
approximately 31%. The output inductor ripple current (∆IL) for this design is given at 30% of the maximum load
current. Next calculate the output inductor (L), where the switching frequency (fS) is 100 kHz. The calculated
output inductor for this design is approximately 38 µH.
D MIN +
DI L +
L+
V OUT ) V F
V BOOST(max)
NP
NS
(30)
P OUT 0.3
V OUT
ǒVOUT ) VFǓ
DI L
(31)
ǒ1 * DMINǓ
fS
(32)
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
output capacitor
The following equations can be used to estimate the minimum output capacitance and the capacitor’s maximum
allowable equivalent series resistance (ESR), where COUT is the minimum output capacitance and tS is the
period of the switching frequency. ∆VOUT is the maximum allowable output ripple voltage, selected as
approximately 1% of the output voltage. For this design, the minimum calculated output capacitance is 170 µF
and the maximum allowable ESR is 96 mΩ. A Panasonic HFQ 1800-µF electrolytic capacitor with an ESR of
0.048 Ω is used.
C OUT + 1
8
ESR +
ǒVOUT ) VFǓ
L
ǒD
MAX
ǒt SǓ
Ǔ
2
DV OUT
(33)
DV OUT
DI L
(34)
RSENSE2
The dc-to-dc power converter is designed for peak current mode control. RSENSE2 is the resistor that senses
the current in the forward converter. The sense resistor in Figure 9 is referred to as R4. The following equations
can be used to calculate RSENSE2. Where IM is the magnetizing current of the transformer used in the step-down
converter and VBOOST is the output voltage of the boost stage. D is the typical duty ratio of the forward converter.
VISENSE2_peak is the peak current sense comparator voltage that is typically 1.15 V. For this design example LM
is approximately 8 mH and the RSENSE2 is approximately 1 Ω.
IM +
V BOOST
LM
D
fS
(35)
V ISENSE2_peak
R SENSE2 +
IM )
NS
NP
ǒ
DI L
) I OUT(max)
2
Ǔ
1.3
(36)
soft-start
The UCC38500 has soft-start circuitry to allow for a controlled ramp of the second stage’s duty cycle during
start-up. This is accomplished through the SS2 circuitry described earlier in this data sheet. Equation (37)
calculates the approximate capacitance needed based on the designer’s soft-start requirements. Where ISS2
is the soft-start charging current, which is typically 10 µA. ∆t is the desired soft start time, which was selected
to be approximately 5 ms for this example. The calculated soft-start capacitor (CSS) for this example is
approximately 10 nF.
C SS +
I ISS2 D t
4.5
(37)
slope compensation
When designing with peak current-mode control, slope compensation may be necessary to prevent instability.
In this design, the magnetizing current provided more than enough slope compensation. If slope compensation
is needed with external components, please refer to Unitrode/Texas Instruments Application Note, Practical
Considerations in Current Mode Power Supplies, TI Literature No. SLUA110.
22
www.ti.com
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
control loop
Figure 12 shows the control block diagram for the typical application shown in Figure 9. GC(s) is the
compensation network’s transfer function (TF), GOPTO(s) is the opto-isolator TF, GCO(s) is the control-to-output
TF, and H(s) is the divider TF. The following equations can be used to estimate the frequency response of each
gain block, where fOPTO_pole is the frequency, where the optoisolator is −3 dB from its dc operating point, and
VREF_TL431 is the reference voltage of the TL431 shunt regulator. RLOAD represents the typical load impedance
for the design.
G OPTO(s) + R13
R36
G C(s) +
H(s) +
s
C14
1
1)
(38)
s R35 C14 ) 1
R31 (1 ) (s R35
R27
+
R27 ) R31
G CO(s) +
s
2p f OPTO_pole
R13
R36
C15))
1
1)
s
2p f OPTO_pole
(39)
V VREF_TL431
V OUT
V OUT
R LOAD
+
VC
R SENSE2
NP
Ns
(40)
ǒ1 ) ǒs
ǒ1 ) ǒs
C OUT
C OUT
ESRǓ
Ǔ
R LOADǓ
Ǔ
(41)
VBOOST
VREF_TL431
Σ
GC(s)
VC
GCO(s)
VOUT
H(s)
Figure 12. UCC38500 Control Block
www.ti.com
23
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
Figure 13 shows the circuitry for the voltage feedback loop. D13 is a TL431 shunt regulator that functions as
an operational amplifier, providing feedback control.
VBOOST
VC = VERR
VOUT
GCO(s)
GCO(s)
Q5
VREF
R36
H11AV1
6
R13
D14
1
5
R16
PGND2
R31
2
4
C14
3
C15
U3
R35
D13
SGND
R27
UDG−01091
Figure 13. UCC38500 Feedback Loop
Initially the designer must select the resistor values for the divider gain H(s). Equation (42) is used to determine
resistor size. Selecting R27 to be a standard value of 10-kΩ requires R31 to be approximately 38.3 kΩ.
R31 +
R27 ǒV OUT * V REFǓ
V REF
(42)
It is important to correctly bias the TL431 and the optoisolator for proper operation. Zener diode D14 and a
depletion mode J-FET, Q5, supply the bias voltage for the TL431. Resistors R16 and R13 provide the minimum
bias currents for the TL431 and the optoisolator respectively and can be calculated with the following equations.
Where IOP(min) is the minimum optoisolation current, and VVERR(max) is the maximum voltage seen at the VERR
pin of the UCC38500. VERR has an internal clamp that limits this pin to 4.5 V. VF is the typical forward voltage
of the diode in the opto isolator, and ITL431(min) is the minimum cathode current of the TL431. For the
components used in this design example R13 is calculated to be approximately 2.0 kΩ and R16 was calculated
to be approximately 680 Ω. The optoisolator is configured to have dc gain of approximately 20 dB and the
optoisolator −3 dB point is approximately 8 kHz. Figure 14 shows the frequency response of the optoisolator.
24
www.ti.com
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
R16 +
R13 +
VF
I TL431 (min)
(43)
V REF * V VERR (max)
I OP (min)
(44)
To compensate the loop, it is necessary to estimate or measure the control-to-output gain’s frequency response
GCO(s). The frequency response for GCO(s) was measured with a network analyzer and the measured
frequency response is shown in Figure 15.
40
120
GAIN
60
Gain − dB
20
0
0
−60
−20
−40
−120
PHASE
50
180
40
144
30
108
20
10
36
0
0
−10
−36
−20
−72
1k
10 k
f − Frequency − Hz
−180
100 k
−108
−30
−40
−60
100
72
GAIN
−50
100
Figure 14
Phase − Degrees
180
Gain − dB
60
POWER STAGE CONTROL-TO-OUTPUT TRANSFER
FUNCTION (GAIN AND PHASE)
vs.
FREQUENCY
Phase − Degrees
OPTOISOLATOR TRANSFER FUNCTION
(GAIN AND PHASE)
vs.
FREQUENCY
PHASE
1k
10 k
f − Frequency − Hz
−144
−180
100 k
Figure 15
After determining the frequency response of GCO(s) it is necessary to define some closed loop frequency
response design goals. The following equation describes the frequency response of the loop gain (T(s)dB) of
the system in decibels. Typically, the loop is designed to crossover at a frequency below one-sixth of the
switching frequency. In order for this design example to have good transient response, the design goal is to have
the loop gain crossover at approximately 1 kHz, which is less than one-sixth of the switching frequency. The
gain crossover frequency for this design example is referenced as fC.
T(s) dB + G C(s) ) G CO(s) ) H(s)
(45)
The compensation network that is used (GC(s)) has three poles and one zero. One pole occurs at the origin,
and a second pole is caused by the limitations of the opto-isolator. The third pole is set to attenuate the
high-frequency gain and needs to be set to one-half of the switching frequency. The zero is set at the desired
crossover frequency.
The following equations can be used to select R35, C14 and C15, where GCO(s), GOPTO(s), and H(s) are the
gains in decibels (dB) of each control block at the desired fC. From the graphs in Figures 14 and 15 it can be
observed at the desired crossover frequency GCO(s) is approximately 0 dB and GOPTO(s) is approximately
www.ti.com
25
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
23 dB. Therefore the compensation circuitry needs to have a gain of −23 dB at the desired crossover frequency.
For this example R35 is calculated at approximately 18.2 kΩ. Capacitor C14 is estimated to be approximately
10 nF and C15 is calculated at approximately 180 pF.
H(s) + 20 log
R35 + R31
C14 +
C15 +
ǒ2p
ǒ
ƪ ƫ
V REF
V OUT
(46)
10 ǒ*G CO(s) dB)G OPTO(s) dB)H(s) dBǓ
(47)
1
R35
f CǓ
1
2p
R35
(48)
Ǔ
f SW
2
(49)
Figure 16 shows the frequency response of the compensation network GC(s) and Figure 17 shows the
measured frequency response of the loop gain T(s). The frequency response characteristics in Figure 17 show
that fC is approximately 1.5 kHz with a phase margin of about 55 degrees. The gain margin is approximately
50 dB.
60
FEEDBACK CONTROL TRANSFER FUNCTION
(GAIN AND PHASE)
vs.
FREQUENCY
TOTAL LOOP TRANSFER FUNCTION
(GAIN AND PHASE)
vs.
FREQUENCY
180
60
40
120
40
20
60
0
0
180
20
−20
−60
LOOP GAIN
−180
100 k
−60
100
−120
1k
10 k
f − Frequency − Hz
Figure 17
Figure 16
26
0
−40
1k
10 k
f − Frequency − Hz
120
60
0
−120
−40
−60
100
−60
LOOP PHASE
www.ti.com
−180
100 k
Phase − Degrees
COMPENSATION
GAIN
GOPTO − Gain − dB
−20
Phase − Degrees
GOPTO − Gain − dB
COMPENSATION
PHASE
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
UCC28500DW
ACTIVE
SOIC
DW
20
25
None
CU SNPB
Level-2-220C-1 YEAR
UCC28500DWTR
ACTIVE
SOIC
DW
20
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC28500N
ACTIVE
PDIP
N
20
20
None
CU SNPB
Level-NA-NA-NA
UCC28501DW
ACTIVE
SOIC
DW
20
25
None
CU SNPB
Level-2-220C-1 YEAR
UCC28501DWTR
ACTIVE
SOIC
DW
20
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC28501N
ACTIVE
PDIP
N
20
20
None
CU SNPB
Level-NA-NA-NA
UCC28502DW
ACTIVE
SOIC
DW
20
25
None
CU SNPB
Level-2-220C-1 YEAR
UCC28502DWTR
ACTIVE
SOIC
DW
20
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC28502N
ACTIVE
PDIP
N
20
20
None
CU SNPB
Level-NA-NA-NA
UCC28503DW
ACTIVE
SOIC
DW
20
25
None
CU SNPB
Level-2-220C-1 YEAR
UCC28503DWTR
ACTIVE
SOIC
DW
20
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC28503N
ACTIVE
PDIP
N
20
20
None
CU SNPB
Level-NA-NA-NA
UCC38500DW
ACTIVE
SOIC
DW
20
25
None
CU SNPB
Level-2-220C-1 YEAR
UCC38500DWTR
ACTIVE
SOIC
DW
20
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC38500N
ACTIVE
PDIP
N
20
20
None
CU SNPB
Level-NA-NA-NA
UCC38501DW
ACTIVE
SOIC
DW
20
25
None
CU SNPB
Level-2-220C-1 YEAR
UCC38501DWTR
ACTIVE
SOIC
DW
20
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC38501N
ACTIVE
PDIP
N
20
20
None
CU SNPB
Level-NA-NA-NA
UCC38502DW
ACTIVE
SOIC
DW
20
25
None
CU SNPB
Level-2-220C-1 YEAR
UCC38502DWTR
ACTIVE
SOIC
DW
20
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC38502N
ACTIVE
PDIP
N
20
20
None
CU SNPB
Level-NA-NA-NA
UCC38503DW
ACTIVE
SOIC
DW
20
25
None
CU SNPB
Level-2-220C-1 YEAR
UCC38503DWTR
ACTIVE
SOIC
DW
20
2000
None
CU SNPB
Level-2-220C-1 YEAR
UCC38503N
ACTIVE
PDIP
N
20
20
None
CU SNPB
Level-NA-NA-NA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2005
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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solutions:
Products
Applications
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amplifier.ti.com
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www.ti.com/audio
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dataconverter.ti.com
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dsp.ti.com
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interface.ti.com
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www.ti.com/digitalcontrol
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logic.ti.com
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www.ti.com/military
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power.ti.com
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www.ti.com/opticalnetwork
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microcontroller.ti.com
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www.ti.com/security
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www.ti.com/telephony
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www.ti.com/video
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www.ti.com/wireless
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