SEMTECH SC120EVB

SC120
Low Voltage Synchronous
Boost Converter
POWER MANAGEMENT
Features
Description
„
The SC120 is a high efficiency, low noise, synchronous
step-up DC-DC converter that provides boosted voltage
levels in low-voltage handheld applications. The wide
input voltage range allows use in systems with single
NiMH or alkaline battery cells as well as in systems with
higher voltage battery supplies. It features an internal
1.2A switch and synchronous rectifier to achieve up to
94% efficiency and to eliminate the need for an external
Schottky diode. The output voltage can be set to 3.3V
with internal feedback, or to any voltage within the specified range using a standard resistor divider.
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Input voltage — 0.7V to 3.8V
Minimum start-up voltage — 0.85V
Output voltage — fixed at 3.3V; adjustable from 1.8V
to 4.0V
Peak input current limit — 1.2A typically
Output current at 3.3 VOUT — 100mA with VIN = 1.0V,
150mA with VIN = 1.5V
Efficiency up to 94%
Internal synchronous rectifier
Switching frequency — 1.2MHz
Automatic power save
Anti-ringing circuit
Operating supply current (measured at OUT) — 50μA
Shutdown current — 0.1μA (typ)
No forward conduction path during shutdown
Available in ultra-thin 1.5 x 2.0 x 0.6 (mm) MLPD-6
package
Fully WEEE and RoHS compliant
Applications
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CO
NF
ID
EN
TI
AL
„
The SC120 operates in Pulse Width Modulation (PWM)
mode for moderate to high loads and Power Save Mode
(PSAVE) for improved efficiency under light load conditions. It features anti-ringing circuitry for reduced EMI in
noise sensitive applications. Output disconnect capability
is included to reduce leakage current, improve efficiency,
and eliminate external components sometimes needed to
disconnect the load from the supply during shutdown.
MP3 players
Smart Phones and cellular phones
Palmtop computers and handheld Instruments
PCMCIA cards
Memory cards
Digital cordless phones
Personal medical products
Wireless VoIP phones
Small motors
Low quiescent current is maintained with a high 1.2MHz
operating frequency. Small external components and the
space saving MLPD-6, 1.5x2.0x0.6mm package make this
device an excellent choice for small handheld applications
that require the longest possible battery life.
Typical Application Circuit
L1
IN
Single
Cell
(1.2V)
LX
OUT
EN
CIN
GND
3.3V
FB
COUT
SC120
August 6, 2009
PRELIMINARY
1
SC120
Pin Configuration
1
GND
2
IN
3
TOP VIEW
T
6
OUT
5
FB
4
EN
Device
Package
SC120ULTRT(1)(2)
MLPD-UT-6 1.5×2
SC120EVB
Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free package only. Device is WEEE and RoHS compliant.
L
LX
Ordering Information
FI
CO
N
Marking Information
DE
NT
IA
MLPD-UT; 1.5x2, 6 LEAD
θJA = 84°C/W
120
yw
y = year of manufacture
w = week of manufacture
PRELIMINARY
2
SC120
Absolute Maximum Ratings
Recommended Operating Conditions
IN, OUT, LX, FB (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
Ambient Temperature Range (°C) . . . . . . . . . . . . -40 to +85
EN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)
VIN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 to 3.8
(1)
ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
VOUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 to 4.0
Thermal Information
Thermal Resistance, Junction to Ambient(2) (°C/W) . . . . 84
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . 150
Storage Temperature Range (°C) . . . . . . . . . . . -65 to +150
L
Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . +260
IA
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NT
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
DE
Electrical Characteristics
Unless otherwise noted VIN = 2.5V, CIN = COUT = 22μF, L1 = 4.7μH, TA = -40 to +85°C. Typical values are at TA = 25°C.
Symbol
Minimum Startup Voltage
Shutdown Current
VIN
VIN-SU
CO
N
Input Voltage Range
Conditions
FI
Parameter
Min
Typ
0.7
IOUT < 1mA, TA = 0°C to 85°C
Max
Units
3.8
V
0.85
V
1
μA
ISHDN
TA = 25°C, VEN = 0V
0.1
IQ
In PSAVE mode, non-switching, measured at OUT
50
μA
fOSC
1.2
MHz
Maximum Duty Cycle
DCMAX
90
%
Minimum Duty Cycle
DCMIN
Operating Supply Current(1)
Internal Oscillator Frequency
Output Voltage
Adjustable Output Voltage Range
Internal Feedback Reference
Accuracy
15
VOUT
VFB = 0V
VOUT_RNG
VOUT > VIN + 0.3V
1.8
4.0
V
VINT_FB
VFB = 0V, (VOUT set to 3.3V)
-3
3
%
1.218
V
0.1
μA
FB Pin Regulation Voltage
VFB
FB Pin Input Current
IFB
Startup Time
tSU
P-Channel ON Resistance
RDSP
3.3
%
1.182
1.200
VFB = 1.2V
VOUT = 3.3V
PRELIMINARY
V
1
ms
0.6
Ω
3
SC120
Electrical Characteristics (continued)
Symbol
Conditions
N-Channel ON Resistance
RDSN
VOUT = 3.3V
N-Channel Current Limit
ILIM(N)
VIN = 3.0V
ILIM(P)-SU
VIN > VOUT, VEN > VIH
LX Leakage Current PMOS
ILXP
TA = 25°C, VLX = 0V
1
μA
LX Leakage Current NMOS
ILXN
TA = 25°C, VLX = 3.3V
1
μA
Logic Input High
VIH
VIN = 3.0V
Logic Input Low
VIL
VIN = 3.0V
Logic Input Current High
IIH
VEN = VIN = 3.0V
Logic Input Current Low
IIL
VEN = 0V
0.9
Typ
Max
0.5
Ω
1.2
A
150
mA
L
0.85
-0.2
Units
V
0.2
V
1
μA
μA
NT
P-Channel Startup Current Limit
Min
IA
Parameter
CO
N
FI
DE
NOTES:
(1) Quiescent operating current is drawn from OUT while in regulation. The quiescent operating current projected to IN is approximately
IQ × (VOUT/VIN).
PRELIMINARY
4
SC120
Typical Characteristics
Efficiency vs. IOUT (VOUT = 1.8V)
Efficiency vs. I
ο
100
VIN = 1.5V
80
80
70
70
VIN = 1.1V
60
VIN = 0.7V
50
40
50
40
30
20
20
10
10
0.1
0.2
0.5
1
2
5
10
20
50
100
200
0
500
TA = 85°C
60
30
0
TA = 25°C
0.1
Efficiency vs. IOUT (VOUT = 3.3V)
1
2
100
VIN = 1.0V
60
VIN = 2.0V
50
FI
40
20
10
0.1
0.2
0.5
1
2
CO
N
30
5
10
20
50
100
Efficiency (%)
DE
70
50
100
200
500
200
500
FB grounded, L = 4.7μH, VIN = 1.5V
TA = –40°C
70
TA = 85°C
60
50
40
TA = 25°C
30
20
10
200
0
500
0.1
0.2
0.5
1
2
Efficiency vs. I
(V
OUT
OUT
ο
R1 = 1.37MΩ, R2 = 590kΩ, L = 4.7μH, TA = 25 C
= 4.0V)
100
VIN = 3.0V
90
80
80
Efficiency (%)
VIN = 2.0V
50
40
20
10
10
2
5
10
20
50
100
200
100
500
= 4.0V)
TA = –40°C
TA = 25°C
TA = 85°C
40
20
1
(V
50
30
0.5
50
60
30
0.2
20
OUT
OUT
R1 = 1.37MΩ, R2 = 590kΩ, L = 4.7μH, VIN = 2.4V
70
VIN = 1.0V
60
0.1
10
Efficiency vs. I
90
70
5
IOUT (mA)
IOUT (mA)
Efficiency (%)
20
80
80
0
10
90
90
100
5
IOUT (mA)
NT
FB grounded, L = 4.7μH, TA = 25 C
VIN = 3.0V
Efficiency (%)
0.5
Efficiency vs. IOUT (VOUT = 3.3V)
ο
0
0.2
IA
IOUT (mA)
100
= 1.8V)
TA = –40°C
90
Efficiency (%)
Efficiency (%)
90
(V
OUT
OUT
R1 = 499kΩ, R2 = 1MΩ, L = 4.7μH, VIN = 1.1V
L
100
R1 = 499kΩ, R2 = 1MΩ, L = 4.7μH, TA = 25 C
0
0.1
0.2
0.5
1
2
5
10
20
50
100
200
500
IOUT (mA)
IOUT (mA)
PRELIMINARY
5
SC120
Typical Characteristics (continued)
Load Regulation (VOUT = 1.8V)
Load Regulation (VOUT = 1.8V)
ο
R1 = 499kΩ, R2 = 1MΩ, L = 4.7μH, TA = 25 C
1.85
1.84
1.84
1.83
1.83
1.82
1.82
VOUT (V)
1.81
1.81
1.8
1.79
TA = 25°C
VIN = 1.5V
VIN = 1.1V
VIN = 0.7V
1.79
TA = 85°C
1.78
50
100
150
200
250
300
350
400
450
1.77
0
500
50
100
150
200
Load Regulation (VOUT = 3.3V)
250
300
350
400
450
500
450
500
IOUT (mA)
IA
IOUT (mA)
Load Regulation (VOUT = 3.3V)
ο
FB grounded, L = 4.7μH, TA = 25 C
FB grounded, L = 4.7μH, VIN = 1.5V
NT
3.34
TA = –40°C
1.8
1.78
1.77
0
R1 = 499kΩ, R2 = 1MΩ, L = 4.7μH, VIN = 1.1V
L
VOUT (V)
1.85
3.34
TA = 85°C
3.32
3.32
VIN = 3.0V
DE
VOUT (V)
3.28
VIN = 2.0V
3.24
FI
3.26
VIN = 1.0V
3.22
3.2
0
50
100
150
CO
N
VOUT (V)
3.3
200
250
300
350
400
3.3
3.28
3.26
3.24 TA = –40°C
TA = 25°C
3.22
TA = 85°C
450
3.2
0
500
50
100
150
200
IOUT (mA)
Load Regulation vs. (V
4.05
OUT
ο
R1 = 1.37MΩ, R2 = 590kΩ, L = 4.7μH, TA = 25 C
250
300
350
400
IOUT (mA)
= 4.0V)
Load Regulation (V
4.05
OUT
R1 = 1.37MΩ, R2 = 590kΩ, L = 4.7μH, VIN = 2.4V
= 4.0V)
TA = 85°C
4
4
VOUT (V)
VOUT (V)
TA = 25°C
VIN = 3.0V
3.95
3.9
3.95
TA = –40°C
TA = –40°C
VIN = 1.0V
3.9
VIN = 2.0V
TA = 25°C
TA = 85°C
3.85
0
50
100
150
200
250
300
350
400
450
500
3.85
0
IOUT (mA)
50
100
150
200
250
300
350
400
450
500
IOUT (mA)
PRELIMINARY
6
SC120
Typical Characteristics (continued)
Line Regulation — PSAVE Mode (VOUT = 1.8V)
1.85
Line Regulation — PWM Mode (VOUT = 1.8V)
R1 = 499kΩ, R2 = 1MΩ, L = 4.7μH, IOUT = 4mA
1.85
1.84
1.84
1.83
1.83
TA = 25°C
TA = –40°C
TA = 85°C
1.82
VOUT (V)
1.82
VOUT (V)
R1 = 499kΩ, R2 = 1MΩ, L = 4.7μH, IOUT = 45mA
1.81
TA = –40°C
1.81
1.8
1.8
1.79
1.79
1.78
1.78
TA = 85°C
1.77
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.77
0.7
1.5
3.34
TA = 85°C
3.32
DE
TA = –40°C
VOUT (V)
3.28
TA = 25°C
FI
3.26
3.22
3.2
0.5
0.75
1
1.25
CO
N
3.24
1.2
1.3
1.4
1.5
FB grounded, L = 4.7μH, IOUT = 75mA
1.5
1.75
2
2.25
2.5
3.3
3.28
TA = –40°C
3.26
TA = 25°C
TA = 85°C
3.24
3.22
2.75
3.2
0.5
3
0.75
1
1.25
1.5
VIN (V)
1.75
2
2.25
2.5
2.75
3
VIN (V)
Line Regulation — PSAVE Mode (VOUT = 4.0V)
4.05
1.1
VIN (V)
3.32
3.3
VOUT (V)
1
NT
3.34
0.9
Line Regulation — PWM Mode (VOUT = 3.3V)
Line Regulation — PSAVE Mode (VOUT = 3.3V)
FB grounded, L = 4.7μH, IOUT = 4mA
0.8
IA
VIN (V)
L
TA = 25°C
Line Regulation — PWM Mode (VOUT = 4.0V)
R1 = 1.37MΩ, R2 = 590kΩ, L = 4.7μH, IOUT = 4mA
4.05
R1 = 1.37MΩ, R2 = 590kΩ, L = 4.7μH, IOUT = 75mA
TA = 85°C
4
4
TA = 25°C
VOUT (V)
VOUT (V)
TA = –40°C
3.95
3.9
3.9
3.85
0.5
3.95
1
1.5
2
2.5
3
3.5
4
3.85
0.5
TA = –40°C
TA = 25°C
TA = 85°C
1
1.5
2
2.5
3
3.5
4
VIN (V)
VIN (V)
PRELIMINARY
7
SC120
Typical Characteristics (continued)
Temperature Reg. — PSAVE Mode (VOUT = 1.8V)
1.85
Temperature Reg. — PWM Mode (VOUT = 1.8V)
R1 = 499kΩ, R2 = 1MΩ, L = 4.7μH, IOUT = 4mA
1.85
VIN = 1.5V
1.84
R1 = 499kΩ, R2 = 1MΩ, L = 4.7μH, IOUT = 45mA
1.84
1.83
1.83
VIN = 0.7V
1.82
VIN = 1.1V
1.81
1.81
1.8
1.8
1.79
1.79
1.78
1.78
1.77
-50
-25
0
25
50
75
VIN = 1.5V
VIN = 1.1V
VIN = 0.7V
1.77
-50
100
-25
o
Junction Temperature ( C)
50
75
100
o
IA
Temperature Reg. — PWM Mode (VOUT = 3.3V)
3.34
VIN = 3.0V
FB grounded, L = 4.7μH, IOUT = 75mA
3.32
DE
VIN = 1.0V
3.3
VIN = 2.0V
VOUT (V)
3.28
3.26
FI
VOUT (V)
25
NT
FB grounded, L = 4.7μH, IOUT = 4mA
3.32
3.22
3.2
-50
-25
0
CO
N
3.24
25
50
75
VIN = 3.0V
3.3
3.28
VIN = 2.0V
3.26
VIN = 1.0V
3.24
3.22
3.2
-50
100
-25
o
0
25
50
75
100
o
Junction Temperature ( C)
Junction Temperature ( C)
Temperature Reg. — PWM Mode (VOUT = 4.0V)
Temperature Reg. — PSAVE Mode (VOUT = 4.0V)
4.05
0
Junction Temperature ( C)
Temperature Reg. — PSAVE Mode (VOUT = 3.3V)
3.34
L
VOUT (V)
VOUT (V)
1.82
R1 = 1.37MΩ, R2 = 590kΩ, L = 4.7μH, IOUT = 4mA
4.05
R1 = 1.37MΩ, R2 = 590kΩ, L = 4.7μH, IOUT = 75mA
VIN = 3.0V
4
4
VIN = 3.0V
VOUT (V)
VOUT (V)
VIN = 2.0V
VIN = 1.0V
3.95
VIN = 1.0V
3.9
3.9
3.85
-50
VIN = 2.0V
3.95
-25
0
25
50
75
100
3.85
-50
-25
0
25
50
75
100
o
o
Junction Temperature ( C)
Junction Temperature ( C)
PRELIMINARY
8
SC120
Typical Characteristics (continued)
Startup Min. Load Resistance vs. VIN (VOUT = 1.8V)
Startup Max. Load Current vs. VIN (VOUT = 1.8V)
50
R1 = 499kΩ, R2 = 1MΩ
160
R1 = 499kΩ, R2 = 1MΩ
140
40
Equivalent RLOAD (Ω)
30
TA = 85°C
20
TA = –40°C
80
60
TA = 85°C
TA = –40°C
10
40
TA = 25°C
0
0.7
0.8
0.9
TA = 25°C
100
20
1
1.1
1.2
1.3
1.4
0
1.5
0.7
1
160
1.3
1.4
1.5
FB grounded
TA = 25°C
TA = 85°C
50
40
FI
TA = –40°C
30
10
TA = 25°C
0
0.5
0.75
1
1.25
CO
N
20
1.5
1.75
2
2.25
2.5
Equivalent RLOAD (Ω)
DE
120
60
100
TA = –40°C
80
60
TA = 85°C
40
20
2.75
0
0.5
3
0.75
1
1.25
1.5
VIN (V)
1.75
2
2.25
2.5
2.75
3
VIN (V)
Startup Max. Load Current vs. VIN (VOUT = 4.0V)
Startup Min. Load Resistance vs. VIN (VOUT = 4.0V)
R1 = 1.37MΩ, R2 = 590kΩ
160
R1 = 1.37MΩ, R2 = 590kΩ
140
80
TA = 85°C
TA = 25°C
120
Equivalent RLOAD (Ω)
IOUT (mA)
1.2
140
70
100
1.1
VIN (V)
NT
FB grounded
80
IOUT (mA)
0.9
Startup Min. Load Resistance vs. VIN (VOUT = 3.3V)
Startup Max. Load Current vs. VIN (VOUT = 3.3V)
90
0.8
IA
VIN (V)
L
IOUT (mA)
120
60
TA = –40°C
40
TA = 25°C
100
80
TA = –40°C
60
40
20
TA = 85°C
20
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
VIN (V)
1
1.5
2
2.5
3
3.5
4
VIN (V)
PRELIMINARY
9
SC120
Typical Characteristics (continued)
IOUT (max) vs. VIN
Minimum Start-up Voltage vs. Temperature
VOUT = 3.3V
0.6
0.9
0.85
0.5
T = 25°C
0.4
Startup Voltage (V)
T = 85°C
0.3
T = -40°C
0.2
0.8
0.75
0.7
0.65
0.1
0.9
1.1
1.3
1.5
1.7
Input Voltage (V)
1.9
2.1
2.3
0.6
-40
2.5
-20
0
20
40
Temperature (°C)
60
80
100
IA
0
0.7
L
Maximum Output Current (A)
VOUT = 3.3V, IOUT = 1mA
Load Transient (PSAVE to PWM)
Load Transient (PWM to PWM)
VOUT = 3.3V, VIN = 1.5V, TA =25°C
NT
VOUT = 3.3V, VIN = 1.2V, TA = 25°C
IOUT = 40mA to
DE
IOUT = 5mA to
100mA
140mA
(50mA/div)
(50mA/div)
FI
VOUT
(100mV/div)
CO
N
AC Coupled
VOUT
(100mV/div)
AC Coupled
Time = (100μs/div)
Time = (100μs/div)
PSAVE Operation
PWM Operation
VOUT = 3.3V, VIN = 1.5V, IOUT = 50mA
VOUT = 3.3V, VIN = 1.5V, IOUT = 20mA
VOUT ripple
VOUT ripple
(50mV/div)
(10mV/div)
IL
IL
(100mA/div)
(100mA/div)
VLX
VLX
(5V/div)
(5V/div)
Time = (10μs/div)
Time = (400ns/div)
PRELIMINARY
10
SC120
Pin Descriptions
Pin #
Pin Name
Pin Function
1
LX
2
GND
3
IN
Battery input and damping switch connection.
4
EN
Enable digital control input — active high.
5
FB
Feedback input — connect to GND for preset 3.3V output. A voltage divider is connected from OUT to GND to
adjust output from 1.8V to 4.0V.
6
OUT
T
Thermal
Pad
Switching node — connect an inductor from the input supply to this pin.
Signal and power ground.
L
Output voltage supply pin — requires an external 10μF bypass capacitor (while under VOUT bias) for normal
operation.
CO
N
FI
DE
NT
IA
Thermal Pad is for heat sinking purposes — connect to ground using multiple vias — not connected internally.
PRELIMINARY
11
SC120
Block Diagram
IN
VOUT
Comp.
3
+
6
OUT
1
LX
2
GND
+ 1.7 V
+
EN
Start-up
Oscillator
4
-
Oscillator and
Slope
Generator
NT
Slope
Comp.
DE
PWM
Comp.
+
Output Voltage
Selection Logic
-
Error
Amp.
CO
N
5
Gate Drive
and
Logic
Control
Bulk
Bias
PWM
Control
FI
-
FB
IA
L
PLIM
Amp.
+
+ VREF
- 1.2 V
PRELIMINARY
+
NLIM
Amplifier
+
-
Current
Amplifier
12
SC120
Applications Information
Detailed Description
The SC120 is a synchronous step-up Pulse Width
Modulated (PWM) DC-DC converter utilizing a 1.2MHz
fixed frequency current mode architecture. It is designed
to provide output voltages in the range 1.8V to 4.0V from
an input voltage as low as 0.7V, with a (output unloaded)
start up input voltage of 0.85V.
R1
FB
CFB
(optional)
R2
Figure 1 — Output Voltage Feedback Circuit
VOUT
IA
L
The values of the resistors in the voltage divider network
are chosen to satisfy the equation:
§ R ·
VFB u ¨¨1 1 ¸¸
© R2 ¹
The value of R2 should be 590kΩ or larger for stability.
Otherwise, the values of R1 and R2 can be as large as
desired to achieve low quiescent current.
CO
N
FI
DE
The regulator control circuitry is shown in the Block
Diagram. It is comprised of a programmable feedback
controller, an internal 1.2MHz oscillator, an nchannel Field Effect Transistor (FET) between the LX and
GND pins, and a p-channel FET between the LX and OUT
pins. The current flowing through both FETs is monitored
and limited as required for startup, PWM operation, and
PSAVE operation. An external inductor must be connected
between the IN pin and the LX pin. When the n-channel
FET is turned on, the LX pin is internally grounded, connecting the inductor between IN and GND. This is called
the on-state. During the on-state, inductor current flows
to ground and is increasing. When the n-channel FET is
turned off and the p-channel FET is turned on (known as
the off-state), the inductor is then connected between IN
and OUT. The (now decreasing) inductor current flows
from the input to the output, boosting the output voltage
above the input voltage.
OUT
NT
The device operates in two modes: PWM and automatic
PSAVE mode. In PWM operation, the devices uses pulse
width modulation control to regulate the output under
moderate to heavy load conditions. It switches to PSAVE
mode when lightly loaded. Quiescent current consumption is as little as 50μA, into the OUT pin, when in PSAVE
mode.
LX
Output Voltage Selection
The SC120 output voltage can be programmed to an
internally preset value or it can be programmed with
external resistors. The output is internally programmed to
3.3V when the FB pin is connected to GND. Any output
voltage in the range 1.8V to 4.0V can be programmed with
a resistor voltage divider between OUT and the FB pin as
shown in Figure 1.
PWM Operation
The PWM cycle runs at a fixed frequency (fosc = 1.2MHz),
with a variable duty cycle (D). PWM operation continually draws current from the input supply (except for discontinuous mode, described below). During the on-state,
of the PWM cycle, the n-channel FET is turned on, grounding the inductor at the LX pin. This causes the current
flowing from the input supply through the inductor to
ground to ramp up. During the off-state, the n-channel
FET is turned off and the p-channel FET (synchronous
rectifier) is turned on. This causes the inductor current to
flow from the input supply through the inductor into the
output capacitor and load, boosting the output voltage
above the input voltage. The cycle then repeats to reenergize the inductor.
Ideally, the steady state (constant load) duty cycle is
determined by D = 1 – (VIN/VOUT ), but must be greater in
practice to overcome dissipative losses. The SC120 PWM
controller constrains the value of D such that 0.15 < D < 0.9,
(approximately).
The average inductor current during the off-state multiplied by (1-D) is equal to the average load current. The
inductor current is alternately ramping up (on-state) and
down (off-state) at a rate and amplitude determined by
PRELIMINARY
13
SC120
Applications Information (continued)
L
When the output current increases above a predetermined level, either of two PSAVE exit conditions will force
the resumption of PWM operation. The first PSAVE exit
criterion is shown in Figure 2. If the PSAVE burst cycle
cannot provide sufficient current to the output, the
output voltage will decrease during the burst. If
FI
DE
At light loads, the SC120 will operate in PSAVE mode.
PSAVE mode ensures proper regulation when VIN is too
close to VOUT while the output load is too small to keep the
duty cycle above its minimum value. At very low output
load, PSAVE mode will operate more efficiently than PWM
mode. PSAVE operation is triggered by 256 consecutive
cycles of DM operation in PWM mode, when the output
of the PLIM amplifier falls to 0V during the off-state due to
low load current.
IA
PSAVE Operation
PSAVE mode requires fewer circuit resources than PWM
mode. All unused circuitry is disabled to reduce quiescent power dissipation. In PSAVE mode, the OUT pin
voltage monitoring circuit remains active and the output
voltage error amplifier operates as a comparator. PSAVE
regulation is shown in Figure 2. When VOUT < 1.008xVREG,
where VREG is the programmed output voltage, a burst of
fixed-period switching occurs to boost the output voltage.
The n-channel FET turns on (on-state) until the inductor
current rises to approximately 240mA. Then the n-channel
FET turns off and the p-channel FET turns on to transfer
the inductor energy to the output capacitor and load for
the duration of the off-state. This cycle repeats until
VOUT > 1.018×VREG, at which point bot FETs are turned off.
The output capacitor then discharges into the load until
VOUT < 1.008×VREG, and the burst cycle repeats.
NT
the inductance value, the input voltage, and the on-time
(D×T). Therefore, the instantaneous inductor current will
be alternately larger and smaller than the average. If the
average output current is sufficiently small, the minimum
inductor current can reach zero during the off-state. If
the energy stored in the inductor is depleted (if the inductor current decreases to zero) during the off-state, both
FETs turn off for the remainder of the off-state. If this discontinuous mode (DM) operation persists, the SC120
transitions to PSAVE operation.
CO
N
PSAVE Mode at
Moderate Load
BURST
OFF
BURST
Higher Load
Applied
PSAVE exit due
to output decay
OFF
BURST
PWM Mode at
High Load
PWM Mode
+1.8%
+0.8%
VOUT
Prog’d
Voltage
-2%
Inductor
Current
240mA
0A
Time
Figure 2 — PSAVE Operation With Exit to PWM Due To Output Voltage Decay
PRELIMINARY
14
SC120
Applications Information (continued)
PSAVE Mode at
Moderate Load
BURST
OFF
(> 5μs)
Higher Load
Applied
PSAVE exit due to
off-time reduction
PWM Mode at
High Load
OFF
(< 5μs)
PWM Mode
BURST
+1.8%
+0.8%
VOUT
Prog’d
Voltage
-2%
L
Inductor
Current
0A
NT
Time
IA
240mA
Figure 3 — PSAVE Operation With Exit to PWM Due To Off-time < 5μs
phenomenon is advantageous. Reverting to PWM operation with high VIN can result in VOUT rising above VREG, due
to the PWM minimum duty cycle. PSAVE operation avoids
this voltage rise because of its voltage-threshold on/off
control. If the load remains low enough to remain in
PSAVE, VIN can approach and even slightly exceed VOUT. To
initally enter PSAVE mode, the initial startup load must be
small enough to cause discontinuous mode PWM operation. This PSAVE mode startup load upper limit can be
increased if needed by reducing the inductance (refer to
the section Inductor Selection). Sufficiently large output
capacitance will prevent PSAVE exit due to the second exit
criterion (Figure 3).
CO
N
FI
DE
VOUT < 0.98 × VREG, PWM operation will resume. The second
PSAVE exit criterion, illustrated in Figure 3, depends on the
rate of discharge of the output capacitor between PSAVE
bursts. If the time between bursts is less than 5μs, then
PWM operation resumes. The output capacitance value
will affect the second criterion, but not the first. Reducing
the output capacitor will reduce the output load at which
PSAVE mode exits to PWM mode.
Within each on/off cycle of a PSAVE burst, the rate of
decrease of the inductor current during the off-state is
proportional to (VOUT − VIN). If VIN is sufficiently close to VOUT,
the decrease in current during the off-state may not overcome the increase in current during the minimum on-time
of the on-state, approximately 100ns. This can result in
the peak inductor current rising above the PSAVE mode
n-channel FET current limit. (Normally, when the
n-channel FET current limit is reached, the on-state ends
immediately and the off-state begins. This sets the duty
cycle on a cycle-by-cycle basis.) This inductor current rise
accumulates with each successive cycle in the burst. The
result is that the output load current that can be supported in PSAVE under this high VIN condition will be
greater than occurs if the 240mA current limit can be
enforced. Therefore the PSAVE exit load due to the first
exit criterion (Figure 2) can increase significantly. This
PSAVE VOUT ripple may increase due to parasitic capacitance on the external FB pin network. If using external
feedback programming, it is prudent to add a small capacitor between OUT and FB to the circuit board layout. When
operating the SC120 in the final configuration in PSAVE,
observe the amplitude of PSAVE ripple. If the ripple
exceeds 50mV for the expected range of input voltage, a
small-value capacitor should be tried. Capacitance on the
order of a few picofarads is often sufficient to bring the
ripple amplitude to approximately 50mV.
PRELIMINARY
15
SC120
Applications Information (continued)
Output Overload and Recovery
When in PSAVE operation, an increasing load will eventually satisfy one of the PSAVE exit criteria and regulation
will revert to PWM operation. As previously noted, the
PWM steady state duty cycle is determined by
D = 1 – (VIN/VOUT ), but must be somewhat greater in practice to overcome dissipative losses. As the output load
increases, the dissipative losses also increase. The PWM
controller must increase the duty cycle to compensate.
Eventually, one of two overload conditions will occur,
determined by VIN, VOUT, and the overall dissipative losses
due to the output load current. Either the maximum duty
cycle of 90% will be reached or the n-channel FET 1.2A
(nominal) peak current limit will be reached, which effectively limits the duty cycle to a lower value. Above that
load, the output voltage will decrease rapidly and in
reverse order the startup current limits will be invoked as
the output voltage falls through its various voltage thresholds. How far the output voltage drops depends on the
load V-I characteristics.
DE
The SC120 permits power up at input voltages from 0.85V
to 3.8V. Startup current limiting of the internal switching
n-channel and p-channel FET power devices protects
them from damage in the event of a short between OUT
and GND. As the output voltage rises, progressively lessrestrictive current limits are applied. This protection
unavoidably prevents startup into an excessive load.
L
Regulator Startup, Short Circuit Protection, and
Current Limits
IA
The EN pin is a high impedance logical input that can be
used to enable or disable the SC120 under processor
control. VEN < 0.2V will disable regulation, set the LX pin in
a high-impedance state (turn off both FET switches), and
turn on an active discharge device to discharge the output
capacitor via the OUT pin. VEN > 0.85V will enable the
output. The startup sequence from the EN pin is identical
to the startup sequence from the application of input
power.
Note that startup with a regulated active load is not the
same as startup with a resistive load. The resistive load
output current increases proportionately as the output
voltage rises until it reaches programmed VOUT/RLOAD, while
a regulated active load presents a constant load as the
output voltage rises from 0V to programmed VOUT. Note
also that if the load applied to the output exceeds an
applicable VOUT–dependent startup current limit or duty
cycle limit, the criterion to advance to the next startup
stage may not be achieved. In this situation startup may
pause at a reduced output voltage until the load is reduced
further.
NT
The Enable Pin
CO
N
FI
To begin, the p-channel FET between the LX and OUT pins
turns on with its current limited to approximately 150mA,
the short-circuit output current. When VOUT approaches VIN
(but is still below 1.7V), the n-channel current limit is set
to 350mA (the p-channel limit is disabled), the internal
oscillator turns on (approximately 200kHz), and a fixed
75% duty cycle PWM operation begins. (See the section
PWM Operation.) When the output voltage exceeds 1.7V,
normal fixed frequency variable duty cycle PWM operation begins, with the n-channel FET’s current limited to
350mA to prevent excessive output voltage overshoot. If
the n-channel FET current limit is exceeded, the on-state
ends immediately and the off-state begins, overriding the
output voltage regulation controller. This reduces the
duty cycle on a cycle-by-cycle basis. When VOUT is within
2% of the programmed regulation voltage, the n-channel
FET current limit is raised to 1.2A.
Once variable duty cycle PWM operation is initiated, the
output becomes independent of VIN and output regulation can be maintained for VIN as low as 0.7V, subject to the
maximum duty cycle and peak current limits. The duty
cycle must remain between 15% and 90% for the device
to operate within specification.
A reduction in input voltage, such as due to a discharging
battery, will lower the load current at which overload
occurs. Lower input voltage increases the duty cycle
required to produce a given output voltage. And lower
input voltage also increases the input current to maintain
the input power, which increases dissipative losses and
further increases the required duty cycle. Therefore an
increase in load current or a decrease in input voltage can
result in output overload.
Once an overload has occurred, the load must be
decreased to permit recovery. The conditions required for
PRELIMINARY
16
SC120
Applications Information (continued)
When both FET switches are simultaneously turned off, an
internal switch between the IN and LX pins is closed, providing a moderate resistance path across the inductor to
dampen the oscillations at the LX pin. This effectively
reduces EMI that can develop from the resonant circuit
formed by the inductor and the drain capacitance at LX.
where η is efficiency.
ΔIL is the inductor (and thus the input) peak-to-peak
current. Neglecting the n-channel FET RDS-ON and the
inductor DCR, for duty cycle D, and with T = 1/fosc,
'IL on
Component Selection
CO
N
FI
The SC120 provides optimum performance when a 4.7μH
inductor is used with a 10μF output capacitor. Different
component values can be used to modify PSAVE exit or
entry loads, modify output voltage ripple in PWM mode,
improve transient response, or to reduce component size
or cost.
Inductor Selection
The inductance value primarily affects the amplitude of
inductor current ripple (ΔI L). Reducing inductance
increases ΔI L. This raises the inductor peak current,
IL-max = IL-avg + ΔIL/2, where IL-avg is the inductor current averaged over a full on/off cycle. I L-max is subject to the
n-channel FET current limit ILIM(N), therefore reducing the
inductance may lower the output overload current threshold. Increasing ΔIL also lowers the inductor minimum
current, IL-min = IL-avg – ΔIL/2, thus raising the PSAVE entry
load current threshold. This is the output load below
which IL-min = 0, the boundary between continuous mode
and discontinuous mode PWM regulation, which signals
the SC120 controller to switch to PSAVE operation. In the
extreme case of VIN approaching VOUT, smaller inductance
can also reduce the PSAVE inductor burst-envelope current
ripple and voltage ripple.
1
L
³
DT
0
VIN dt
VIN u D u T
L
This is the change in IL during the on-state. During the
off-state, again neglecting the p-channel FET RDS-ON and
the inductor DCR,
DE
The anti-ringing circuitry is disabled between PSAVE
bursts.
1 VOUT u IOUT
u
K
VIN
IL avg
L
In PWM operation, the n-channel and p-channel FETs are
simultaneously turned off when the inductor current
reaches zero. They remain off for the zero-inductorcurrent portion of the off-state. Note that discontinuous
mode is a marginal-load condition, which if persistent will
trigger a transition to PSAVE operation.
IA
Anti-ringing Circuitry
The governing equations for inductor selection are the
following. Equating input power to output power, noting
that input current equals inductor current, and averaging
over a full PWM switching cycle,
NT
overload recovery are identical to those required for successful initial startup.
'IL off
1
L
T
³ V
DT
IN
VOUT dt
VIN VOUT u T 1 D
L
Note that this is a negative quantity, since VOUT > VIN and
0 < D < 1. For a constant load in steady-state, the inductor
current must satisfy ΔIL-on + ΔIL-off = 0. Substituting the two
expressions and solving for D, obtain D = 1 – VIN/VOUT.
Using this expression, and the positive valued expression
ΔIL = ΔIL-on for current ripple amplitude, obtain expanded
expression for IL-max and IL-min.
IL max,min
VOUT u IOUT
T
V
r
u IN u VOUT VIN VIN u K
2 u L VOUT
If the value of IOUT decreases until IL-min = 0, which is the
boundary of continuous and discontinuous PWM operation, the SC120 will transition from PWM operation to
PSAVE operation. Define this value of IOUT as IPSAVE-entry.
Setting the expression for IL-min to 0 and solving,
2
IPSAVE entry
PRELIMINARY
K u T § VIN ·
¨
¸ VOUT VIN 2 u L ¨© VOUT ¸¹
17
SC120
Applications Information (continued)
The value of the inductor determines the PSAVE entry
output load current. Evaluate IPSAVE-entry at the smallest and
largest expected values of VIN. If the input range includes
VIN = 2/3 VOUT, also determine IPSAVE-entry-max. If the largest VIN
exceeds approximately 90% of VOUT, then instead evaluate
PSAVE entry at VIN = 0.9VOUT. Since PSAVE exit will require
an unusually high output load current at high VIN. This was
explained in a previous section, therefore PSAVE entry
under this condition may not be relevant.
DCR
(Ω)
Rated
Current
(mA)
Tolerance
(%)
Dimensions
LxWxH
(mm)
4.7
0.4
500
10
4.5 x 3.2 x 2.6
Capacitor Selection
Input and output capacitors must be chosen carefully to
ensure that they are of the correct value and rating. The
output capacitor requires a minimum capacitance value
of 10μF at the programmed output voltage to ensure stability over the full operating range. This must be considered when choosing small package size capacitors as the
DC bias must be included in their derating to ensure this
required value. For example, a 10μF 0805 capacitor may
provide sufficient capacitance at low output voltages but
may be too low at higher output voltages. Therefore, a
higher capacitance value may be required to provide the
minimum of 10μF at these higher output voltages.
Additional output capacitance may be required for VIN
close to VOUT to reduce ripple in PSAVE mode and to ensure
stability in PWM mode, especially at higher output load
currents.
CO
N
FI
DE
The inductor selection should also consider the n-channel
FET current limit for the expected range of input voltage
and output load current. The largest IL-avg will occur at the
expected smallest VIN and largest IOUT. Determine the
largest allowable ΔIL, based on the largest expected IL-avg,
the minimum n-channel FET current limit, and the
inductor tolerance. Ensure that in the worst case,
IL-avg + ΔIL/2 < ILIM(N).
Murata
LQH43MN4R7K03L
Value
(μH)
L
Ku T 2
u u VOUT
L
27
Manufacturer/
Part #
IA
IPSAVE entry max
Table 1 — Recommended Inductors
NT
The programmed value of VOUT is constant. IPSAVE-entry is a
polynomial function of VIN. Equating dIPSAVE-entry/dVIN = 0
and solving for VIN reveals that there is one non-zero extremum of this function, a maximum, at VIN = 2/3 VOUT. Applying
this value of VIN,
These calculations include the parameter η, efficiency.
Efficiency varies with VIN, IOUT, and temperature. Estimate η
using the plots provided in this datasheet, or from experimental data, at the operating condition of interest when
computing the effect of a new inductor value on PSAVE
entry and I-limit margin.
Any chosen inductor should have low DCR, compared to
the RDS-ON of the FET switches, to maintain efficiency,
though for DCR << RDS-ON, further reduction in DCR will
provide diminishing benefit. The inductor ISAT value should
exceed the expected IL-max. The inductor self-resonant frequency should exceed 5×fosc. Any inductor with these
properties should provide satisfactory performance.
Low ESR capacitors such as X5R or X7R type ceramic
capacitors are recommended for input bypassing and
output filtering. Low-ESR tantalum capacitors are not recommended due to possible reduction in capacitance seen
at the switching frequency of the SC120. Ceramic capacitors of type Y5V are not recommended as their temperature coefficients make them unsuitable for this application.
Table 2 lists the manufacturer of the recommended
capacitor.
Table 2 — Recommended Capacitor
Manufacturer/
Part Number
Murata
GRM21BR60J226ME39B
Value
(μF)
Rated Voltage
(VDC)
Type
Case
Size
22
6.3
X5R
0805
Table 1 lists the manufacturers of recommended inductor
options.
PRELIMINARY
18
SC120
Applications Information (continued)
•
PCB Layout Considerations
Poor layout can degrade the performance of the DC-DC
converter and can contribute to EMI problems, ground
bounce, and resistive voltage losses. Poor regulation and
instability can result.
•
A few simple design rules can be implemented to ensure
good layout:
•
IA
L
Place the inductor and filter capacitors as close
to the device as possible and use short wide
traces between the power components.
COUT
FI
DE
NT
6.7mm
LX
CO
N
•
Route the output voltage feedback path away
from the inductor and LX node to minimize
noise and magnetic interference.
Maximize ground metal on the component side
to improve the return connection and thermal
dissipation. Separation between the LX node
and GND should be maintained to avoid coupling capacitance between the LX node and the
ground plane.
Use a ground plane with several vias connecting
to the component side ground to further reduce
noise interference on sensitive circuit nodes.
LX
VIN
GND
OUT
SC120
IN
VOUT
R1
5.2mm
FB
EN
(2
nd
layer)
R2
CIN
PRELIMINARY
19
SC120
Outline Drawing — MLPD-UT-6 1.5x2
DIMENSIONS
B
D
DIM
E
A2
C
A1
2
E1
0.50
0.00
.012
.063
.055
.083
.035
0.18
1.40
0.90
1.90
0.65
(.006)
.010
.059
-
.079
.031
.020 BSC
.012
.014
.016
6
.003
.004
NOM
(.152)
0.25
1.50
-
MAX
0.60
0.05
0.30
1.60
1.40
2.10
0.90
2.00
0.80
0.50 BSC
0.30
0.35
0.40
6
0.08
0.10
FI
bbb
C A B
CO
N
1.
MIN
.024
.002
bxN
e
NOTES:
MAX
DE
LxN
N
bbb
.007
.055
.035
.075
.026
NOM
-
MILLIMETERS
NT
D1
1
L
N
aaa
.020
.000
IA
SEATING
PLANE
aaa C
MIN
A
A1
A2
b
D
D1
E
E1
e
PIN 1
INDICATOR
(LASER MARK)
A
INCHES
L
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS TERMINALS.
PRELIMINARY
20
SC120
Land Pattern — MLPD-UT-6 1.5x2
H
R
DIMENSIONS
INCHES
C
(.077)
(1.95)
G
.047
1.20
H
.051
1.30
K
.031
0.80
P
.020
0.50
R
.006
0.15
X
.012
0.30
Y
.030
0.75
Z
.106
2.70
Z
(C)
G
K
Y
P
MILLIMETERS
NT
IA
X
L
DIM
NOTES:
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
DE
1.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
FI
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
CO
N
FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
PRELIMINARY
21