SEMTECH SC2677BITSTRT

SC2677B
Dual Synchronous Voltage Mode
Controller with Current Sharing Circuitry
POWER MANAGEMENT
Description
Features
The SC2677B is a versatile 2 phase, synchronous, voltage
mode PWM controller that can be used in two distinct ways.
First, the SC2677B is ideal for applications where point of
use output power exceeds any single input power budget.
Alternatively, the SC2677B can be configured as a dual
switcher. The SC2677B features a precise temperature
compensated voltage reference, cycle-by-cycle peak current limit, under voltage lockout over current protection,
and internal level-shifted high-side gate drive circuitry.
‹ 300kHz to 1MHz externally programmable
frequency operation
Soft Start and Enable function
Power Good output provided
Cycle-by-cycle peak current limit
Latch off for over current protection
Phase-shifted switchers minimize ripple
High efficiency operation, >90%
Programmable output(s) as low as 0.5V
Industrial temperature range
TSSOP-24 package
TSSOP-24 EDP package
‹ Bias voltage as low as 4.5V
‹ Adjustable phase shift between channels
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
In current sharing configuration, the SC2677B can produce a single output voltage from two separate input voltage sources (which can be different in voltage levels) while
maintaining current sharing between the two channels.
Current sharing is programmable to allow each input supply to be loaded differently per application requirements.
Two Phase, Current Sharing Controller
‹ Flexible, same or separate VIN
‹ Programmable current sharing
‹ Thermal distribution via multi-phase output
In dual switcher configuration, two feedback paths are provided for independent control of the separate outputs. The
device will provide a regulated output from flexibly configured inputs, such as 3.3V, 5V, 12V etc. The phasing between the two switchers is adjustable to minimize the input and output ripple.
Applications
Graphics cards
Peripheral add-in card
Dual-Phase power supply
Power supplies requiring two outputs
‹
‹
‹
‹
Typical Application Schematic
D2
CS1-
R51
CS1+
C63
C6
D1
R50
L1
M1
1
2
Vout1
C4
M3
R5
C19
C23
PW RGD
R8
ENABLE
CS1+
C28
CS1-
R13
13
14
DL1
DH1
R10
BSTC
15
16
BST1
18
19
17
COMP1
-IN1
PHASING
20
SS/ENA
22
23
21
PWRGD
GND
R14
PGND
C33
12
DL2
DH2
11
10
9
BST2
COMP2
8
-IN2
7
VCC
6
5
4
VREF
CS22
1
+IN2
SC2677B
FREQ
U1
3
R19
CS2+
Vin
CS1-
CS1+
24
C26
C25
R21
CS2+
R20
CS2C36
CS2C39
C38
R49
CS2+
C62
R18
R48
L2
1
2
M5
C43
D3
M7
Vout2
C57
C59
D4
Dual Independent outputs
Revision: Dec. 04, 2009
1
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SC2677B
Dual Synchronous Voltage Mode
Controller with Current Sharing Circuitry
POWER MANAGEMENT
Typical Application Schematic
D2
Vin3
CS1R51
CS1+
C63
C6
D1
R50
Vin1
L1
VP1
M1
1
2
Vout
C4
M3
C19
R5
C23
R8
PW RGD
ENABLE
CS1+ CS1C28
R13
BSTC
DL1
13
14
15
16
DH1
BST1
17
COMP1
19
18
-IN1
PHASING
20
SS/ENA
21
22
GND
PWRGD
23
R10
R14
PGND
C33
12
11
10
DL2
DH2
BST2
COMP2
9
8
-IN2
+IN2
7
VCC
6
5
VREF
4
CS2-
3
1
FREQ
SC2677B
CS2+
U1
2
R19
CS1-
CS1+
24
C26
C25
R21
CS2+ CS2C35
C36
VOUT
C37
VOUT
R22
R26
Vin3
R24
C38
C39
VP2
VP1
CS2-
R49
CS2+
D
C62
R48
L2
VP2
Vin2
1
2
M5
C43
C59
M7
D3
C57
D4
Vin3
Dual Input, Single output, Current share Mode
D2
CS1R51
CS1+
C63
C6
D1
R50
L1
VP1
M1
1
2
Vout
C4
M3
C19
R5
C23
PW RGD
R8
ENABLE
CS1+ CS1C28
R13
13
BSTC
14
DL1
16
15
DH1
COMP1
BST1
17
18
-IN1
19
PHASING
20
SS/ENA
21
GND
PWRGD
22
23
R10
R14
PGND
DL2
C33
12
11
10
DH2
BST2
9
COMP2
8
-IN2
7
+IN2
6
VCC
5
4
3
CS2-
VREF
FREQ
SC2677B
CS2+
U1
2
R19
1
Vin
CS1-
CS1+
24
C26
C25
R21
CS2+ CS2C35
C36
VOUT
C37
VOUT
R22
R26
R24
C38
C39
VP2
VP1
CS2-
R49
CS2+
D
C62
R48
L2
VP2
1
2
M5
C43
C59
D3
M7
C57
D4
Single Input/output, Current share Mode
2
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SC2677B
POWER MANAGEMENT
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical
Characteristics section is not implied.
P ar am et er
S y m b ol
Li mi ts
Units
V IN
-0.3 to 15
V
±1
V
BST1, BST2 to GN D
-0.3 to 30
V
BSTC to GN D
-0.3 to 20
V
-IN 1, +/-IN 2 to GN D
7
V
COMP1, COMP2 to GN D
7
V
DH1, DH2 to GN D
-0.3 to 30
V
DL1, DL2 to GN D
-0.3 to BSTC + 0.3
V
-3 p eak (50nS)
V
V CC to GN D
PGN D to GN D
(6)
CS1+, CS1-, CS2+, CS2PWRGD to GN D
PHA SIN G
SS/EN A to GN D
(1)
7
V
V CC + 0.3
V
7
V
-0.3 to 7
V
Thermal Resistance Junction to Case
TSSOP-24
TSSOP-24 EDP
θJC
17
5.5
°C/W
Thermal Resistance Junction to A mb ient
TSSOP-24
TSSOP-24 EDP
θJA
90
32
°C/W
Op erating A mb ient Temp erature Range
TA
-40 to 85
°C
Op erating Junction Temp erature Range
TJ
-40 to 125
°C
Storage Temp erature Range
TSTG
-65 to +150
°C
Lead Temp erature (Sold ering) 10 sec
T LE A D
300
°C
Electrical Characteristics
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, TJ = 25°C, VBSTC = VBST = 12V
P a r a met er
Mi n
Ty p
Ma x
Un i ts
0.495
0.500
0.505
V
VOUT = VFB, -40 to 125 C
0.492
0.500
0 .5 0 8
V
Supply Voltage
VCC
4.5
Supply Current
VCC = 5.0
10
mA
VCC Ramp up Threshold
2 .8 4
V
VCC
100
mV
0.5
V
Output Voltage
C on d i t i on s
VOUT = VFB
o
UVLO
UVLO Hysteresis
Reference
15
V
Reference Load Regulation
VREF source 10uA ~ 100uA
0 .2
%
Reference Line Regulation
5V < VCC < 15V
0.7
%
Output Line Regulation
Gain (Gm) (Error Amplifier)
5V < VIN < 15V
COMP pin source 100uA
Input Of fset Voltage (Slave Error Amplifier)
Max Current (Error Amplifier)
Input Bias Current
© 2009 Semtech Corp.
Source, Sink
-IN1, +IN2, -IN2
3
0.7
%
4
5
6.5
mA/V
-3
-1
0
mV
400
460
μA
2
μA
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SC2677B
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, TJ = 25°C, VBSTC = VBST = 12V
P ar am et er
Con d i t i on s
Und er Voltage Latching off Threshold
Oscillator Freq uency Range
Min
Ty p
M ax
Units
60
70
80
%
1000
kHz
550
kHz
300
RSET = 5kohm
450
500
Oscillator Max Duty Cycle
FOSC = 500kHz
86
90
%
Phasing of DH2 and DH1
V PHASING = 0.585V
180
°
Oscillator Freq uency
DH Sink Current
DH - PGN D = 3.5V
1.7
A
DH Sink Current
DH - PGN D = 2.5V
0.85
A
DH Source Current
BSTH - DH = 3.75V
1.7
A
DH Source Current
BSTH - DH = 3V
0.85
A
DL Sink Current
DL - PGN G = 3.5V
1.7
A
DL Sink Current
DL - PGN D = 2.5V
0.85
A
DL Source Current
BSTL - DL = 3.75V
1.7
A
DL Source Current
BSTL - DL = 3V
0.85
A
-40 to 0 C
DH Minimum on Time
Dead Time
Soft Star t Charge Current
300
o
N ote 5
50
Soft Star t End
Soft Star t Transition Threshold
(2)
0% d uty cycle
400
mV
100% d uty cycle
825
mV
Synchronous mod e
1.22
V
28
33
From OCP d etection to DH low
Inp ut Offset (Current Sense A mp lifier)
Inp ut Bias Current
ns
μA
OCP Trip Threshold
OCP Delay Time
120
50
(2)
Soft Star t Enab le
85
ns
37
mV
200
nS
+/-3
CS1+, CS1-, CS2+, CS2-
Pow er Good Threshold
V OUT ramp ing up
Pow er Good Pull Dow n
Sink Current = 2mA
83%
88%
mV
100
nA
93%
V OUT
0.4
V
Notes:
(1) Measured from 50% to 50% pulse amplitude.
(2) The soft start pin sources 50μA to an external capacitor. The converter operates in synchronous mode
above the soft start transition threshold and in asynchronous mode below it.
(4) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(5) 120ns maximum at 70°C.
(6) Under pulsing condition, the negative voltage can be -5V for no more than 40ns measured from 50% falling to 50% rising.
© 2009 Semtech Corp.
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SC2677B
POWER MANAGEMENT
Pin Configuration
Ordering Information
Top View
D e v i c e ( 1)
SC2677BITSTRT
P ack ag e
( 2)
SC2677BTETRT( 2)
TSSOP-24
TSSOP-24 EDP
SC2677BEV B-1
Current Share Evaluation Board
SC2677BEV B-2
Dual Channel Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel contains 2500 devices.
(2) Lead free package. Device is fully WEEE and RoHS
compliant.
(TSSOP-24 Pin)
Pin Descriptions
EXP
ANDED PIN DESCRIPTION
EXPANDED
Pin 1
4: (CS2+, CS1+)
24:
1,, 2
Current sense amplifier (for OCP protection) non-inverting
inputs.
Pin 2, 23: (CS2-, CS1-)
Current sense amplifier (for OCP protection) inverting
inputs.
Pin 3: (VREF)
Internal 0.5V reference. Connected to the + input of the
master channel error amplifier.
Pin 4: (FREQ)
External frequency adjustment. Connect a resistor to
AGND to set the switching frequency. Please see more
information in Application section.
Pin 5: (VCC)
Bias pin for the controller. Connect a ceramic decoupling
capacitor from this pin to AGND with minimum trace
length.
Pin 6: (+IN2)
“+” input of the slave error amplifier.
Pin 7, 18: (-IN2, -IN1)
“-” inputs of the error amplifiers.
Pin 8, 1
7: (COMP2, COMP1)
17
Compensation pins of the error amplifiers.
Pin 9, 1
6: (BST2, BST1)
16:
Supply pins for the high side drivers. Usually connected
to bootstrap circuit.
Pin 1
0, 1
10,
15:
5: (DH2, DH1)
© 2009 Semtech Corp.
Gate drive pins for the top MOSFETs. Requires a small
series resistor.
Pin 1
1, 1
4: (DL2, DL1)
11
14:
Gate drive pins for the bottom MOSFETs. Requires a
small series resistor.
Pin 12: (PGND)
Power GND. Return of the high side and low side gate
drivers.
Pin 1
3: (BSTC)
13:
Supply pin for bottom MOSFET gate drivers.
Pin 19: (PHASING)
This pin controls the phase shift between master and
slave for optimum noise immunity. Use a resistive
divider from the FREQ pin (pin 2) to AGND, and connect
the tap of the resistive divider to pin 17. Please see
more information in Application section.
Pin 20: (SS/ENA)
Soft start pin. Connect a ceramic capacitor from this pin
to AGND, and there is an internal current source charging up this capacitor during soft start. The PWM operation can be disabled if this pin is pulled low.
Pin 2
1: (PWRGD)
21:
Power good signal. This is an open collector output. It is
pulled low internally if output voltage is outside the
power good window.
Pin 22: (GND)
Analog GND. Return of the analog signals and bias of
the chip.
5
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SC2677B
POWER MANAGEMENT
Block Diagram
1.25V
50uA
Notes:
(1) Channel 1 is the Master and Channel 2 is the Slave in current sharing configuration.
(2) For dual output operation, tie +IN2 to VREF and the two PWM channels are independent.
© 2009 Semtech Corp.
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SC2677B
POWER MANAGEMENT
Application Information
Main Loop(s)
The controller provides a power good signal. This is an
open collector output, which is pulled low if the output
voltage is outside of the power good window.
t/Enable
Sof
Softt Star
Start/Enable
The Soft Start/Enable (SS/ENA) pin serves several
functions. If held below the Enable threshold, both channels are inhibited. DH1 and DH2 will be low, turning off
the top FETs. Between the Soft Start Enable threshold
and the Soft Start End threshold, the duty cycle is allowed
to increase. At the Soft Start End threshold, maximum
duty cycle is reached. In practical applications the error
amplifier will be controlling the duty cycle before the Soft
Start End threshold is reached. To avoid boost problems
during start-up in current share mode, both channels start
up in asynchronous mode, and the bottom FET body diode
is used for circulating current during the top FET off time.
When the SS/ENA pin reaches the Soft Start Transition
threshold, the channels begin operating in synchronous
mode for improved efficiency. The soft start pin sources
approximately 50uA and soft start timing can be set by
selection of an appropriate soft start capacitor value.
a) Two independent channels with either common
or different input voltages and different output
voltages. The two channels each have their own voltage feedback path from their own output. In this
mode, positive input of the error amplifier 2 is connected externally to Vref. If the application uses a
common input voltage, the sawtooth phase shift between the channels provides some measure of input
ripple current cancellation.
Freq
uency Se
requency
Sett and Phasing
The switching frequency can be programmed by connecting a resistor from the FREQ pin to AGND. The PHASING
pin controls the phase shift between the master sawtooth
and slave sawtooth which allows the adjustment of the
phase shift for maximum noise immunity by controlling
the timing between master and slave transition. A resistive divider is used from the FREQ pin to AGND and the
divided voltage is fed to the PHASING pin as depicted.
The offset of the current sharing error amplifier is
trimmed whthin the range of -2mV to 0mV. The polarity being such that the slave is OFF if the master
has no current.
© 2009 Semtech Corp.
7
13
BSTC
14
DL1
15
DH1
16
BST1
17
COMP1
18
-IN1
19
PHASING
20
SS/ENA
21
PWRGD
23
22
GND
DL2
DH2
BST2
COMP2
-IN2
PGND
12
11
10
9
8
7
VCC
FREQ
VREF
+IN2
6
5
4
3
1
Power Good
CS2-
SC2677B
CS2+
R19
CS1-
CS1+
24
R13
2
b) Two channels operating in current sharing mode
with common output voltage and either common input voltage or different input voltages. In this mode,
channel 1 operates as a voltage mode Buck controller,
as before, but error amplifier 2 monitors and amplifies the difference in voltage across the output current sense resistors of channel 1 and channel 2 (Master and Slave) and adjusts the Slave duty cycle to
match output currents. To controller also works well
for using the output choke winding resistance as current sensing element (please refer the application
schematic for details). The amount of the current of
the slave channel vs the master channel can be programmed according to the application. This feature
is especially useful when two input sources are used
and each source has its power budget.
U1
The SC2677B is a dual, voltage mode synchronous Buck
controller. The two separate channels are identical and
share only IC supply pins (Vcc and GND), output driver
ground (PGND) and pre-driver supply voltage (BSTC). They
also share a common oscillator generating a sawtooth
waveform for channel 1 and an dephased sawtooth for
channel 2. Channel 2 has both inputs of the error amplifier uncommitted and available externally. This allows the
SC2677B to operate in two distinct modes.
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SC2677B
POWER MANAGEMENT
Application Information(Cont.)
ICC
QGT
QG
FSW
N
(R13+R19) vs.Oscillator Frequency
Oscillator Frequency (kHz)
1000
900
800
700
It’s recommended that the below figure be performed to
ensure SC2677B under safe operation area.
600
500
400
QGT limitation (with loading)
300
4
6
8
10
12
14
16
18
20
(R13+R19) (kohm)
Vphasing vs Phase Shift
Q G T(nC )
180
160
140
Phase (deg)
: Supply current for controller.
: Total gate charge of all selected MOSFETs.
: Total gate charge of per selected MOSFETs.
: Switching frequency.
: Number of MOSFET.
120
100
80
60
40
20
0
0.55
620
580
540
500
460
420
380
340
300
260
220
180
140
100
60
20
SOA
5Vin
8.5Vin
12Vin
SOA
SOA
150
0.60
0.65
0.70
0.75
0.80
0.85
200
250
0.90
Over Current Protection
400
450
500
An example is shown below to demonstrate the
procedure introduced above.
Vin =12V
Fsw =250KHz
N =4(number of MOSFET)
Then
QGT = 108nC
QG = 27nC (per MOSFET)
Layout Guidelines
Controller Power Dissipation
Power and signal traces must be kept separated for noise
considerations. Feedback, current sense traces and analog ground should not cross any traces or planes carrying
high switching currents, such as in the input loop or the
phase node.
Controller power dissipation is generated by following
parameter; switching frequency, total gate charge of all
selected MOSFETs and supply voltage.
P = Vin * (ICC + QGT* FSW)
QGT = QG * N
The input loop, consisting of the input capacitors and both
MOSFETs must be kept as small as possible. Since all of
the high switching currents occur in the input loop, the
enclosed loop area must be kept small to minimize inductance and radiated and conducted noise emissions.
Where
Vin : Supply voltage for controller and driving
MOSFET.
© 2009 Semtech Corp.
350
Fsw(KHz)
Vphasing (V)
Current sense amplifiers sense the inductor DCR, and compare with an internal OCP reference. As over current being
detected, the current sense amplifier will trip the peak
current limit on cycle-by-cycle basis. If the over current
condition sustains, and the output voltage drops below
75% of its nominal voltage level, the PWM will be disabled
and the power supply be latched off with short amount of
delay. The latch can be reset by power cycling.
300
8
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SC2677B
POWER MANAGEMENT
Application Information(Cont.)
The IC must have a ceramic decoupling capacitor across
its supply pins, mounted as close to the device as possible.
The small ceramic, noise-filtering capacitors on the current sense lines should also be placed as close to the IC as
possible.
Designing for minimum trace length is not the only factor
for best design, often a optimum layout can be achieved
by keeping the wide trace and using proper layer stacking
to minimize the stray inductance.
It is important to keep the gate traces short, the IC must
be close to the power switches. It is recommended to use
at least 25 mil width or wider trace when. A good placement can help if the controller is placed in the middle of
the two PWM channels.
Grounding requirements are always important in a buck
converter layout, especially at high power. Power ground
(PGND) should be returned to the bottom MOSFET source
to provide the best gate current return path. Analog ground
(AGND) should be used for the anaglog returns such as
chip decoupling, frequency setiing, reference voltage (or
soft starting cap), and the compensation.
This AGND shape should be single point connected to the
PGND shape near the ground side of the output capacitors.
This will provide noise free analog ground for operation
stablity, and also provide best possible remote sensing for
the feedback voltage.
In case two output rails need to be regulated, the AGND
shape should single point connected to the geometric center of the PGND for the two point of loads. The single
ponit tie is a must to prevent the power current from flowing on the AGND shape, so that the analog circuitry in the
controller has an electrically quiet reference and to provide the greatest noise free operation. Keep in mind that
the AGND pin is never allowed to have bigger than 1V
voltage difference vs the PGND pin. This usually achievable by using a ground plane for PGND in PCB layout.
Using ground plane for PGND can reduce the physical separation between the two grounds, such that even the fast
current transitions in the PGND plane can not generate
voltage spikes exceeding the 1V level, therefore preventing unstable and erratic behavior from happening.
The feedback divider must be close to the IC and be returned to analog ground. Current sense traces must be
run parallel and close to each other and to analog ground.
© 2009 Semtech Corp.
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SC2677B
POWER MANAGEMENT
Evaluation Schematic
Dual Independent outputs
CS1-
R51
CS1+
M1
13K
C63
R50
7.32K
VP1
IPD13N03LA
+12V
220nF
Vout1
L1
8.8uH
[email protected]
DCR=8.83mohm
1000uF
1uF
D1 D1N4148
1.0
C9
C10
C19
1800uF
C4
IP D13N03LA
C1
4.7uF
R1
M3
C6
4.7uF 4.7uF
C21
1nF
D2
D1N4148
C23
R5
7.5K
C24
PWRGD
R9
10.0K
R11
10.0K
Q1
9.09K
1uF
C28
R13
4.42k
C27
R19
U1
R10
100nF
1.00K
12.4K
SC2677B
1
2
3
4
5
6
7
8
9
10
11
12
6.19K
C S2+
C S1+
C S2C S1VREF
G ND
PW R G D
F REQ
VCC
SS/ENA
+IN2
PH ASING
-IN2
-IN1
C O MP2
C O MP1
B ST 2
B ST1
D H2
D H1
D L2
D L1
PG N D
BSTC
Enable/Disable
Circuit(option)
C26
R14
O ption
24
23
22
21
20
19
18
17
16
15
14
13
1uF
CS1CS1+
2N3904
Enable
R8
C25
300
2N3904
Q2
0.1uF
R12
1uF
C33
47nF
C34
47pF
R21
C S2 C S2 +
4.53K
5.6K
R20
C38
0.1uF
+12V
1K
1uF
D5
R54
R31
3K
CS2C39
R49
CS2+
R48
4.02K
VP2
M5
220nF
R52
2K
R53
8K
1N4148
R55
4.7k
33.2K
C62
1uF
Q3
C50
1uF
S_ E n a b le
2.2
2N3906
C36
Delay Output
Circuit(option)
R18
Vout2
L2
4.7uH
IPD13N03LA
C59
M7
D4
C60
1nF
C47
C46
C57
1800uF
1000uF
1uF
4.7uF
4.7uF
D3
1N4148
4.7uF
C43
IP D13N03LA
C40
[email protected]
DCR=6.35mohm
R35
1.0
R36
0R0
1N4148
© 2009 Semtech Corp.
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SC2677B
POWER MANAGEMENT
Evaluation Board - Bill of materials
Dual Independent outputs
Item
Referen ce
Qu an ti ty
Descri p ti on
Par t
1
C1,C9,C10,C40,C46,C47
6
16V Cerami c Cap , X7R
4.7u F
2
C4,C43
2
16V A l u mi n u m El ectrol y ti c Cap .
1000u F/16V
3
C19,C57
2
16V A l u mi n u m El ectrol y ti c Cap .
1800u F/16V
4
C6,C23,C25,C28,C38,C39,C59,C50
8
16V Cerami c Cap , X7R
1u F
5
C21,C60
2
16V Cerami c Cap , X7R
1n F
6
C24,C36
2
16V Cerami c Cap , X7R
0.1u F
7
C26
1
16V Cerami c Cap , X7R
100n F
8
C33
1
16V Cerami c Cap , X7R
47n F
9
C34
1
16V Cerami c Cap , X7R
47p F
10
C62,C63
2
16V Cerami c Cap , X7R
220n F
11
L1
1
In d u ctor
8.8u H/4m oh m
12
L2
1
In d u ctor
4.7u H/4m oh m
13
M1,M3,M5,M7
4
30V N -Ch an n el MOSFET
IPD13N 03LA
14
D1,D2,D3,D4,D5
5
Smal l Si gn al Di od e
1N 4148
15
Q1,Q2
2
N PN Gen eral Pu rp ose A mp l i fi er
2N 3904
16
Q3
1
PN P Gen eral Pu rp ose A mp l i fi er
2N 3906
17
R1,R35
2
SM 5%
1oh m
18
R5
1
SM 5%
7.5K
19
R8
1
SM 5%
9.09K
20
R9,R11
2
SM 5%
10K
21
R10
1
SM 5%
1K
22
R12
1
SM 5%
300oh m
23
R13
1
SM 5%
4.42K
24
R14
1
SM 5%
12.4K
25
R18
1
SM 5%
5.6K
26
R19
1
SM 5%
6.19K
27
R20
1
SM 5%
1K
28
R21
1
SM 5%
4.53K
29
R31
1
SM 5%
2.2oh m
30
R36
1
SM 5%
0oh m
31
R48
1
SM 5%
4.02K
32
R49
1
SM 5%
33.2K
33
R50
1
SM 5%
7.32K
34
R51
1
SM 5%
13K
35
R52
1
SM 5%
2K
36
R53
1
SM 5%
8K
37
R54
1
SM 5%
3K
38
R55
1
SM 5%
4.7K
39
U1
1
PWM con trol l er
SC2677B
© 2009 Semtech Corp.
11
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SC2677B
POWER MANAGEMENT
Performance (Dual output)
Test condition:12Vin,[email protected] circuit, [email protected] 0A
Test condition:12Vin,[email protected], [email protected]
Vcc
Vcc
5Vout
3.3Vout
5Vout
PWRGD
3.3Vout
PWRGD
Test condition:12Vin,[email protected],[email protected]
Test condition:12Vin,[email protected], [email protected]
Vcc
5Vout
Vcc
5Vout
3.3Vout
3.3Vout
PWRGD
PWRGD
Test condition:12Vin,[email protected], [email protected]
DH1
DL1
DH2
DL2
© 2009 Semtech Corp.
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SC2677B
POWER MANAGEMENT
Performance (Dual output)
3.3V OCP
5V OCP
6.0
4.0
Vout2 (V)
Vout1 (V)
5.0
3.0
2.0
1.0
0.0
0
1
2
3
4
5
6
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
7
0
1
Load Current (A)
5
6
5
6
Load Current vs.Vcs2+ to Vout2
Load Current vs. Vcs1+ to Vout1
40
40
35
35
Vcs2+ to Vout2 (mV)
Vcs1+ to Vout1 (mV)
2
3
4
Load Current (A)
30
25
20
15
10
5
30
25
20
15
10
5
0
0
0
1
2
3
4
5
Load Current (A)
6
7
0
1
2
3
4
Load Current (A)
Ove ra ll S yste m Efficie ncy
96
94
Efficiency (%)
92
90
88
Io1+Io2
86
84
82
80
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Loa ding (A)
© 2009 Semtech Corp.
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SC2677B
POWER MANAGEMENT
Evaluation Schematic (Cont.)
Single output, Current share Mode
(1)
CS1-
R51
CS1+
M1
IPD09N03LA
+3.3V
5.76K
C63
R50
6.34K
VP1
220nF
Vout1
L1
2uH
[email protected]
DCR=4mohm
R1
C6
1800uF
D1N4148
D1N4148
D1
1.0
C9
4.7uF
C21
C10
4.7uF
1nF
C19
C20
1800uF
4.7uF
M3
1uF
1800uF
C4
IPD06N03LA
C1
D2
+12V
C23
R5
7.5K
C24
1uF
PWRGD
R11
10.0K
Q1
C28
1.00K
13
BSTC
14
R10
47nF
8.06K
C33
PGND
15
16
17
C26
R14
33nF
R21
12
DL1
DL2
DH2
10
11
DH1
BST1
BST2
9
19
18
8
-IN2
7
6
VCC
5
FREQ
4
VREF
3
CS2+
CS22
1
+IN2
SC2677B
5.9K
COMP2
COMP1
-IN1
PHASING
21
20
SS/ENA
22
U1
PWRGD
R19
23
24
CS1+
Enable/Disable
Circuit (option)
GND
R13
4.64k
CS1-
1uF
CS1+
2N3904
Enable
1.78K
1uF
300
2N3904
Q2
R8
C25
0.1uF
R12
CS1-
R9
10.0K
2.1K
CS2-
CS2+
R22
2.32K
R24
4.87K
C37
220nF
C36
C38
0.1uF
1uF
R31
VP1
VP2
C35
220nF
R26
4.3K
Vout
Vout
1uF
1N4148
C39
2.2
(1)
D5
CS2-
C62
CS2+
220nF
M5
VP2
R48
3K
L2
+5V
2uH
IPD09N03LA
C40
R35
1.0
C59
1nF
C47
C46
C56
C57
1800uF
C60
1800uF
D4
+12V
M7
4.7uF
1uF
4.7uF
D3
1N4148
IPD06N03LA
1800uF
4.7uF
C43
DCR=4mohm
R36
0R0
1N4148
Note (1) : Current Scale. Master channel current w eighting factor is around 0.68 * Io, Slaver is around 0.32 * Io
© 2009 Semtech Corp.
14
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SC2677B
POWER MANAGEMENT
Evaluation Board - Bill of materials
Single output, Current share Mode
Item
Reference
Quanti ty
Descri p ti on
Par t
1
C1,C9,C10,C40,C46,C47
6
16V Cerami c Cap , X7R
4.7uF
2
C4,C19,C20,C43,C56,C57
6
16V A lumi num Electroly ti c Cap .
1800uF/16V
3
C6,C23,C25,C28,C38,C39,C59
7
16V Cerami c Cap , X7R
1uF
4
C24,C36
2
16V Cerami c Cap , X7R
0.1uF
5
C26
1
16V Cerami c Cap , X7R
47nF
6
C33
1
16V Cerami c Cap , X7R
33nF
7
C35,C37,C62,C63
4
16V Cerami c Cap , X7R
220nF
8
L1,L2
2
Ind uctor
2uH/4m oh m
9
M1,M5
2
25V N -Ch annel MOSFET
IPD09N 03LA
10
M3,M7
2
25V N -Ch annel MOSFET
IPD06N 03LA
11
D1,D2,D3,D4,D5
5
Small Si gnal Di od e
1N 4148
12
Q1,Q2
2
N PN General Purp ose A mp li fi er
2N 3904
13
R1,R35
2
SM 5%
1oh m
14
R5
1
SM 5%
7.5K
15
R8
1
SM 5%
1.78K
16
R9,R11
2
SM 5%
10K
17
R10
1
SM 5%
1K
18
R12
1
SM 5%
300oh m
19
R13
1
SM 5%
4.64K
20
R14
1
SM 5%
8.06K
21
R19
1
SM 5%
5.9K
22
R21
1
SM 5%
2.1K
23
R22
1
SM 5%
2.32K
24
R24
1
SM 5%
4.87K
25
R26
1
SM 5%
4.3K
26
R31
1
SM 5%
2.2oh m
27
R36
1
SM 5%
0oh m
28
R48
1
SM 5%
3K
29
R50
1
SM 5%
6.34K
30
R51
1
SM 5%
5.76K
31
U1
1
PWM controller
SC2677B
© 2009 Semtech Corp.
15
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SC2677B
POWER MANAGEMENT
Performance (Single output)
Test condition: 3.3Vin/5Vin, Io=0A
Test condition: 3.3Vin/5Vin, Io=20A
Vout
Vout
SS/EN
Io
DH1
PWRGD
DL1
Test condition: 3.3Vin/5Vin, short circuit
Test condition: 3.3Vin/5Vin, Io=20A
Test condition: Io=20A
Vout
Vout
Io
Io
PWRGD
PWRGD
Test condition: Io=0 - 20A, T1=T2=3ms, RT=FT=2.5A/us
Test condition:3.3Vin/5Vin, [email protected]
Vout
Vout
Io
DH1
IL1
DL1
IL2
© 2009 Semtech Corp.
16
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SC2677B
POWER MANAGEMENT
Performance (Single output)
Test condition:3.3Vin/5Vin, [email protected]
OCP
1.4
1.2
Vout (V)
Vout
DH2
DL2
1.0
0.8
Vo (V)
0.6
0.4
0.2
0.0
0
5
10 15 20 25 30
Load Current (A)
3.3V and 5V Input Curre nt
Load Current vs.Vcs+to Vout (mV)
7
6
Input Current (A)
Vcs1+ to Vout1 (mV)
8
40
35
30
25
20
15
10
5
0
Vcs1+to Vout1
Vcs2+to Vout2
5
Iin3.3 A
4
Iin5 A
3
2
1
0
5
10
15
20
25
30
0
0
2
4
6
LoadCurrent (A)
8
10
12
14
16
18
20
Load Current (A)
Regualation Characteristic
Overall System Efficiency
1.4060
90
Efficiency (%)
Vout (V)
1.4055
1.4050
1.4045
Vout V
1.4040
1.4035
85
Io
80
75
70
1.4030
0
5
10
15
0
20
Load Current (A)
© 2009 Semtech Corp.
2
4
6
8
10 12 14 16 18 20
Load Current (A)
17
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SC2677B
POWER MANAGEMENT
Outline Drawing - TSSOP-24
A
DIM
D
e
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
N
2X E/2
E1
E
PIN 1
INDICATOR
ccc C
2X N/2 TIPS
1 2 3
e/2
B
.047
.002
.006
.031
.042
.007
.012
.003
.007
.303
.307
.311
.169
.173
.177
.252 BSC
.026 BSC
.018
.024
.030
(.039)
24
0
8
.004
.004
.008
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
7.70
7.80
7.90
4.30
4.40
4.50
6.40 BSC
0.65 BSC
0.45
0.60
0.75
(1.0)
24
0
8
0.10
0.10
0.20
D
aaa C
SEATING
PLANE
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
A2
C
A
H
A1
bxN
bbb
C A-B D
c
GAGE
PLANE
0.25
L
(L1)
SEE DETAIL
SIDE VIEW
DETAIL
A
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4.
REFERENCE JEDEC STD MO-153, VARIATION AD.
-A-
AND
-B-
TO BE DETERMINED AT DATUM PLANE -H-
Land Pattern - TSSOP-24
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
© 2009 Semtech Corp.
18
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SC2677B
POWER MANAGEMENT
Outline Drawing - TSSOP-24 EDP
A
D
e
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
N
DIM
2X E/2
E1
E
PIN 1
INDICATOR
ccc C
2X N/2 TIPS
1 2 3
e/2
B
D
aaa C
SEATING
PLANE
A2
C
A
A1
bxN
bbb
.047
.002
.006
.031
.042
.007
.012
.003
.007
.303
.307
.311
.169
.173
.177
.252 BSC
.211
.217
.221
.118
.112
.122
.026 BSC
.024
.018
.030
(.039)
24
0
8
.004
.004
.008
A
A1
A2
b
c
D
E1
E
F
H
e
L
L1
N
01
aaa
bbb
ccc
1.20
0.15
0.05
1.05
0.80
0.19
0.30
0.09
0.20
7.70
7.80
7.90
4.30
4.40
4.50
6.40 BSC
5.37
5.52
5.62
2.85
3.00
3.10
0.65 BSC
0.45
0.60
0.75
(1.0)
24
0
8
0.10
0.10
0.20
C A-B D
SEE DETAIL
SIDE VIEW
A
H
BOTTOM
VIEW
c
GAGE
PLANE
H
0.25
L
(L1)
DETAIL
F
01
A
OTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4.
REFERENCE JEDEC STD MO-153, VARIATION AD.
-A-
AND
-B-
TO BE DETERMINED AT DATUM PLANE
-H-
Land Pattern - TSSOP-24 EDP
F
X
DIM
(C)
H
G
C
F
G
H
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.225
.161
.126
.026
.016
.061
.283
(5.65)
5.72
4.10
3.20
0.65
0.40
1.55
7.20
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
© 2009 Semtech Corp.
19
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