SC403 6A EcoSpeedTM Integrated FET Regulator with Programmable LDO POWER MANAGEMENT Features Description Power System: Input voltage — 3V to 28V Internal or external bias voltage — 3V to 5V Integrated bootstrap switch Programmable LDO output — 200mA 1% reference tolerance -40 to +85 °C EcoSpeedTM architecture with pseudo-fixed frequency adaptive on-time control Logic Input/Output Control: Independent control EN for LDO and switcher Programmable VIN UVLO threshold Power good output Selectable ultrasonic power save mode Programmable soft start time Protections: Over-voltage and under-voltage TC compensated RDS(ON) sensed current limit Thermal shutdown Any ESR — SP, POSCAP, OSCON, and ceramic capacitors Package: Lead-free package — 5x5mm, 32-pin MLPQ Fully RoHS/WEEE compliant and halogen free The SC403 is a stand-alone synchronous EcoSpeedTM buck power supply which incorporates Semtech’s advanced patent-pending adaptive on-time control architecture to provide excellent light-load efficiency and fast transient response. It features integrated power MOSFETs, a bootstrap switch, and a programmable LDO in a 5x5mm package. The device is highly efficient and uses minimal PCB area. • • • • • • • • • • • The SC403 supports using standard capacitor types such as electrolytic or special polymer, in addition to ceramic, at switching frequencies up to 1MHz. The programmable frequency, synchronous operation, and selectable powersave provide high efficiency operation over a wide load range. • • • Additional features include a programmable soft-start, programmable cycle-by-cycle over-current limit protection, under and over-voltage protections, soft shutdown, and selectable power-save. The device also provides separate enable inputs for the PWM controller and LDO as well as a power good output for the PWM controller. • • Applications The wide input and bias voltage ranges, programmable frequency, and programmable LDO make the device extremely flexible and easy to use in a broad range of applications. The SC402 can be used in server computers and single cell or multi-cell battery systems in addition to traditional DC power supply applications. Office automation and computing Networking and telecommunication equipment Point of load power supplies and module replacement Typical Application Circuit ENABLE/PSAVE TON RILIM ILIM ENL RTON LXS PGOOD PGOOD VOUT 10Ω VEXT/LDO EN/PSV ENABLE LDO VDD L1 SC403 1µF VOUT LX CSOFT SS BST June 30, 2010 AGND PGND CIN LXBST VIN VIN RFB1 FB COUT + RFB2 CBST © 2010 Semtech Corporation SC403 6 SS 7 BST 8 PGOOD LX VIN PAD 2 9 10 11 12 13 14 15 16 PGND VIN LX PAD 3 PGND 5 AGND PAD 1 NC FBL 25 NC 4 26 LXBST AGND 27 VIN 3 28 VIN 2 VDD 29 Top View 1 VOUT ILIM 30 EN/PSV AGND 31 LXS TON 32 Ordering Information VIN FB ENL Pin Configuration 24 LX 23 LX 22 PGND 21 PGND 20 PGND 19 PGND 18 PGND 17 PGND Device Package SC403MLTRT(1)(2) MLPQ-32 5X5 SC403EVB Evaluation Board Notes: 1) Available in tape and reel only. A reel contains 3000 devices. 2) Lead-free package only. Device is RoHS/WEEE compliant and halogen free. SC403 MLPQ-32; 5x5, 32 LEAD Marking Information SC403 yyww xxxxxx xxxxxx yyww = Date Code xxxxxx = Semtech Lot Number xxxxxx = Semtech Lot Number SC403 Absolute Maximum Ratings Recommended Operating Conditions LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28 LX to PGND (V) (transient — 100ns max.) . . . . . . . -2 to +30 VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5 VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 to 5.5 EN/PSV, PGOOD, ILIM, to GND (V). . . . . . -0.3 to +(VDD + 0.3) Thermal Information SS, VOUT, FB, FBL, to GND (V). . . . . . . . . . -0.3 to +(VDD + 0.3) VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 Storage Temperature (°C). . . . . . . . . . . . . . . . . . . . . -60 to +150 TON to AGND (V). . . . . . . . . . . . . . . . . . . . . -0.3 to +(VDD - 1.5) Maximum Junction Temperature (°C). . . . . . . . . . . . . . . 150 ENL (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN Operating Junction Temperature (°C). . . . . . -40 to +125 BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 Thermal resistance, junction to ambient (2) (°C/W) BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35 High-side MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 AGND to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PWM controller and LDO thermal resistance . . . . . . 36 Peak IR Reflow Temperature (°C). . . . . . . . . . . . . . . . . . . . 260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless specified: VIN =12V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, VDD = +5V, per applicable Detailed Application Circuit Parameter Conditions Min Typ Max Sensed at ENL pin, rising edge 2.40 2.60 2.95 Sensed at ENL pin, falling edge 2.235 2.40 2.565 Units Input Supplies VIN UVLO Threshold(1) VIN UVLO Hysteresis V EN/PSV = High 0.2 V Measured at VDD pin, rising edge 2.5 3.0 Measured at VDD pin, falling edge 2.4 2.9 VDD UVLO Threshold V VDD UVLO Hysteresis VIN Supply Current 0.2 ENL , EN/PSV = 0V, VIN = 16V 8.5 Standby mode; ENL=VDD, EN/PSV = 0V 130 V 20 μA SC403 Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units ENL , EN/PSV = 0V 3 7 μA EN/PSV = VDD, no load (fSW = 25kHz), VFB > 750mV 2 EN/PSV = VDD, no load (fSW = 25kHz), VFB > 750mV 1 VDD = 5V, fSW = 250kHz, EN/PSV = floating , no load 4 VDD = 3V, fSW = 250kHz, EN/PSV = floating , no load 2.5 Input Supplies (continued) VDD Supply Current FB On-Time Threshold mA Static VIN and load, 0 to +85 °C 0.744 Static VIN and load, -40 to +85 °C 0.742 0.750 Continuous mode operation 0.756 V 0.758 V 1000 Frequency Range kHz Minimum fSW, EN/PSV = VDD, no load 25 Bootstrap Switch Resistance 10 Ω Switching MOSFET Resistance RDSON High Side FET 30 Low Side FET 10 mΩ Timing On-Time Continuous mode operation, VIN = 15V, VOUT = 5V, fSW= kHz, RTON = 300kΩ 2386 2650 2915 ns 3V < VDD < 4.5V (2) Minimum On-Time Minimum Off-Time 80 VDD = 5V 250 VDD = 3V 370 ns ns Soft-Start Soft-Start Current Soft-Start Voltage When VOUT reaches regulation 2.75 μA 1.5 V 500 kΩ Analog Inputs/Outputs VOUT Input Resistance SC403 Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units LX - PGND -3 0 +3 mV Current Sense Zero-Crossing Detector Threshold Power Good Power Good Threshold Start-Up Delay Time (between PWM enable and PGOOD going high) Soft Start Threshold Upper limit, VFB > internal 750mV reference +20 % Lower limit, VFB < internal 750mV reference -10 % VDD = 3V, CSS = 10nF 7 VDD = 5V, CSS = 10nF 12 When PGOOD logic switches high 64 % 5 µs Fault (noise immunity) Delay Time ms Leakage 1 Power Good On-Resistance 10 µA Ω Fault Protection VDD = 5V,RILIM = 6k Ω 5.1 VDD = 3V,RILIM = 6k Ω 4.3 Output Under-Voltage Fault VFB with respect to internal 750mV reference, 8 consecutive clocks -25 % Smart Power-save Protection Threshold VFB with respect to internal 750mV reference +10 % Over-Voltage Protection Threshold VFB with respect to internal 750mV reference +20 % 5 μs 10°C hysteresis 155 °C Logic Input High Voltage ENL, minimum level 1 V Logic Input Low Voltage ENL, maximum level 0.4 V Maximum level expressed in % of VDD 100 Minimum level expressed in % of VDD 45 Maximum level expressed in % of VDD 42 % Minimum level 1 V Valley Current Limit Over-Voltage Fault Delay Over-Temperature Shutdown A Logic Inputs/Outputs EN/PSV Input for PSAVE Operation EN/PSV Input for Forced Continuous Operation % SC403 Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Logic Inputs/Outputs (continued) Maximum level 0.4 Minimum level 0 EN/PSV Input for Disabling Switcher V EN/PSV Input Bias Current EN/PSV= VDD or AGND ENL Input Bias Current -8 VIN = 16V FBL, FB Input Bias Current 11 FBL, FB = VDD or AGND -1 LDO load = 10mA 0.735 +8 μA 18 μA +1 μA 0.765 V Linear Regulator (The LDO is shorted to the VDD pin internally.) FBL Accuracy LDO Current Limit 0.75 Short-circuit protection, VIN = 12V, VDD < 0.75V 65 Start-up and foldback, VIN = 12V, 0.75 < VDD < 90% of final VDD value 115 Operating current limit, VIN = 12V, VDD > 90% of final VDD value 135 mA 200 LDO to VOUT Switch-over Threshold (3) -140 +140 mV LDO to VOUT Non-switch-over Threshold (3) -450 +450 mV LDO to VOUT Switch-over Resistance LDO Drop Out Voltage (4) VOUT = +5V 2 Ω From VIN to VDD, VDD = +5V, ILDO = 100mA 1.2 V Notes: (1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND pins. The ENL voltage is compared to an internal reference. (2) For VDD less than 4.5V, the on-time may be limited by the VDD supply voltage and by the VIN. See the TON limitation and VDD supply voltage section in the applications Information. (3) The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that LDO will internally switchover to VOUT. The non-switch-over threshold is the minimum voltage differential between the LDO and VOUT pins which ensures that LDO will not switch-over to VOUT. (4) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the no load regulation value. SC403 Detailed Application Circuit-1 Internal LDO Used as Bias ENABLE LDO ENABLE/ PSAVE PGOOD RILIM 8.06KΩ RTON 130KΩ 1 2 FB VOUT VDD AGND FBL VIN SOFT BST 3 4 5 6 RLDO1 425KΩ RLDO2 1µF 1µF 3.3nF VIN 75KΩ 7 8 CBST PAD 2 1µF VIN +12V SC403 LX LX PGND PGND PGND PGND PGND PGND VIN VIN NC LXBST NC PGND PGND AGND VIN PAD 1 ENL TON AGND EN/PSV LXS ILIM PGOOD LX 32 31 30 29 28 27 26 25 LX 24 23 22 21 20 19 18 17 PAD 3 9 10 11 12 13 14 15 16 CIN 2 x 10µF (see note) RGND 0 1.5V @ 6A, 300kHz L1 1.5µH CFF 100pF + COUT 330µF 9mΩ VOUT 10nF RFB1 10KΩ RFB2 10KΩ Key Components Component Value Manufacturer Part Number CIN 2 x 10µF/25V Murata GRM32DR71E106KA12L www.murata.com COUT 330µF/9mΩ Panasonic EEF-SX0E331ER www.panasonic.com L1 1.5µH/6.7mΩ Cyntec PCMB065T-1R5MS www.cyntec.com Web NOTE: The quantity of 10µF input capacitors required varies with the application requirements. SC403 Detailed Application Circuit-2 External 5V Used as Bias ENABLE/ PSAVE PGOOD RILIM 8.06KΩ RTON 130KΩ 5V FB VOUT VDD AGND FBL VIN SOFT BST 3 4 5 6 10Ω 7 8 1µF 3.3nF VIN 1µF CBST 1µF VIN +12V PAD 2 SC403 LX LX PGND PGND PGND PGND PGND PGND VIN VIN NC LXBST NC PGND PGND AGND 1 2 VIN PAD 1 ENL TON AGND EN/PSV LXS ILIM PGOOD LX 32 31 30 29 28 27 26 25 LX 24 23 22 21 20 19 18 17 PAD 3 9 10 11 12 13 14 15 16 CIN 2 x 10µF (see note) RGND 0 1.5V @ 6A, 300kHz L1 1.5µH CFF 100pF + COUT 330µF 15mΩ VOUT 10nF RFB1 10KΩ RFB2 10KΩ Key Components Component Value Manufacturer Part Number CIN 2 x 10µF/25V Murata GRM32DR71E106KA12L www.murata.com COUT 330µF/9mΩ Panasonic EEF-SX0E331ER www.panasonic.com 1.5µH/6.7mΩ Cyntec PCMB065T-1R5MS www.cyntec.com L1 Web NOTE: The quantity of 10µF input capacitors required varies with the application requirements. SC403 Typical Characteristics Characteristics in this section are based on using the applicable Detailed Application Circuit. Efficiency vs. Load — Forced Continuous Mode 80 VOUT = 1.5V, VLDO = VDD = ENL = 5V, EN/P5V is floating 125 VIN = 12V VIN = 12V 40 1.0 VIN = 20V 20 0 0.001 0.100 IOUT (ADC) 1.000 VIN = 12V 0.0 10.000 25 1.425 0.001 0.010 2.5 VIN = 6V Efficiency 1.575 VOUT = 1.5V, VLDO = VDD = EN/PSV= ENL = 5V 150 125 VIN = 12V VIN = 20V 40 1.0 VOUT (VDC) 1.525 1.5 PLOSS (W) Efficiency (%) VIN = 12V VOUT VIN = 20V 1.500 1.475 0 0.001 0.5 VIN = 6V VIN = 12V 0.010 0.100 IOUT (ADC) 1.000 0.0 10.000 100 75 VIN = 6V VIN = 12V PLOSS VIN = 20V 0 10.000 1.000 1.550 2.0 60 20 0.100 IOUT (ADC) VOUT vs. Load — PSAVE Mode VOUT = 1.5V, VLDO = VDD = EN/PSV= ENL = 5V 80 50 VIN = 6V Efficiency vs. Load — PSAVE Mode 100 VPK-PK 1.450 VIN = 6V VIN = 12V 0.010 75 VIN = 6V VIN = 20V 0.5 VIN = 20V 1.500 VOUT 1.475 PLOSS 100 VIN = 20V VOUT (VDC) 1.5 PLOSS (W) Efficiency (%) 1.525 60 150 1.550 2.0 Efficiency VIN = 6V 1.575 2.5 VPKPK (mVRMS) VOUT = 1.5V, VLDO = VDD = ENL = 5V, EN/P5V is floating VPK-PK VIN = 20V 1.450 50 VPKPK (mVRMS) 100 VOUT vs. Load — Forced Continuous Mode 25 VIN = 6V 1.425 0.001 0.010 0.100 IOUT (ADC) 1.000 0 10.000 SC403 Typical Characteristics (continued) Characteristics in this section are based on using the applicable Detailed Application Circuit. Frequency vs. Load — PSAVE Mode Frequency vs. Load — Forced Continuous Mode 400 VOUT = 1.5V, VLDO = VDD = ENL = 5V, EN/P5V is floating 400 350 350 VIN = 12V 300 Frequency (kHZ) VOUT = 1.5V, VLDO = VDD = EN/PSV= ENL = 5V VIN = 6V Frequency (kHZ) 250 VIN = 20V 200 150 250 200 100 50 50 0.010 1.000 0.100 IOUT (ADC) 0 0.001 10.000 VOUT = 1.5V, VLDO = VDD = ENL = 5V, EN/P5V is floating 0.010 0.100 IOUT (ADC) 1.000 10.000 Frequency vs. Line — FCM Mode VOUT vs. Line — Forced Continuous Mode 1.575 VIN = 20V VIN = 6V 150 100 0 0.001 VIN = 12V 300 400 150 1.550 125 1.525 100 VOUT = 1.5V, VLDO = VDD = ENL = 5V, EN/P5V is floating 350 1.500 75 1.475 50 VPKPK 25 6.0 8.8 11.5 14.3 17.0 VIN (VDC) 250 200 150 100 1.450 1.425 Frequency (HZ) VOUT (VDC) VOUT VPK_PK (mVRMS) 300 19.8 22.5 25.3 0 28.0 22.5 25.3 28.0 50 0 6.0 8.8 11.5 14.3 17.0 VIN (VDC) 19.8 22.5 25.3 28.0 On Time vs. Line 1200 VOUT = 1.5V, VLDO = VDD = ENL = 5V, IOUT = 0A 1000 On-Time (ns) 800 600 3.3V 400 5V 200 0 6.0 8.8 11.5 19.8 14.3 17.0 Input Voltage (V) 10 SC403 Typical Characteristics (continued) Characteristics in this section are based on using the applicable Detailed Application Circuit. Ultrasonic Powersave Mode — No Load VIN = 12V, VOUT = 1.5V, IOUT = 0A, VLDO = VDD = EN/PSV= ENL = 3.3V Forced Continuous Mode — No Load VIN = 12V, VOUT = 1.5V, IOUT = 0A, VLDO = VDD = ENL = 3.3V, EN/PSV= floating (20mV/div) (20mV/div) (10V/div) (10V/div) Time (10µs/div) Time (10µs/div) Self-Biased Start-Up — Power Good True Enabled Loaded Output VIN = 0V to 12V step, VOUT = 1.5V, IOUT = 0A, VLDO = VDD = EN/PSV= ENL = 3.3V VIN = 12V, VOUT = 1.5V, IOUT = 1A, VLDO = VDD = ENL = EN/PSV= floating (10V/div) (10mV/div) (500mV/div) (500mV/div) (2V/div) (2V/div) (5V/div) (5V/div) Time (400µs/div) Time (400µs/div) 11 SC403 Typical Characteristics (continued) Characteristics in this section are based on using the applicable Detailed Application Circuit. Output Under-voltage Response — Normal Operation VIN = 12V, VOUT = 1.5V, IOUT = 0A, VLDO = VDD = ENL = 3.3V, floating EN/PSV Output Over-current Response — Normal Operation VIN = 12V, VOUT = 1.5V, VLDO = VDD = ENL = 3.3V, EN/PSV= floating; IOUT ramped to trip point (500mV/div) (10V/div) (500mV/div) (5A/div) (10V/div) (5V/div) (5V/div) Time (100µs/div) Time (100µs/div) Shorted Output Response — Normal Operation Shorted Output Response — Soft-start Operation VIN = 12V, VOUT = 1.5V, VLDO = VDD = ENL = 3.3V, EN/P5V is floating VIN = 12V, VOUT = 1.5V, IOUT = 0A, VLDO = VDD = EN/PSV= ENL = 3.3V (1V/div) (1V/div) (10A/div) (10A/div) (10V/div) (5V/div) (5V/div) (5V/div) Time (40µs/div) Time (400µs/div) Transient Response VIN = 12V, VOUT = 1.5V, IOUT = 0A to 7A, VLDO = VDD = EN/PSV= ENL = 3.3V (10mV/div) (50mV/div) (5A/div) Time (40µs/div) 12 SC403 Pin Descriptions Pin # Pin Name Pin Function 1 FB 2 VOUT Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin. 3 VDD Bias supply for the IC — when using the internal LDO as a bias power supply, the VDD is the LDO output. When using an external power supply to bias the IC, the LDO output should be disabled. 4, 30, PAD 1 AGND 5 FBL Feedback input for the internal LDO — connect to an external resistor divider from VDD to AGND to program the LDO output. 6, 9-11, PAD 2 VIN Input supply voltage 7 SS The soft start time is programmed by an internal current source charging a capacitor on this pin. 8 BST Bootstrap pin — connect a capacitor of at least 100nF from BST to LX to develop the floating supply for the high-side gate drive. 12 NC No connection 13 LXBST 23-25, PAD 3 LX Switching (phase) node 14 NC No connection 15-22 PGND Power ground 26 PGOOD 27 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS. 28 LXS LX sense — connects to RILIM. 29 EN/PSV 31 TON On-time programming input — set the on-time by connecting through a resistor to AGND. 32 ENL Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic signal for logic control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND pins. Feedback input for switching regulator used to program the output voltage — connect to an external resistor divider from VOUT to AGND. Analog ground LX Boost — connect to the BST capacitor. Open-drain power good indicator — high impedance indicates power is good. An external pull-up resistor is required. Enable/power-save input for the switching regulator — connect to AGND to disable the switching regulator. Float to operate in forced continuous mode (PSAVE disabled). Connect to VDD to operate with ultrasonic PSAVE mode enabled. 13 SC403 Block Diagram PGOOD EN/PSV VIN 29 A 26 VDD VDD AGND D Control & Status Reference VDD VIN Bootstrap Switch DL SS FB Gate Drive Control On-- time Generator 1 FB Comparator TON 31 VOUT 2 VDD DL Zero Cross Detector Valley Current Limit 3 NC B LX 13 LXBST 28 LXS C PGND 27 ILIM Lo-side MOSFET A VIN Y B LDO 14 NC VLDO Switchover MUX FBL 12 Bypass Comparator VDD VDD BST Hi-side MOSFET Soft Start 7 8 5 32 ENL A = connected to pins 6, 9-11, PAD 2 B = connected to pins 23-25, PAD 3 C = connected to pins 15-22 D = connect to pins 4, 30, PAD 1 14 SC403 Applications Information Synchronous Buck Converter The SC403 is a step down synchronous DC-DC buck converter with integrated power MOSFETs and a 200mA programmable LDO. The device operates at a current up to 6A at very high efficiency. A space saving 5x5 (mm) 32-pin package is used. The programmable operating frequency of up to 1MHz enables optimizing the configuration for PCB area and efficiency. The buck controller uses a pseudo-fixed frequency adaptive on-time control. This control method allows fast transient response which permits the use of smaller output capacitors. The ripple voltage generated at the output capacitor ESR is used as a PWM ramp signal. This ripple is used to trigger the controller on-time. VLX Shutdown The SC403 can be shutdown by pulling either VDD or EN/ PSV pin below its threshold. When using an external supply voltage for VDD, the VDD pin must be deactivated while the VIN voltage is still present. A 10Ω resistor must be placed between the external VDD supply and the VDD pin to avoid damage to the device. When the VDD pin is active and EN/PSV is at low logic level, the output voltage discharges through an internal FET. VFB FB Threshold VLX VOUT L Q2 ESR + The SC403 requires two input supplies for normal operation: VIN and VDD. VIN operates over a wide range from 3V to 28V. VDD requires a supply voltage between 3V to 5V that can be an external source or the internal LDO from VIN. The SC403 initiates a start up when VIN, VDD, and EN/PSV pins are above the applicable thresholds. When using an external bias supply for the VDD voltage, it is recommended that the VDD is applied to the device only after the VIN voltage is present because VDD cannot exceed VIN at any time. A 10Ω resistor must be placed between the external VDD supply and the VDD pin to avoid damage to the device during power-up and or shutdown situations where VDD could exceed VIN unexpectedly. CIN Q1 Input Voltage Requirements Power Up Sequence TON VIN FB COUT Figure 1 — PWM Control Method, VOUT Ripple The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the highside MOSFET. The pulse period is determined by VOUT and VIN. The period is proportional to output voltage and inversely proportional to input voltage. With this adaptive on-time arrangement, the device automatically anticipates the on-time needed to regulate VOUT for the present VIN condition and at the selected frequency. The advantages of adaptive on-time control are: • • • • • Predictable operating frequency compared to other variable frequency methods. Reduced component count by eliminating the error amplifier and compensation components. Reduced component count by removing the need to sense and control inductor current. Fast transient response — the response time is controlled by a fast comparator instead of a typically slow error amplifier. Reduced output capacitance due to fast transient response Psuedo-fixed Frequency Adaptive On-time Control The PWM control method used by the SC403 is pseudofixed frequency, adaptive on-time, as shown in Figure 1. 15 SC403 Applications Information (continued) One-Shot Timer and Operating Frequency One-shot timer operation is shown in Figure 2. The FB Comparator output goes high when VFB is less than the internal 750mV reference. This feeds into the gate drive and turns on the high-side MOSFET, and starts the oneshot timer. The one-shot timer uses an internal comparator and a capacitor. One comparator input is connected to VOUT, the other input is connected to the capacitor. When the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to VIN. When the capacitor voltage reaches VOUT, the on-time is completed and the high-side MOSFET turns off. FB Comparator FB 750mV + VOUT VIN RTON Gate Drives One-Shot Timer DH Q1 VLX DL Q2 VOUT L ESR COUT + FB This method automatically produces an on-time that is proportional to VOUT and inversely proportional to VIN. Under steady-state conditions, the switching frequency can be determined from the on-time by the following equation. VOUT TON u VIN The SC403 uses an external resistor to set the on-time which indirectly sets the frequency. The on-time can be programmed to provide an operating frequency from 200kHz to 1MHz using a resistor between the TON pin and ground. The resistor value is selected by the following equation. ( t ON 10ns) u VIN 25pF u VOUT The maximum RTON value allowed is shown by the following equation. RTON _ MAX VIN _ MIN 10 u 1.5PA VFB falls below the 750mV reference The zero cross detector senses that the voltage on the LX node is below ground. Power save is activated eight cycles after a zero crossing is detected. For VDD below 4.5V, the TON accuracy may be limited by the input voltage. VIN Figure 2 — On-Time Generation RTON • • TON limitations and VDD Supply Voltage On-time = K x RTON x (VOUT/VIN) fSW Immediately after the on-time, the DL (drive signal for the low side FET) output drives high to turn on the low-side MOSFET. DL has a minimum high time of ~320ns, after which DL continues to stay high until one of the following occurs: The original RTON equation is accurate if VIN satisfies the relationship over the entire VIN range, as follows. VIN < (VDD - 1.6V) x 10 If VIN exceeds (VDD - 1.6V) x 10, for all or part of the VIN range, the RTON equation is not accurate. In all cases where VIN > (VDD - 1.6V) x 10, the RTON equation must be modified, as follows. (TON 10ns) u (VDD 1.6V) u 10 25pF u VOUT RTON Note that when VIN > (VDD - 1.6V) x 10 , the actual on-time is fixed and does not vary with VIN. When operating in this condition, the switching frequency will vary inversely with VIN rather than approximating a fixed frequency. VOUT Voltage Selection The switcher output voltage is regulated by comparing VOUT as seen through a resistor divider at the FB pin to the internal 750mV reference voltage, see Figure 3. VOUT R1 To FB pin R2 Figure 3 — Output Voltage Selection 16 SC403 Applications Information (continued) Note that this control method regulates the valley of the output ripple voltage, not the DC value. The DC output voltage VOUT is offset by the output ripple according to the following equation. VOUT § R · §V · 0.75 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸ R 2 © ¹ 2 ¹ © FB Ripple Voltage (VFB) FB threshold (750mV) DC Load Current Inductor Current When a large capacitor is placed in parallel with R1 (CTOP) VOUT is shown by the following equation. VOUT § R · §V · 0.75 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸ u © R2 ¹ © 2 ¹ 1 (R1ZCTOP )2 § R u R1 · 1 ¨¨ 2 ZCTOP ¸¸ © R 2 R1 ¹ On-time (TON) 2 Enable and Power Save Input The EN/PSV input is used to enable or disable the switching regulator and the LDO. When EN/PSV is low (grounded), the switching regulator is off and in its lowest power state. When off, the output of the switching regulator soft-discharges the output into a 15Ω internal resistor via the VOUT pin. When EN/PSV is allowed to float, the pin voltage will float to 33% of the voltage at VDD. The switching regulator turns on with PSAVE (power save) disabled and all switching is in forced continuous mode. When EN/PSV is high (above 45% of the voltage at VDD), the switching regulator turns on with ultrasonic powersave enabled. The ultrasonic PSAVE operation maintains a minimum switching frequency of 25kHz, for applications with stringent audio requirements. Forced Continuous Mode Operation The SC403 operates the switcher in FCM (Forced Continuous Mode) by floating the EN/PSV pin (see Figure 4). In this mode one of the power MOSFETs is always on, with no intentional dead time other than to avoid crossconduction. This feature results in uniform frequency across the full load range with the trade-off being poor efficiency at light loads due to the high-frequency switching of the MOSFETs. DH is the gate signal driving the upper MOSFET. DL is the lower gate signal driving the lower MOSFET. DH on-time is triggered when VFB reaches the FB Threshold. DH DL DL drives high when on-time is completed. DL remains high until VFB falls to the FB threshold. Figure 4 — Forced Continuous Mode Operation Ultrasonic PSAVE Operation The SC403 provides ultrasonic PSAVE operation at light loads, with the minimum operating frequency fixed at 25kHz. This is accomplished using an internal timer that monitors the time between consecutive high-side gate pulses. If the time exceeds 40µs, DL drives high to turn the low-side MOSFET on. This draws current from VOUT through the inductor, forcing both VOUT and VFB to fall. When VFB drops to the 750mV threshold, the next DH on-time is triggered. After the on-time is completed the high-side MOSFET is turned off and the low-side MOSFET turns on. The low-side MOSFET remains on until the inductor current ramps down to zero, at which point the low-side MOSFET is turned off. 17 SC403 Applications Information (continued) Because the on-times are forced to occur at intervals no greater than 40µs, the frequency will not fall below ~25kHz. Figure 5 shows ultrasonic PSAVE operation. VOUT drifts up to due to leakage current flowing into COUT Smart Power Save Threshold (825mV) VOUT discharges via inductor and low-side MOSFET Normal VOUT ripple FB threshold Minimum fSW ~ 20kHz DH and DL off FB Ripple Voltage (VFB) FB threshold (750mV) High-side Drive (DH) Single DH on-time pulse after DL turn-off (0A) Inductor Current Low-side Drive (DL) On-time (TON) DH On-Time is triggered when VFB reaches the FB Threshold DH DL turns on when Smart PSAVE threshold is reached Normal DL pulse after DH on-time pulse DL turns off when FB threshold is reached Figure 6 — Smart PSAVE 50µsec time-out SmartDriveTM DL After the 50µsec time-out, DL drives high if VFB has not reached the FB threshold. Figure 5 — Ultrasonic PSAVE Operation Smart PSAVE Protection Active loads may leak current from a higher voltage into the switcher output. Under light load conditions with PSAVE enabled, this can force VOUT to slowly rise and reach the over-voltage threshold, resulting in a hard shutdown. Smart PSAVE prevents this condition. When the FB voltage exceeds 10% above nominal, the device immediately disables PSAVE, and DL drives high to turn on the low-side MOSFET. This draws current from VOUT through the inductor and causes VOUT to fall. When VFB drops back to the 750mV trip point, a normal tON switching cycle begins. This method prevents a hard OVP shutdown and also cycles energy from VOUT back to VIN. It also minimizes operating power by avoiding forced conduction mode operation. Figure 6 shows typical waveforms for the Smart PSAVE feature. For each DH pulse the DH driver initially turns on the highside MOSFET at a lower speed, allowing a softer, smooth turn-off of the low-side diode. Once the diode is off and the LX voltage has risen 1V above PGND, the SmartDrive circuit automatically drives the high-side MOSFET on at a rapid rate. This technique reduces switching power loss while maintaining high efficiency and also avoids the need for snubbers or series resistors in the gate drive. Current Limit Protection Programmable current limiting is accomplished by using the RDSON of the lower MOSFET for current sensing. The current limit is set by the RILIM resistor. The RILIM resistor connects from the ILIM pin to the LXS pin which is also the drain of the low-side MOSFET. When the low-side MOSFET is on, an internal ~10μA current flows from the ILIM pin and through the RILIM resistor, creating a voltage drop across the resistor. While the low-side MOSFET is on, the inductor current flows through it and creates a voltage across the RDSON. The voltage across the MOSFET is negative with respect to ground. If this MOSFET voltage drop exceeds the voltage across RILIM, the voltage at the ILIM pin will be negative and current limit will activate. The current limit then keeps the low-side MOSFET on and will not allow another high-side on-time, until the current in the low-side MOSFET reduces enough to bring the ILIM voltage back up to zero. This method regulates the inductor valley current at the level shown by ILIM in Figure 7. 18 SC403 Inductor Current Applications Information (continued) IPEAK ILOAD ILIM Time Figure 7 — Valley Current Limit Setting the valley current limit to 6A results in a peak inductor current of 6A plus the peak-to-peak ripple current. In this situation, the average (load) current through the inductor is 6A plus one-half the peak-to-peak ripple current. The internal 10μA current source is temperature compensated at 4100ppm in order to provide tracking with the RDSON. The RILIM value is calculated by the following equation. t SS C SS u 1 .5 V 2.75PA The voltage at the SS pin continues to ramp up and eventually is equal to 64% of VDD. After soft start completes, the FB pin voltage is compared to an internal reference of 0.75V. The delay time between the VOUT regulation point and PGOOD going high is shown by the following equation. t PGOOD-DELAY 0.64 u VDD 1.5 V 2.75PA (10mV/div) (500mV/div) (2V/div) (5V/div) RILIM = 1176 x ILIM x [0.088 x (5V - VDD) + 1] (Ω) where ILIM is in Amps. When selecting a value for RILIM do not exceed the absolute maximum voltage value for the ILIM pin. Note that because the low-side MOSFET with low RDSON is used for current sensing, the PCB layout, solder connections, and PCB connection to the LX node must be done carefully to obtain good results. RILIM should be connected directly to LXS (pin 28). Soft-Start of PWM Regulator SC403 has a programmable soft-start time that is controlled by an external capacitor at the SS pin. After the controller meets both UVLO and EN/PSV thresholds, the controller has an internal current source of 2.75µA flowing through the SS pin to charge the capacitor. During the start up process (Figure 8), 50% of the voltage at the SS pin is used as the reference for the FB comparator. The PWM comparator issues an on-time pulse when the voltage at the FB pin is less than 50% of the SS pin. As result, the output voltage follows the SS start voltage. The output voltage reaches and maintains regulation when the soft start voltage is > 1.5V. The time between the first LX pulse and when VOUT meets regulation is the soft start time (tSS). The calculation for the soft-start time is shown by the following equation. Time (400µs/div) Figure 8 — Soft-start Timing Diagram Pre-Bias Startup SC403 can start up as if in a soft-start condition with an existing output voltage level. The soft start time is still the same as normal start up (when the output voltage starts from zero). The output voltage starts to ramp up when one-half of the voltage at SS pin meets the pre-charge FB voltage level. Pre-bias startup is achieved by turning off the lower gate when the inductor current falls below zero. This method prevents the output voltage from decreasing. Power Good Output The PGOOD (power good) output is an open-drain output which requires a pull-up resistor. When the voltage at the FB pin is 10% below the nominal voltage, PGOOD is pulled low. It is held low until the output voltage returns above 92% of nominal. PGOOD will transition low if the VFB pin exceeds +20% of nominal, which is also the over-voltage shutdown threshold. PGOOD also pulls low if the EN/PSV pin is low when VDD voltage is present. 19 SC403 Applications Information (continued) Output Over-Voltage Protection Over-voltage protection becomes active as soon as the device is enabled. The threshold is set at 750mV + 20% (900mV). When VFB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off, until the EN/PSV input is toggled or VDD is cycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Output Under-Voltage Protection When VFB falls 25% below its nominal voltage (falls to 562.5mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to tristate the MOSFETs. The controller stays off until EN/PSV is toggled or VDD is cycled. VDD UVLO, and POR A minimum 0.1μF capacitor referenced to AGND is required along with a minimum 1.0μF capacitor referenced to PGND to filter the gate drive pulses. Refer to the layout guidelines section for component placement suggestions. LDO ENL Functions The ENL input is used to control the internal LDO. When ENL is low (grounded), the LDO is off. When ENL is above the V IN UVLO threshold, the LDO is enabled and the switcher is also enabled if EN/PSV and VDD meet the thresholds. The ENL pin also acts as the switcher UVLO (under-voltage lockout) for the VIN supply. The VIN UVLO voltage is programmable via a resistor divider at the VIN, ENL and AGND pins. UVLO (Under-Voltage Lock-Out) circuitry inhibits switching and tri-states the DH/DL drivers until VDD rises above 3.0V. An internal POR (Power-On Reset) occurs when VDD exceeds 3.0V, which resets the fault latch and soft-start counter to prepare for soft-start. The SC403 then begins a soft-start cycle. The PWM will shut off if VDD falls below 2.4V. If the ENL pin transitions from high to low within 2 switching cycles and is less than 1V, then the LDO will turn off but the switcher remains on. If the ENL goes below the VIN UVLO threshold and stays above 1V, then the switcher will turn off but the LDO remains on. The VIN UVLO function has a typical threshold of 2.6V on the VIN rising edge. The falling edge threshold is 2.4V. LDO Regulator Note that it is possible to operate the switcher with the LDO disabled, but the ENL pin must be below the logic low threshold (0.4V maximum). In this case, the UVLO function for the input voltage cannot be used. The table below summarizes the function of the ENL and EN pins, with respect to the rising edge of ENL. SC403 has an option to bias the switcher by using an internal LDO from VIN. The LDO output is connected to VDD internally. The output of the LDO is programmable by using external resistors from the VDD pin to AGND. The feedback pin (FBL) for the LDO is regulated to 750mV (see Figure 9). VDD RLDO1 To FBL pin RLDO2 Figure 9 — LDO Start-Up EN ENL LDO status Switcher status low high low high low high low, < 0.4V low, < 0.4V high, < 2.6V high, < 2.6V high, > 2.6V high, > 2.6V off off on on on on off on off off off on The LDO output voltage is set by the following equation. VLDO · § R 750mV u ¨¨1 LDO1 ¸¸ RLDO 2 ¹ © 20 SC403 Applications Information (continued) Figure 10 shows the ENL voltage thresholds and their effect on LDO and switcher operation. VVLDO Final Voltage regulating with ~ 200mA current limit 90% of VVLDO Final ENL voltage LDO on Switcher on if EN = high Constant current startup @ ~ 115mA 0.7V Short-circuit Protection @ ~ 65mA 2.6V VIN UVLO hysteresis 2.4V LDO on Switcher off by VIN UVLO ENL low threshold (min 0.4V) LDO off Switcher on if EN = high AGND Figure 10 — ENL Threshold Before start-up, the LDO checks the status of the following signals to ensure proper operation can be maintained. 1. ENL pin 2. VIN input voltage When the ENL pin is high and VIN is above the UVLO point, the LDO will begin start-up. During the initial phase, when the VDD voltage (which is the LDO output voltage) is less than 0.75V, the LDO initiates a current-limited start-up (typically 65mA) to charge the output capacitors while protecting from a short circuit event. When VDD is greater than 0.75V but still less than 90% of its final value (as sensed at the FBL pin), the LDO current limit is increased to ~115mA. When VDD has reached 90% of the final value (as sensed at the FBL pin), the LDO current limit is increased to ~200mA and the LDO output is quickly driven to the nominal value by the internal LDO regulator. It is recommended that during LDO start-up to hold the PWM switching off until the LDO has reached 90% of the final value. This prevents overloading the current-limited LDO output during the LDO start-up. Due to the initial current limitations on the LDO during power up (Figure 11), any external load attached to the VDD pin must be limited to 20mA before the LDO has reached 90% of it final regulation value. Figure 11 — LDO Start-Up LDO Switch-Over Operation The switch-over function is provided to increase efficiency by using the more efficient DC-DC converter to power the LDO output, avoiding the less efficient LDO regulator when possible. The switch-over function connects the VDD pin directly to the VOUT pin using an internal switch. When the switch-over is complete the LDO is turned off, which results in power savings and maximizes efficiency. If the LDO output is used to bias the SC403, then after switch-over the device is self-powered from the switching regulator with the LDO turned off. The switch-over logic waits for 32 switching cycles before it starts the switch-over. When the LDO is already in regulation and the DC-DC converter is later enabled, as soon as the PGOOD output goes high, the 32 cycles are started. The voltages at the VDD and VOUT pins are then compared; if the two voltages are within ±300mV of each other, the VDD pin connects to the VOUT pin using an internal switch, and the LDO is turned off. Switch-over Limitations on VOUT, ENL, and VDD Because the internal switch-over circuit always compares the VOUT and VDD pins at start-up, there are limitations on permissible combinations of these pins. Consider the case where VOUT is programmed to 3.0V and VLDO is programmed to 3.3V. After start-up, the device would connect VOUT to VDD and disable the LDO, since the two voltages are within the ±300mV switch-over window. To avoid unwanted switch-over, the minimum difference between the voltages for VOUT and VLDO should be ±500mV. 21 SC403 Applications Information (continued) In many applications, the EN/PSV pin will be pulled high to the VDD node to allow control of the PWM and LDO ENL pin. If the switch over feature is used, this circuit must be implemented with caution or the circuit may be damaged. In the case where the ENL pin is being controlled by a GPIO signal or is tied directly to the input voltage, the ENL pin can be pulled low while the PWM is still generating an output voltage that is seen across one of the switch-over diodes. This may result in the VDD node being held above its UVLO threshold while the LDO is deactivated. Operating in this way can potentially damage the part. In the case where the ENL pin is used to control the input UVLO, it is acceptable to connect EN/PSV directly to the VDD node. It is not recommended to use the switch-over feature for an output voltage less than 3V since this does not provide sufficient voltage for the gate-source drive to the internal p-channel switch-over MOSFET. Switch-over MOSFET Parasitic Diode The switch-over MOSFET contains a parasitic diode that is inherent to its construction, as shown in Figure 12. Switchover control Switchover MOSFET VOUT LDO Parasitic diode VDD Figure 12— Switch-over MOSFET Parasitic Diodes If VOUT is higher than VDD, then the diode will turn on and the SC403 operating current will flow through this diode. This has the potential of damaging the device. There are some important design rules that must be followed to prevent forward bias of this diode. The following condition, VDD ≥ VOUT needs to be satisfied in order for the parasitic diode to stay off and prevent damaging the device. Many applications connect the EN pin to V5V and control the on/off of the LDO and PWM simultaneously with the ENL pin. This allows one signal to control both the bias and power output of the SC414. When VOUT > 3.0V this configuration can cause problems due to the parasitic diodes in the LDO switchover circuitry. After the V OUT > 3.0V PWM output is up and running the switchover diodes can hold up V5V > UVLO even if the ENL pin is grounded, turning off the LDO. Operating in this way can potentially damage the part. Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (VINMAX) is the highest specified input voltage. The minimum input voltage ( VINMIN) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design. • • • • Nominal output voltage (VOUT ) Static or DC output tolerance Transient response Maximum load current (IOUT ) There are two values of load current to evaluate — continuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design. • • • • VIN = 12V + 10% VOUT = 1.5V + 4% fSW = 300kHz Load = 6A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. 22 SC403 Applications Information (continued) The desired switching frequency is 300kHz which results from using components selected for optimum size and cost. A resistor (RTON) is used to program the on-time (indirectly setting the frequency) using the following equation. RTON ( t ON 10ns) u VIN 25pF u VOUT To select RTON, use the maximum value for VIN, and for tON use the value associated with maximum VIN. t ON V OUT V INMAX u f SW tON = 379 ns at 13.2VIN, 1.5VOUT, 300kHz Substituting for RTON results in the following solution. RTON = 129.9kΩ, use RTON = 130kΩ Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current and ripple voltage and for a given DC resistance are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for PSAVE operation. The switching will typically enter PSAVE mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4A then PSAVE operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then PSAVE will start for loads less than 20% of maximum current. The inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the DH on-time, voltage across the inductor is (VIN - VOUT ). The equation for determining inductance is shown next. L ( VIN VOUT ) u t ON IRIPPLE Example In this example, the inductor ripple current is set equal to 50% of the maximum load current. Therefore ripple current will be 50% x 6A or 3A. To find the minimum inductance needed, use the VIN and tON values that correspond to VINMAX. L (13.2 1.5) u 379ns 3A 1.48PH A slightly larger value of 1.5µH is selected. This will decrease the typical IRIPPLE to 2.7A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum VIN conditions is also checked using the following equations. t ON _ VINMIN IRIPPLE 25pF u RTON u VOUT 10ns VINMIN 461ns ( VIN VOUT ) u t ON L IRIPPLE _ MIN (10.8 1.5) u 461ns 1.5PH u (1 0.2) 2.38 A IRIPPLE _ MAX (10.8 1.5) u 379ns 1.5PH u (1 0.2) 3. 7 A The value of L has been adjusted by +20% for the equations above assuming an inductor tolerance of +20%. Output Capacitor Selection The output capacitors are chosen based upon required ESR and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-topeak ripple. A change in the output ripple voltage will lead to a change in DC voltage at the output. 23 SC403 Applications Information (continued) The design goal is that the output voltage regulation be ±4% under static conditions. The internal 750mV reference tolerance is ±1%. Allowing ±1% tolerance from the FB resistor divider, this allows 2% tolerance due to VOUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 60mV for a 1.5V output. The maximum ripple current of 3.7A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. ESR MAX VRIPPLE IRIPPLEMAX 60mV 3 .7 A The following can be used to calculate the needed capacitance for a given dILOAD/dt. Peak inductor current is shown by the next equation. ILPK = IMAX + 1/2 x IRIPPLEMAX ILPK = 6 + 1/2 x 3.7 = 7.9A ESRMAX = 16.2 mΩ Rate of change of Load Current The output capacitance is usually chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when the inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1µs), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor requiring a capacitance provided by the following equation. COUTMIN 1 § ·2 L¨ IOUT u IRIPPLEMAX ¸ 2 © ¹ 2 VPEAK VOUT 2 Assuming a peak voltage VPEAK of 1.6V (100mV rise upon load release), and a 6A load release, the required capacitance is shown by the next equation. COUTMIN inductor. If the load di/dt is not much faster than the -di/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. 1 § · 1.5PH¨ 6 A u 3.7 A ¸ 2 © ¹ 2 1.6V 1.5V IMAX = maximum load release = 6A Lu COUT ILPK u COUTMIN = 298µF If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 750mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately -VOUT. This causes a down-slope or falling di/dt in the ILPK I MAX u dt VOUT dlLOAD 2VPK VOUT Example dlLOAD dt 2A 1Ps This would cause the output current to move from 6A to 0A in 3.0µs, giving the minimum output capacitance requirement shown in the following equation. C OUT 7 .9 A u 2 2 dlLOAD dt 7. 9 6 u 1Ps 1 .5 2 21.6 V 1.5 V 1.5PH u COUT = 194 µF Note that COUT is much smaller in this example, 194µF compared to 298µF based on a worst-case load release. To meet the maximum design criteria of minimum 298µF and maximum 16mΩ ESR, select one capacitor rated at 330µF and 9mΩ ESR. It is recommended that an additional small capacitor be placed in parallel with COUT in order to filter high frequency switching noise. 24 SC403 Applications Information (continued) Soft Start Capacitor Selection CTOP For a soft-start time (tSS) of approximately 3ms, solve the following equation for CSS. CSS CSS 2.75PA 1 .5 V 5.5nF VOUT t SS To FB pin R1 R2 If CSS is selected as 4.7 nF, then tSS will be 2.6 ms. Then the PGOOD delay, the time from VOUT regulation to PGOOD signal high is shown by the following equation. t PGOOD-DELAY 4.7nF u (0.64 VDD 1.5 V ) 2.75PA At VDD = 5V, the PGOOD delay will be 2.9ms. Stability Considerations Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the 250ns minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resistor, as shown in Figure 13. This capacitor should be left unpopulated until it can be confirmed that double-pulsing exists. Adding the CTOP capacitor will couple more ripple into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor. Figure 13 — Capacitor Coupling to FB Pin ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. One simple way to solve this problem is to add trace resistance in the high current output path. A side effect of adding trace resistance is a decrease in load regulation performance. ESR Requirements A minimum ESR is required for two reasons. One reason is to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications the minimum ESR ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the following equation. ESR MIN 3 2 u S u C OUT u f sw 25 SC403 Applications Information (continued) Using Ceramic Output Capacitors For applications using ceramic output capacitors, the ESR is normally too small to meet the above ESR criteria. In these applications it is necessary to add a small virtual ESR network composed of two capacitors and one resistor, as shown in Figure 14. This network creates a ramp voltage across CL, analogous to the ramp voltage generated across the ESR of a standard capacitor. This ramp is then capacitively coupled into the FB pin via capacitor CC. L Highside Lowside RL CC Virtual ESR Network CL R1 COUT R2 FB pin Figure 14 — Virtual ESR Ramp Circuit Dropout Performance The output voltage adjust range for continuous-conduction operation is limited by the fixed 80ns (typical) minimum off-time of the one-shot. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The duty-factor limitation is shown by the next equation. DUTY t ON(MIN) t ON(MIN) t OFF(MAX ) The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy (VOUT Controller) Three factors affect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static conditions it trips when the feedback pin is 750mV, +1%. The on-time pulse from the SC403 in the design example is calculated to give a pseudo-fixed frequency of 300kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because constant on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50mV with VIN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with VIN = 25V, then the measured DC output will be 40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1% feedback resistors may result in up to 1% error. If tighter DC accuracy is required, 0.1% resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variation The switching frequency will vary depending upon line and load conditions. The line variation is a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As VIN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net effect is that frequency tends to falls slightly with increasing input voltage. 26 SC403 Applications Information (continued) The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A constant on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from VIN as losses increase). The on-time is essentially constant for a given VOUT/VIN combination, to offset the losses the off-time will tend to reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load. 27 SC403 Applications Information (continued) PCB Layout Guidelines The optimum layout for the SC403 is shown in Figure 15. This layout shows an integrated FET buck regulator with a maximum current of 6A. The total PCB area is approximately 20 x 25 mm. Critical Layout Guidelines The following critical layout guidelines must be followed to ensure proper performance of the device. • • • • • • • All other decoupling capacitors must be located as close as possible to the IC. PGND Plane PGND requires its own copper plane with no other signal traces routed on it. Copper planes, multiple vias and wide traces are needed to connect PGND to input capacitors, output capacitors, and the PGND pins on the device. The PGND copper area between the input capacitors, output capacitors, and PGND pins must be as tight and compact as possible to reduce the area of the PCB that is exposed to noise due to current flow on this node. Connect PGND to AGND with a short trace or 0Ω resistor. This connection should be as close to the device as possible. • • • IC decoupling capacitors PGND plane AGND island FB, VOUT, and other analog control signals BST, ILIM, and LX CIN and COUT placement and current loops • IC Decoupling Capacitors A 0.1 μF capacitor must be located as close as possible to the IC and directly connected to pins 3 (VDD) and 4 (AGND). • V5V Decoupling Capacitor RGND — AGND connects to PGND close to the IC AGND plane on inner layer RILIM RLDO2 RGND CLDO RFB1 CFF RFB2 CBST CIN PGND on Top Layer Pin 1 marking IC with vias for LX, AGND, VIN CV5V All components shown Top Side RLDO1 VIN plane on inner or bottom layer COUT VOUT Plane on Top layer L PGND on inner or bottom layer LX plane on inner or bottom layer PGND Figure 15 — PCB Layout 28 SC403 Applications Information (continued) AGND Island AGND should have its own island of copper with no other signal traces routed on this layer that connects the AGND pins and pad of the device to the analog control components. All of the components for the analog control circuitry should be located so that the connections to AGND are done by wide copper traces or vias down to AGND. Connect PGND to AGND with a short trace or 0Ω resistor. This connection should be as close to the device as possible. • • • FB, VOUT, and Other Analog Control Signals The connection from the V OUT power to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. The traces between VOUT and the analog control circuitry (VOUT, and FB pins) must be short and routed away from noise sources, such as BST, LX, VIN, and PGND between the input capacitors, output capacitors, and the device. ILIM and TON nodes must be as short as possible to ensure the best accuracy in current limit and on time. RILIM should be close to the device and connected to LX with a Kelvin trace to pin 28 on the device. All of the LX pins are connected to the LX PAD on the device, which should be a sufficient connection and will prevent the need to connect the resistor further into the LX plane. The feedback components for the switcher and the LDO need to be as close to the FB and FBL pins of the device as possible to reduce the possibility of noise corrupting these analog signals. • • • • • BST, ILIM and LX LX and BST are very noisy nodes and must be routed to minimized the PCB area that is exposed to these signals. The connections for the boost capacitor between the device and LX must be short and directly connected to the LXBST (pin 13). The connections for the current limit resistor between the ILIM pin and LX must be as short as possible and directly connected to pin 28 (LXS). The LX node between the IC and the inductor should be wide enough to handle the inductor current and short enough to eliminate the possibility of LX noise corrupting other signals. Multiple vias should be used to provide a good connection to LX between the device and the inductor. • • • • • Capacitors and Current Loops The current loops between the input capacitors, the device, the inductor, and the output capacitors must be as close as possible to each other to reduce IR drop across the copper. All bypass and output capacitors must be connected as close as possible to the pin on the device. • • • Soft-Start Capacitor The capacitor used for soft-start should be located away from the BST pin and its capacitor. If possible locate the boost capacitor on the opposite side of the board form the IC and softstart capacitor. • • 29 SC403 Outline Drawing — MLPQ-5x5-32 DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX .031 .039 0.80 1.00 A .002 0.00 0.05 A1 .000 (.008) (0.20) A2 b .007 .010 .012 0.18 0.25 0.30 D .193 .197 .201 4.90 5.00 5.10 D1 .076 .078 .080 1.92 1.97 2.02 E .193 .197 .201 4.90 5.00 5.10 E1 .135 .137 .139 3.43 3.48 3.53 e .020 BSC 0.50 BSC L .012 .016 .020 0.30 0.40 0.50 32 32 N aaa .003 0.08 bbb .004 0.10 B D A PIN 1 INDICATOR (LASER MARK) E A2 A aaa SEATING PLANE C C A1 3.48 D1 0.76 1.05 LxN 1.49 E1 3.61 1.66 2 1 0.76 N R0.20 PIN 1 IDENTIFICATION bxN e bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 30 SC403 Land Pattern — MLPQ-5x5-32 3.48 K1 K DIMENSIONS 1.74 (C) H2 1.74 H 3.61 G Z H1 Y X P DIM INCHES MILLIMETERS C (.195) (4.95) G .165 4.20 H .137 3.48 H1 .059 1.49 H2 .065 1.66 K .078 1.97 K1 .041 1.05 P .020 0.50 X .012 0.30 Y .030 0.75 Z .224 5.70 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. 31 SC403 © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. 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