SEMTECH SC653ULTRT

SC653
Light Management Unit with
2 LDOs and SemPulse® Interface
POWER MANAGEMENT
Features
Description
„
The SC653 is a highly integrated light management unit
that provides two low-noise LDOs, a multi-mode high
efficiency charge pump, and four programmable LED
drivers. Performance is optimized for use in single-cell Liion battery applications.
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Input supply voltage range — 2.9V to 5.5V
Four programmable current sinks with 29 steps from
0mA to 25mA
Very high efficiency charge pump driver system with
three modes — 1x, 1.5x and 2x
Two programmable 200mA low-noise LDO regulators
Charge pump frequency — 250kHz
SemPulse single wire interface
Backlight current accuracy — ±1.5% typical
Backlight current matching — ±0.5% typical
Fade-in/fade-out feature for main backlight
Automatic sleep mode (LEDs off ) — IQ = 100μA
Shutdown current — 0.1μA (typical)
Ultra-thin package — 2.3 x 2.3 x 0.6 (mm)
Lead-free and halogen-free
WEEE and RoHS compliant
Applications
„
Cellular phones, smart phones, and PDAs
LCD modules
„ Portable media players
„ Digital cameras and GPS units
„ Display backlighting and LED indicators
The load and supply conditions determine whether the
charge pump operates in 1x, 1.5x, or 2x mode. A programmable fading feature can be enabled to gradually adjust
the backlight current, simplifying control software. The
low-dropout, low-noise linear regulators can be used for
powering a camera module or other peripheral circuits.
The SC653 uses the proprietary SemPulse® single wire
interface. This interface controls all functions of the device,
including backlight currents and LDO voltage outputs.
The single wire interface minimizes microcontroller and
interface pin counts.
The SC653 enters sleep mode when all the LED drivers are
disabled. In this mode, the quiescent current is reduced
while the device continues to monitor the SemPulse interface. The two LDOs can be enabled when the device is in
sleep mode.
„
Typical Application Circuit
SC653
VBAT = 2.9V to 5.5V
CIN
2.2μF
IN
SemPulse
Interface
ENL1
ENL2
GND2
BYP
CBYP
22nF
COUT
2.2μF
GND2
BL1
BL2
BL3
BL4
GND1
LDO1
GND2
LDO2
C1+ C1-
C2+ C2-
GND2
C1
2.2μF
October 21, 2009
OUT
SPIF
GND2
GND1
MAIN BACKLIGHT
VLDO1 = 1.5V to 3.3V
VLDO2 = 1.2V to 1.8V
CLDO1
1μF
C2 GND1
2.2μF
© 2009 Semtech Corporation
CLDO2
1μF
GND1
US Patents: 6,504,422; 6,794,926
1
SC653
BYP
LDO1
GND2
IN
OUT
Ordering Information
LDO2
Pin Configuration
18
17
16
15
14
1
13
C2+
TOP VIEW
BL1
2
12
C1+
BL2
3
11
C1-
BL3
4
10
C2-
6
7
8
9
GND1
ENL1
ENL2
BL4
5
SPIF
T
Device
Package
SC653ULTRT(1)(2)
MLPQ-UT-18 2.3×2.3
SC653EVB
Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free packaging only. Device is WEEE and RoHS compliant,
and halogen-free.
MLPQ-UT-18; 2.3x2.3, 18 LEAD
θJA = 45°C/W
Marking Information
653
yyww
xxxx
yyww = date code
xxxx = Semtech Lot Number
2
SC653
Absolute Maximum Ratings
Recommended Operating Conditions
IN, OUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
Ambient Temperature Range (°C) . . . . . . . . -40 ≤ TA ≤ +85
C1+, C2+ (V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VOUT + 0.3)
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . 2.9 ≤ VIN ≤ 5.5
Pin Voltage — All Other Pins (V) . . . . . . . . . -0.3 to (VIN + 0.3)
Output Voltage (V) . . . . . . . . . . . . . . . . . . . . . 2.5 ≤ VOUT ≤ 5.25
OUT — Short Circuit Duration . . . . . . . . . . . . . . Continuous
Voltage Difference between any two LEDs (V). . ΔVF < 1.0(2)
LDO1, LDO2 — Short Circuit Duration . . . . . . Continuous
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal Information
Thermal Resistance, Junction to Ambient(3) (°C/W) . . . . . . . 45
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . .+150
Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150
Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . +260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) ΔVF(max) = 1.0V when VIN = 2.9V, higher VIN supports higher ΔVF(max)
(3) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless otherwise noted, TA = +25°C for Typ, -40ºC to +85°C for Min and Max, TJ(MAX) = 125ºC, VIN = 3.7V, CIN= C1= C2= 2.2μF,
COUT = 2.2μF (ESR = 0.03Ω), ΔVF ≤ 1.0V(1)
Parameter
Symbol
Conditions
IQ(OFF)
Min
Typ
Max
Units
Shutdown
0.1
2
μA
Sleep (LDOs off ), SPIF = VIN(2)
100
Sleep (LDOs on), SPIF = VIN(2), ILDOn = 0mA
220
Charge pump in 1x mode, IOUT = 20mA, IBLn = 5mA
3.8
Charge pump in 1.5x mode, IOUT = 20mA, IBLn = 5mA
4.6
Charge pump in 2x mode, IOUT = 20mA, IBLn = 5mA
4.6
Supply Specifications
Shutdown Current
μA
Total Quiescent Current
IQ
mA
Charge Pump Electrical Specifications
IOUT(MAX)
VIN > 3.2V, sum of all active LED currents,
VOUT(MAX) = 4.2V
100
IBL
Nominal setting for BL1 thru BL4
0.5
Backlight Current Accuracy
IBL_ACC
IBLn = 12mA(3), TA = 25°C
-8
Backlight Current Matching
IBL-BL
IBLn = 12mA(4)
-3.5
Maximum Total Output Current
Backlight Current Setting
mA
25
mA
±1.5
+8
%
±0.5
+3.5
%
3
SC653
Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Charge Pump Electrical Specifications (continued)
1x Mode to 1.5x Mode
Falling Transition Voltage
V TRANS1x
IOUT = 40mA, IBLn = 10mA, VOUT = 3.2V
3.27
V
1.5x Mode to 1x Mode Hysteresis
VHYST1x
IOUT = 40mA, IBLn = 10mA, VOUT = 3.2V
250
mV
1.5x Mode to 2x Mode
Falling Transition Voltage
V TRANS1.5x
IOUT = 40mA, IBLn = 10mA, VOUT = 4.0V(5)
2.92
V
2x Mode to 1.5x Mode Hysteresis
VHYST1.5x
IOUT = 40mA, IBLn = 10mA, VOUT = 4.0V(5)
300
mV
IBLn
VIN = VBLn = 4.2V
0.1
fPUMP
VIN = 3.2V
250
LDO1 Voltage Setting
VLDO1
Range of nominal settings in 100mV increments
1.5
3.3
V
LDO2 Voltage Setting
VLDO2
Range of nominal settings in 100mV increments
1.2
1.8
V
LDO1, LDO2 Output
Voltage Accuracy
ILDOn = 1mA, TA = 25°C, 2.9V ≤ VIN ≤ 4.2V
-3
+3
%
ΔVLDO
ILDOn = 1mA to 100mA, 2.9V ≤ VIN ≤ 4.2V
-3.5
±3
+3.5
%
ILDO1 = 1mA, VOUT = 2.8V
2.1
7.2
Line Regulation
ΔVLINE
ILDO2 = 1mA, VOUT = 1.8V
1.3
4.8
Current Sink Off-State
Leakage Current
Pump Frequency
1
μA
kHz
LDO Electrical Specifications
Load Regulation
Dropout Voltage(6)
VLDO1 = 3.3V, ILDO1 = 1mA to 100 mA
25
VLDO2 = 1.8V, ILDO2 = 1mA to 100 mA
20
ΔVLOAD
mV
VD
ILDO1 = 150mA
150
PSRRLDO1
1.5V < VLDO1 < 3.0V, f < 1kHz, CBYP = 22nF,
ILDO1 = 50mA with 0.5VP-P supply ripple
55
PSRRLDO2
1.2V < VLDO2, f < 1kHz, CBYP = 22nF, ILDO2 = 50mA,
with 0.5VP-P supply ripple
60
en-LDO1
LDO1, 10Hz < f < 100kHz, CBYP = 22nF, CLDOn = 1μF,
ILDO1 = 50 mA, 1.5V < VLDO1 < 3.0V
100
en-LDO2
LDO2, 10Hz < f < 100kHz, CBYP = 22nF, CLDO = 1μF,
ILDO2 = 50 mA
50
Power Supply Rejection Ratio
Output Voltage Noise
Minimum Output Capacitor
mV
CLDO(MIN)
200
mV
dB
μVRMS
1
μF
4
SC653
Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min
1.6
Typ
Max
Units
Digital I/O Electrical Specifications (SPIF, ENL1, ENL2)
Input High Threshold(7)
VIH
VIN = 5.5V
Input Low Threshold(7)
VIL
VIN = 3.0V
Input High Current
IIH
VIN = 5.5V
Input Low Current
IIL
VIN = 5.5V
V
0.4
V
-1
+1
μA
-1
+1
μA
SemPulse Electrical Specifications (SPIF)
SemPulse Start-up Time(8)
tSU
1
Bit Pulse Duration(7)
tHI
0.75
250
μs
Duration Between Bits(7)
tLO
0.75
250
μs
5000
μs
ms
Hold Time - Address(7)
tHOLDA
SPIF is held high
500
Hold Time - Data(7)
tHOLDD
SPIF is held high
500
μs
Bus Reset Time(7)
tBR
SPIF is held high
10
ms
Shutdown Time(9)
tSD
SPIF is pulled low
10
ms
IOUT(SC)
OUT pin shorted to GND
ILIM
VLDOn enabled
TOTP
Rising threshold
165
°C
THYS
Hysteresis
30
°C
VOVP
OUT pin open circuit, VOUT = VOVP
rising threshold
VUVLO-OFF
Increasing VIN
2.7
V
VUVLO-HYS
Hysteresis
800
mV
Fault Protection
Output Short Circuit Current Limit
LDO Current Limit
250
mA
200
mA
Over-Temperature
Charge Pump
Over-Voltage Protection
5.3
5.7
6.0
V
Under Voltage Lockout
Notes:
(1) ΔVF is the voltage difference between any two LEDs.
(2) SPIF is high for more than 10ms
(3) Subscript n = 1 and 2 for the LDOs, and n = 1, 2, 3, and 4 for the backlights.
(4) Current matching equals ± [IBL(MAX) - IBL(MIN] / [IBL(MAX) + IBL(MIN)].
(5) Test voltage is VOUT = 4.0V — a relatively extreme LED voltage — to force a transition during test. Typically VOUT = 3.2V for white LEDs.
(6) Dropout is defined as (VIN - VLDO1) when VLDO1 drops 100mV from nominal. Dropout does not apply to LDO2 since it has a maximum output voltage
of 1.8V.
(7) The source driver used to provide the SemPulse output must meet these limits.
(8) The SemPulse start-up time is the minimum time that the SPIF pin must be held high to enable the part before starting communication.
(9) The SemPulse shutdown time is the minimum time that the SPIF pin must be pulled low to shut the part down.
5
SC653
Typical Characteristics
Battery Current (4 LEDs) — 25mA Each
180
Backlight Efficiency (4 LEDs) — 25mA Each
VOUT = 3.56V, IOUT = 100mA, 25°C
100
90
Efficiency (%)
Battery Current (mA)
160
140
120
80
70
60
100
80
4.2
3.9
3.6
VIN(V)
3.3
3
50
4.2
2.7
VOUT = 3.41V, IOUT = 48mA, 25°C
100
70
60
50
VIN(V)
3.3
3
2.7
VOUT = 3.41V, IOUT = 48mA, 25°C
80
70
60
40
4.2
3.9
3.6
VIN(V)
3.3
3
50
4.2
2.7
Battery Current ( 4 LEDs) — 5.0mA Each
VOUT = 3.27V, IOUT = 20mA, 25°C
100
3.6
VIN(V)
3.3
3
2.7
VOUT = 3.27V, IOUT = 20mA, 25°C
Efficiency (%)
90
30
20
10
0
4.2
3.9
Backlight Efficiency ( 4 LEDs) — 5.0mA Each
40
Battery Current (mA)
3.6
90
Efficiency (%)
Battery Current (mA)
80
50
3.9
Backlight Efficiency (4 LEDs) — 12mA Each
Battery Current (4 LEDs) — 12mA Each
90
VOUT = 3.56V, IOUT = 100mA, 25°C
80
70
60
3.9
3.6
VIN(V)
3.3
3
2.7
50
4.2
3.9
3.6
VIN(V)
3.3
3
2.7
6
SC653
Typical Characteristics (continued)
PSRR vs. Frequency — 1.8V
-10
-10
-20
-20
-30
-40
-30
-40
-50
-50
-60
-60
-70
10
100
VIN = 3.7V, IOUT = 50mA, TA = 25°C
0
PSRR (dB)
PSRR (dB)
0
PSRR vs. Frequency — 2.8V
VIN = 3.7V, IOUT = 50mA, TA = 25°C
Frequency (Hz)
1000
-70
10000
10
100
Line Regulation (LDO2)
1.5
3
Output Voltage Variation (mV)
Output Voltage Variation (mV)
ILDO1 = 1mA, VLDO1 = 2.8V, 25°C
2
0.5
1.2V
0
1.8V
-0.5
-1
-1.5
4.2
1
0
2.8V
-1
-2
-3
3.9
3.6
3.3
3
VIN(V)
4.2
2.7
LDO Noise vs. Load Current — 1.8V
3.9
3.6
VIN(V)
3.3
3
2.7
LDO Noise vs. Load Current — 2.8V
VLDO=1.8V, VIN=3.7V, 25°C, 10Hz < f < 100kHz
100
80
VLDO=2.8V, VIN=3.7V, 25°C, 10Hz < f < 100kHz
80
Noise (μVRMS)
Noise (μVRMS)
10000
1000
Line Regulation (LDO1)
ILDO1 = 1mA, VLDO1 = 1.2V and 1.8V, 25°C
1
100
Frequency (Hz)
60
40
20
60
40
20
0
0
0
20
40
60
IOUT (mA)
80
100
0
30
60
90
120
150
IOUT (mA)
7
SC653
Typical Characteristics (continued)
Load Regulation (LDO2)
0
Load Regulation (LDO1)
VIN = 3.7V, 25°C
0
-5
Output Voltage Variation (mV)
Output Voltage Variation (mV)
-5
1.2V
-10
1.5V
-15
1.8V
-20
-25
-30
VIN=3.7V, 25°C
1.5V
-10
1.8V
-15
2.5V
-20
2.8V
-25
3.3V
-30
-35
0
40
80
ILDO (mA)
120
160
200
0
80
120
160
200
ILDO (mA)
LDO Load Transient Response (1.2V)
LDO Load Transient Response (3.3V)
VIN=3.7V, VLDO=3.3V, ILDO=1 to 100mA, 25°C
VIN=3.7V, VLDO=1.2V, ILDO=1 to 100mA, 25°C
VLDO (50mV/div)
40
VLDO (50mV/div)
ILDO (100mA/div)
ILDO (100mA/div)
Time (20μs/div)
Time (20μs/div)
LDO Load Transient Response (1.8V)
Output Short Circuit Current Limit
VIN=3.7V, VLDO=1.8V, ILDO=1 to 100mA, 25°C
VOUT=0V, VIN=4.2V, 25°C
VOUT (1V/div)
VLDO (50mV/div)
ILDO (100mA/div)
IOUT (200mA/div)
Time (20μs/div)
Time (1ms/div)
8
SC653
Typical Characteristics (continued)
Ripple — 1.5X Mode
Ripple — 1X Mode
VIN=2.9V, 4 Backlights — 25 mA each, 25°C
VIN=3.7V, 4 Backlights — 25 mA each, 25°C
VIN (100mV/div)
VIN (100mV/div)
VOUT (100mV/div)
VOUT (100mV/div)
IBL (20mA/div)
IBL (20mA/div)
Time (20μs/div)
Time (20μs/div)
Ripple — 2X Mode
Output Open Circuit Protection
VIN=2.9V, 4 Backlights — 25 mA each, 25°C
VIN=3.7V, 25°C
VBL (500mV/div)
VIN (100mV/div)
5.42V
VOUT (1V/div)
VOUT (100mV/div)
IBL (20mA/div)
IBL (20mA/div)
Time (20μs/div)
Time (200μs/div)
9
SC653
Pin Descriptions
Pin #
Pin Name
Pin Function
1
BYP
Bypass pin for voltage reference — ground CBYP to GND1 on ground island.
2
BL1
Current sink output for main backlight LED 1 — leave this pin open if unused
3
BL2
Current sink output for main backlight LED 2 — leave this pin open if unused
4
BL3
Current sink output for main backlight LED 3 — leave this pin open if unused
5
BL4
Current sink output for main backlight LED 4 — leave this pin open if unused
6
SPIF
SemPulse single wire interface pin — used to enable/disable the device and to configure all registers (refer to Register Map and SemPulse Interface sections)
7
GND1
Ground pin — Ground CBYP, CLDO1, CLDO2 to GND1 on ground island.
8
ENL1 (1)
LDO1 enable input — active high
9
ENL2 (2)
LDO2 enable input — active high
10
C2-
Negative connection to bucket capacitor 2
11
C1-
Negative connection to bucket capacitor 1
12
C1+
Positive connection to bucket capacitor 1
13
C2+
Positive connection to bucket capacitor 2
14
OUT
Charge pump output — all LED anode pins should be connected to this pin
15
IN
16
GND2
Ground Pin — connect to ground plane
17
LDO1
Output of LDO1 — ground CLDO1 to GND1 on ground island.
18
LDO2
Output of LDO2 — ground CLDO2 to GND1 on ground island.
T
THERMAL PAD
Battery voltage input
Thermal pad for heatsinking purposes — connect to ground plane using multiple vias. This pad is
internally connected to ground and to pins 7 and 16.
NOTES:
(1) ENL1 must be high for the SPIF interface to control LDO1. When low, ENL1 disables LDO1.
(2) ENL2 must be high for the SPIF interface to control LDO2. When low, ENL2 disables LDO2.
10
SC653
Block Diagram
VIN
IN
15
SPIF
6
SemPulseTM
Digital
Interface
and Logic
Control
C1+
C1-
C2+
C2-
12
11
13
10
Fractional Charge Pump
(1x, 1.5x, 2x)
1
GND1
7
Bandgap
Reference
Voltage
Setting
DAC
2
BL1
3
BL2
4
BL3
5
BL4
17
LDO1
18
LDO2
VIN
LDO1
ENL1
OUT
Oscillator
Current
Setting
DAC
BYP
14
8
VIN
ENL2
9
LDO2
GND2
16
11
SC653
Applications Information
General Description
This design is optimized for handheld applications supplied from a single Li-Ion cell and includes the following
key features:
•
•
•
A high efficiency fractional charge pump that
supplies power to all LEDs
Four matched current sinks that control LED
backlighting current, with 0mA to 25mA per
LED
Two adjustable LDOs with outputs ranging from
1.5V to 3.3V for LDO1 and 1.2V to 1.8V for LDO2,
adjustable in 100mV increments
High Current Fractional Charge Pump
The backlight outputs are supported by a high efficiency,
high current fractional charge pump output at the OUT
pin. The charge pump multiplies the input voltage by 1,
1.5, or 2 times. The charge pump switches at a fixed frequency of 250kHz in 1.5x and 2x modes and is disabled in
1x mode to save power and improve efficiency.
The mode selection circuit automatically selects the mode
as 1x, 1.5x, or 2x based on circuit conditions such as LED
voltage, input voltage, and load current. The 1x mode is
the most efficient of the three modes, followed by 1.5x
and 2x modes. Circuit conditions such as low input voltage,
high output current, or high LED voltage place a higher
demand on the charge pump output. A higher numerical
mode (1.5x or 2x) may be needed momentarily to maintain regulation at the OUT pin during intervals of high
demand. The charge pump responds to momentary high
demands, setting the charge pump to the optimum mode
to deliver the output voltage and load current while optimizing efficiency. Hysteresis is provided to prevent mode
toggling.
The charge pump requires two bucket capacitors for
proper operation. One capacitor must be connected
between the C1+ and C1- pins and the other must be connected between the C2+ and C2- pins as shown in the
typical application circuit diagram. These capacitors
should be equal in value, with a nominal capacitance of
1.0μF to support the charge pump current requirements.
Note that small package capacitors can decrease in value
by up to 50% under DC loading, so it is strongly recommended that 2.2uF capacitors be selected when using
0402 size ceramic capacitors. The device also requires a
2.2μF capacitor on the IN pin and a 2.2μF capacitor on
the OUT pin to minimize noise and support the output
drive requirements. Capacitors with X7R or X5R ceramic
dielectric are strongly recommended for their low ESR
and superior temperature and voltage characteristics.
Y5V capacitors should not be used as their temperature
coefficients make them unsuitable for this application.
LED Backlight Current Sinks
The backlight current is set via the SemPulse interface.
The current is regulated to one of 29 values between
0mA and 25mA. The step size varies depending upon the
current setting. The step sizes are 0.5mA for current settings between 0mA and 5mA. The step size increases to
1mA for settings between 5mA and 21mA. Steps are 2mA
between 21mA and 25mA. The variation in step size
allows finer adjustment for dimming functions in the low
current setting range and coarse adjustment at higher
current settings where small current changes are not
visibly noticeable in LED brightness. A zero setting is also
included to allow the current sink to be disabled by
writing to either the enable bit or the current setting register for maximum flexibility.
All backlight current sinks have matched currents, even
when there is variation in the forward voltages (ΔVF ) of
the LEDs. A ΔVF of 1.2V is supported when the input
voltage is at 3.0V. Higher ΔVF LED mis-match is supported
when VIN is higher than 3.0V. All current sink outputs are
compared and the lowest output is used for setting the
voltage regulation at the OUT pin. This is done to ensure
that sufficient bias exists for all LEDs.
The backlight LEDs default to the off state upon powerup. For backlight applications using less than four LEDs,
any unused output must be left open and the unused
LED driver must remain disabled. When writing to the
Backlight Enable register, a zero (0) must be written to
the corresponding bit of any unused output.
12
SC653
Applications Information (continued)
Backlight Quiescent Current
The quiescent current required to operate all four backlights is reduced by 1.5mA when backlight current is set
to 4.0mA or less. This feature results in higher efficiency
under light-load conditions. Further reduction
in quiescent current will result from using fewer than four
LEDs.
Fade-In and Fade-Out
The SC653 contains bits that control the fade state of the
main bank. When enabled, the fade function causes the
backlight settings to step from their current state to the
next programmed state as soon as the new state is stored
in its register. For example, if the backlight is set at 25mA
and the next setting is the off state, the backlight will step
from 25mA down to 0mA using all 29 settings at the fade
rate specified by the bits in register 04h. The same is true
when turning on or increasing the backlight current —
the backlight current will step from the present level to
the new level at the step rate defined in register 04h. This
process applies for both the main and the sub displays.
The fade rate may be changed dynamically when a fade
operation is active by writing new values to the fade register. When a new backlight level is written during an
ongoing fade operation, the fade will be redirected to the
new value from the present state. An ongoing fade operation may be cancelled by disabling fade which will result
in the backlight current changing immediately to the final
value. If fade is disabled, the current level will change
immediately without the fade delay. The state diagram in
Figure 1 describes all possible conditions for a fade operation. More details can be found in the Register Map
Section.
Immediate
change to new
bright level
No change
FADE=0
Write new
bright level
Write FADE=0
FADE=0
Immediate
change to
new bright
level
Write
FADE=0
Write
FADE=1
FADE=1
No
change
FADE=1
Write
FADE=1
Write new
bright
level
Fade=0
Fade
ends
Fade
begins
Fade
processing(1)
No
change
Write new
bright level
Write
Fade=1
Continue
fade using
new rate
Fade is redirected
toward the new
value from current
state
Write
new fade
rate
Note:
(1) When the data in backlight
enable register 01h is not 00h
Figure 1 — Fade State Diagram
Programmable LDO Outputs
Two low dropout (LDO) regulators are provided for
camera module I/O and core power. Each LDO output
voltage setting has ±3.5% accuracy over the operating
temperature range. Output current greater than the
specification is possible at somewhat reduced accuracy.
Input pins ENL1 and ENL2 may be used to directly enable
and disable the LDOs without communication via the
SPIF interface. When power is first applied to the SC653,
the register defaults reset the LDOs to the off state, so
SPIF must be used one time to set the voltages before
ENL1 and ENL2 can be used to enable the LDOs.
13
SC653
Applications Information (continued)
To control LDOs exclusively by software, ENL1 and ENL2
may be permanently terminated to the battery voltage.
ENL1 must be high for the SPIF interface to control LDO1.
When low, ENL1 disables LDO1. ENL2 is used exactly the
same way to enable and disable LDO2.
A 1μF, low ESR capacitor should be used as a bypass
capacitor on each LDO output to reduce noise and ensure
stability. In addition, it is recommended that a nominal
minimum 22nF capacitor be connected between the BYP
pin and the GND1 pin to minimize noise and achieve
optimum power supply rejection. A larger capacitor can
be used for this function, but at the expense of increasing
turn-on time. Capacitors with X7R or X5R ceramic dielectric are strongly recommended for their low ESR and
superior temperature and voltage characteristics. Y5V
capacitors should not be used as their temperature coefficients make them unsuitable for this application.
Shutdown Mode
The device is disabled when the SPIF pin is held low for
the shutdown time specified in the electrical characteristics section. All registers are reset to default condition at
shutdown. Typical current consumption in this mode is
0.1μA.
Output Open Circuit Protection
Over-Voltage Protection (OVP) is provided at the OUT pin
to prevent the charge pump from producing an excessively high output voltage. In the event of an open circuit
at OUT, the charge pump runs in open loop and the
voltage rises up to the OVP limit. OVP operation is hysteretic, meaning the charge pump will momentarily turn off
until VOUT is sufficiently reduced. The maximum OVP
threshold is 6.0V, allowing the use of a ceramic output
capacitor rated at 6.3V.
Over-Temperature Protection
The Over-Temperature (OT) protection circuit prevents the
device from overheating and experiencing a catastrophic
failure. When the junction temperature exceeds 165°C, the
device goes into thermal shutdown with all outputs disabled until the junction temperature is reduced. All register information is retained during thermal shutdown.
Hysteresis of 30°C is provided to ensure that the device
cools sufficiently before re-enabling.
Charge Pump Output Current Limit
The device limits the charge pump current at the OUT pin.
When OUT is shorted to ground, the output current will
typically equal 250mA. The output current is also limited
to 250mA when over-loaded resistively.
Sleep Mode
When all LEDs are disabled, sleep mode is activated. This
is a reduced current mode that helps minimize overall
current consumption by disabling the clock and the
charge pump while continuing to monitor the serial
interface for commands. The two LDOs can be enabled
when the device is in sleep mode.
LDO Current Limit
The device limits the output currents of LDO1 and LDO2
to help prevent the device from overheating and to
protect the loads. The minimum limit is 200mA, so load
current greater than the rated current and up to 200mA
can be used with degraded accuracy and larger dropout
without tripping the current limit.
Protection Features
The SC653 provides several protection features to safeguard the device from catastrophic failures. These features include:
•
•
•
•
•
Output Open Circuit Protection
Over-Temperature Protection
Charge Pump Output Current Limit
LDO Current Limit
LED Float Detection
LED Float Detection
Float detect is a fault detection feature of the LED current
sink outputs. If an output is programmed to be enabled
and an open circuit fault occurs at any current sink output,
that output will be disabled to prevent a sustained output
OVP condition from occurring due to the resulting open
loop. Float detect ensures device protection but does not
ensure optimum performance. Unused LED outputs must
be disabled to prevent an open circuit fault from
occurring.
14
SC653
Applications Information (continued)
PCB Layout Considerations
•
The layout diagram in Figure 2 illustrates a proper
two-layer PCB layout for the SC653 and supporting components. Following fundamental layout rules is critical for
achieving the performance specified in the Electrical
Characteristics table. The following guidelines
are recommended when developing a PCB layout:
•
•
•
•
•
Place all bucket, bypass, and decoupling capacitors — C1, C2, CIN, COUT, CLDO1, CLDO2, and
CBYP as close to the device as possible.
All charge pump current passes through IN,
OUT, and the bucket capacitor connection pins.
Ensure that all connections to these pins make
use of wide traces so that the resistive drop on
each connection is minimized.
The thermal pad should be connected to the
ground plane using multiple vias to ensure
proper thermal connection for optimal heat
transfer.
CLDO2
CBYP
CLDO1
18
1
17
CIN
16
COUT
IN
OUT
15
14
Figure 3 — Layer 1
TBD Figure 3 — Layer 1
12
SC653
3
Vias to
ground
plane
13
GND2
2
•
The following capacitors — CLDO1, CLDO2, and
CBYP should be grounded together through an
isolated copper island. Using no vias, connect
the island only, to pin 7 as shown in Figure 2.
Figure 3 shows only the vias that should be connected to the ground plane with multiple vias.
Make all ground connections to a solid ground
plane as shown in Figure 4.
All LDO output traces should be made as wide
as possible to minimize resistive losses.
11
C1
C2
10
4
5
6
7
8
9
Keep gap
open
Ground Layer
Island for
pin 7 GND1
(no vias)
Figure 4 — Layer 2
Figure 2 — Recommended PCB Layout
TBD Figure 2 — Recommended PCB Layout
TBD Figure 4 — Layer 2
15
SC653
SemPulse® Interface
Introduction
SemPulse is a write-only single wire interface. It provides
access to up to 32 registers that control device functionality. Two sets of pulse trains are transmitted via the SPIF
pin. The first pulse set is used to set the desired address.
After the bus is held high for the address hold period, the
next pulse set is used to write the data value. After the
data pulses are transmitted, the bus is held high again for
the data hold period to signify the data write is complete.
At this point the device latches the data into the address
that was selected by the first set of pulses. See the
SemPulse Timing Diagrams for descriptions of all timing
parameters.
Chip Enable/Disable
The device is enabled when the SemPulse interface pin
(SPIF) is pulled high for greater than tSU. If the SPIF pin is
pulled low again for more than tSD, the device will be
disabled.
Address Writes
The first set of pulses can range between 0 and 31 (or 1 to
32 rising edges) to set the desired address. After the
pulses are transmitted, the SPIF pin must be held high for
tHOLDA to notify the slave device that the address write is
finished. If the pulse count is between 0 and 31 and the
line is held high for tHOLDA, the address is latched as the
destination for the data word. If the SPIF pin is not held
high for tHOLDA, the slave device will continue to count
pulses. If the total exceeds 31 pulses, the write will be
ignored and the bus will reset after the next valid hold
time is detected. Note that if tHOLDA exceeds its maximum
specification, the bus will reset. This means that the communication is ignored and the bus resumes monitoring
the pin, expecting the next pulse set to be an address.
Data Writes
After the bus has been held high for the minimum
address hold period, the next set of pulses are used to
write the data value. The total number of pulses can
range from 0 to 63 (or 1 to 64 rising edges) since there are
a total of 6 register bits per register. Just like with the
address write, the data write is only accepted if the bus is
held high for tHOLDD when the pulse train is completed. If
the proper hold time is not received, the interface will
keep counting pulses until the hold time is detected. If
the total exceeds 63 pulses, the write will be ignored and
the bus will reset after the next valid hold time is detected.
After the bus has been held high for tHOLDD, the bus will
expect the next pulse set to be an address write. Note
that this is the same effect as the bus reset that occurs
when tHOLDA exceeds its maximum specification. For this
reason, there is no maximum limit on tHOLDD — the bus
simply waits for the next valid address to be transmitted.
Multiple Writes
It is important to note that this single-wire interface
requires the address to be paired with its corresponding
data. If it is desired to write multiple times to the same
address, the address must always be re-transmitted prior
to the corresponding data. If it is only transmitted one
time and followed by multiple data transmissions, every
other block of data will be treated like a new address. The
result will be invalid data writes to incorrect addresses.
Note that multiple writes only need to be separated by
the minimum tHOLDD for the slave to interpret them correctly. As long as tHOLDA between the address pulse set and
the data pulse set is less than its maximum specification
but greater than its minimum, multiple pairs of address
and data pulse counts can be made with no detrimental
effects.
Standby Mode
Once data transfer is completed, the SPIF line must be
returned to the high state for at least 10ms to return to the
standby mode. In this mode, the SPIF line remains idle
while monitoring for the next command. This mode
allows the device to minimize current consumption
between commands. Once the device has returned to
standby mode, the bus is automatically reset to expect the
address pulses as the next data block. This safeguard is
intended to reset the bus to a known state (waiting for the
beginning of a write sequence) if the delay exceeds the
reset threshold.
16
SC653
SemPulse® Interface (continued)
The SemPulse single wire interface is used to enable or disable the device and configure all registers (see Figure 2). The
timing parameters refer to the digital I/O electrical specifications.
Address is set
Up to 32 rising edges
(0 to 31 pulses)
Up to 64 rising edges
(0 to 63 pulses)
Data is written
SPIF
t = tSU
t = tHOLDA
t = tHOLDD
tHI
tLO
Figure 2 — Uniform Timing Diagram for SemPulse Communication
Timing Example 1
In this example (see Figure 3), the slave chip receives a sequence of pulses to set the address and data, and the pulses
experience interrupts that cause the pulse width to be non-uniform. Note that as long as the maximum high and low
times are satisfied and the hold times are within specification, the data transfer is completed regardless of the number
of interrupts that delay the transmission.
Address is set to
register 02h
Data written is
000011
SPIF
t = tSU
tHI
tLO
t = tHOLDA
t < tHImax
t = tHOLDD
t < tLOmax
Figure 3 — SemPulse Data Write with Non-Uniform Pulse Widths
Timing Example 2
In this example (see Figure 4), the slave chip receives two sets of pulses to set the address and data, but an interrupt
occurs during a pulse that causes it to exceed the minimum address hold time. The write is meant to be the value 03h
in register 05h, but instead it is interpreted as the value 02h written to register 02h. The extended pulse that is delayed
by the interrupt triggers a false address detection, causing the next pulse set to be interpreted as the data set. To avoid
any problems with timing, make sure that all pulse widths comply with their timing requirements as outlined in this
datasheet.
Address is set to
register 02h
SPIF
Data written is
000010
Address is set to register
03h (address and data are
now out of order)
Interrupt
duration
t > tHImax
t = tHOLDA
t = tHOLDD
Figure 4 — Faulty SemPulse Data Write Due to Extended Interrupt Duration
17
SC653
Register Map(1)
Address
D5
D4
D3
D2
D1
D0
Reset
Value
Description
00h
0(2)
BL_4
BL_3
BL_2
BL_1
BL_0
00h
Backlight
Current
01h
0(2)
0(2)
BLEN_4
BLEN_3
BLEN_2
BLEN_1
00h
Backlight
Enable
02h
0(2)
0(2)
LDO1_3
LDO1_2
LDO1_1
LDO1_0
00h
LDO1
03h
0(2)
0(2)
0(2)
LDO2_2
LDO2_1
LDO2_0
00h
LDO2
04h
0(2)
0(2)
0(2)
FADE_1
FADE_0
FADE_EN
00h
Fade
Notes:
(1) All registers are write-only.
(2) 0 = always write a 0 to these bits
Definition of Registers and Bits
BL_4
BL_3
BL_2
BL_1
BL_0
Backlight
Current (mA)
BL Current Control Register (00h)
0
1
0
1
1
4
This register is used to set the currents for the backlight
current sinks. These current sinks need to be enabled in
the Backlight Enable Control register to be active.
0
1
1
0
0
4.5
0
1
1
0
1
5
0
1
1
1
0
6
0
1
1
1
1
7
1
0
0
0
0
8
1
0
0
0
1
9
1
0
0
1
0
10
1
0
0
1
1
11
1
0
1
0
0
12
1
0
1
0
1
13
1
0
1
1
0
14
1
0
1
1
1
15
1
1
0
0
0
16
1
1
0
0
1
17
1
1
0
1
0
18
1
1
0
1
1
19
1
1
1
0
0
20
1
1
1
0
1
21
1
1
1
1
0
23
1
1
1
1
1
25
BL[D4:D0]
These bits are used to set the current for the backlight
current sinks. All enabled backlight current sinks will sink
the same current, as shown in Table 1.
Table 1 — Backlight Current Settings
BL_4
BL_3
BL_2
BL_1
BL_0
Backlight
Current (mA)
0
0
0
0
0
0
0
0
0
0
1
See note 1
0
0
0
1
0
See note 1
0
0
0
1
1
See note 1
0
0
1
0
0
0.5
0
0
1
0
1
1
0
0
1
1
0
1.5
0
0
1
1
1
2
0
1
0
0
0
2.5
0
1
0
0
1
3
0
1
0
1
0
3.5
(1) Reserved for future use
18
SC653
Register and Bit Definitions (continued)
Backlight Enable Control Register (01h)
LDO2 Control Register (03h)
This register is used to enable the backlight current
sinks.
This register is used to enable the LDO2 and to set the
output voltage VLDO2.
BLEN[D4:D1]
These bits are used to enable current sinks (active high,
default low).
LDO2[D2:D0]
These bits are used to set the output voltage, VLDO2, as
shown in Table 3.
Table 3 — LDO2 Control Bits
BLEN_4 — Enable bit for backlight BL4
BLEN_3 — Enable bit for backlight BL3
BLEN_2 — Enable bit for backlight BL2
BLEN_1 — Enable bit for backlight BL1
When enabled, the current sinks will carry the current set
by the backlight current control bits BL[4:0], as shown in
Table 1.
LDO1 Control Register (02h)
This register is used to enable LDO1 and set the output
voltage VLDO1.
LDO1[D3:D0]
These bits set the output voltage, V LDO1, as shown in
Table 2.
Table 2 — LDO1 Control Bits
LDO1_3
LDO1_2
LDO1_1
LDO1_0
VLDO1
0
0
0
0
OFF
0
0
0
1
3.3V
0
0
1
0
3.2V
0
0
1
1
3.1V
0
1
0
0
0
1
0
0
1
0
LDO2_2
LDO2_1
LDO2_0
VLDO2
0
0
0
OFF
0
0
1
1.8V
0
1
0
1.7V
0
1
1
1.6V
1
0
0
1.5V
1
0
1
1.4V
1
1
0
1.3V
1
1
1
1.2V
Fade Control Register (04h)
This register is used to enable the backlight fade and to
set the rise and fall rate at which fading proceeds.
FADE[D2:D1]
These bits are used to set the rise/fall rate between two
backlight currents as shown in Table 4.
Table 4 — Fade Control Bits
FADE_1
FADE_0
Fade Feature Rise/Fall Rate
(ms/step)
3.0V
0
0
32
1
2.9V
0
1
24
1
0
2.8V
1
0
16
1
1
1
2.7V
1
1
8
1
0
0
0
2.6V
1
0
0
1
2.5V
1
0
1
0
2.4V
1
0
1
1
2.2V
1
1
0
0
1.8V
1
1
0
1
1.7V
1
1
1
0
1.6V
1
1
1
1
1.5V
The number of steps in changing the backlight current
will be equal to the change in binary count of bits
BL[4:0].
19
SC653
Register and Bit Definitions (continued)
FADE_EN [D0]
This bit is used to enable or disable the fade feature. When
the fade function is enabled and a new backlight current
is set, the backlight current will change from its current
value to a new value set by bits BL[4:0] at a rate of 8ms to
32ms per step. A new backlight level cannot be written
during an ongoing fade operation, but an ongoing fade
operation may be cancelled by resetting the fade bit.
Clearing the fade bit during an ongoing fade operation
changes the backlight current immediately to the value of
BL[4:0]. The number of counts to complete a fade operation equals the difference between the old and new
backlight values to increment or decrement the BL[4:0]
bits. If the fade bit is cleared, the current level will change
immediately without the fade delay. The rate of fade may
be changed dynamically, even while a fade operation is
active, by writing new values to the FADE_1 and FADE_0
bits. The total fade time is determined by the number of
steps between old and new backlight values, multiplied
by the rate of fade in ms/step. The longest elapsed time
for a full scale fade-out of the backlight is nominally 938ms
when the default interval of 32ms is used.
20
SC653
Outline Drawing — MLPQ-UT-18 2.3x2.3
A
D
B
DIMENSIONS
DIM
A
A1
A2
b
D
D1
E
E1
e
E
PIN 1
INDICATOR
(LASER MARK)
A2
A
SEATING
PLANE
aaa C
C
A1
L
N
aaa
bbb
MILLIMETERS
MIN
0.50
0.00
0.15
2.20
1.15
2.20
1.15
NOM
(0.152)
0.20
2.30
1.20
2.30
1.20
0.40 BSC
0.25
0.30
18
0.08
0.10
MAX
0.60
0.05
0.25
2.40
1.25
2.40
1.25
0.35
D1
LxN
E/2
E1
2
1
e/2
N
bxN
bbb
e
C A B
D/2
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
21
SC653
Land Pattern — MLPQ-UT-18 2.3x2.3
K
(C)
DIMENSIONS
R
G
H
Z
Y
X
P
DIM
MILLIMETERS
C
(2.33)
G
1.76
H
1.20
K
1.20
P
0.40
R
0.10
X
0.20
Y
0.57
Z
2.90
NOTES:
1.
2.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
4.
SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
22