TI SN74HC273DW

SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 12 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Contain Eight Flip-Flops With Single-Rail
Outputs
D Direct Clear Input
D Individual Data Input to Each Flip-Flop
D Applications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
description
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
2D
2Q
3Q
3D
4D
8Q
1
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
SN54HC273 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
CLR
VCC
SN54HC273 . . . J OR W PACKAGE
SN74HC273 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.
ORDERING INFORMATION
PACKAGE†
TA
PDIP − N
SN74HC273N
Tube of 25
SN74HC273DW
Reel of 2000
SN74HC273DWR
SOP − NS
Reel of 2000
SN74HC273NSR
HC273
SSOP − DB
Reel of 2000
SN74HC273DBR
HC273
Tube of 70
SN74HC273PW
Reel of 2000
SN74HC273PWR
Reel of 250
SN74HC273PWT
CDIP − J
Tube of 20
SNJ54HC273J
SNJ54HC273J
CFP − W
Tube of 85
SNJ54HC273W
SNJ54HC273W
LCCC − FK
Tube of 55
SNJ54HC273FK
TSSOP − PW
−55°C
125°C
−55
C to 125
C
TOP-SIDE
MARKING
Tube of 20
SOIC − DW
−40°C to 85°C
ORDERABLE
PART NUMBER
SN74HC273N
HC273
HC273
SNJ54HC273FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
POST OFFICE BOX 655303
&)$#!" #&(! ! 01
(( &%!%" % !%"!%)
$(%"" !+%-"% !%)* (( !+% &)$#!"
&)$#!
&#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"*
• DALLAS, TEXAS 75265
1
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
description/ordering information (continued)
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related
directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has
no effect at the output.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
CLK
D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
logic diagram (positive logic)
1D
CLK
2D
3
11
3D
4
1D
7
1D
C1
5D
8
1D
C1
R
CLR
4D
13
1D
C1
R
6D
14
1D
C1
R
7D
17
1D
C1
R
8D
1D
C1
R
18
1D
C1
R
C1
R
R
1
2
1Q
5
6
2Q
3Q
9
12
4Q
15
5Q
6Q
16
7Q
19
8Q
logic diagram, each flip-flop (positive logic)
D
C
C
TG
TG
Q
C
C
C
C
TG
CLK(I)
TG
C
C
C
C
R
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC273
VCC
VIH
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
MIN
NOM
MAX
2
5
6
Supply voltage
VCC = 2 V
VCC = 4.5 V
Low-level input voltage
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
VCC = 4.5 V
VCC = 6 V
Input voltage
0
Output voltage
0
Input transition rise/fall time
SN74HC273
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
0.5
1.35
1.35
1.8
1.8
0
0
V
V
0.5
VCC
VCC
UNIT
VCC
VCC
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
IOH = −20 µA
VOH
VI = VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
VI = VCC or 0
VI = VCC or 0,
IO = 0
Ci
VCC
MIN
TA = 25°C
TYP
MAX
SN54HC273
MIN
MAX
SN74HC273
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
µA
3
10
10
10
pF
6V
2 V to 6 V
V
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
CLR low
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK↑
CLR inactive
th
4
Hold time, data after CLK
CLK↑
POST OFFICE BOX 655303
TA = 25°C
MIN
MAX
SN54HC273
MIN
MAX
SN74HC273
MIN
MAX
2V
5
4
4
4.5 V
27
18
21
6V
32
21
25
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPHL
tpd
CLR
Any
CLK
Any
tt
Any
VCC
MIN
TA = 25°C
TYP
MAX
SN54HC273
MIN
MAX
SN74HC273
MIN
2V
5
11
4
4
4.5 V
27
50
18
21
6V
32
60
21
25
MAX
UNIT
MHz
2V
55
160
240
200
4.5 V
15
32
48
40
6V
12
27
41
34
2V
56
160
240
200
4.5 V
15
32
48
40
6V
13
27
41
34
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per flip-flop
POST OFFICE BOX 655303
No load
• DALLAS, TEXAS 75265
TYP
35
UNIT
pF
5
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
90%
50%
10%
90%
tr
th
90%
tPHL
Out-of-Phase
Output
90%
tPLH
50%
10%
tf
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOH
50%
10%
VOL
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
5962-8409901VRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
5962-8409901VSA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
84099012A
ACTIVE
LCCC
FK
20
1
TBD
8409901RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
8409901SA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
JM38510/65601BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
JM38510/65601BSA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
SN54HC273J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
SN74HC273DBLE
OBSOLETE
SSOP
DB
20
SN74HC273DBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273DBRE4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273DBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273DWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273N
ACTIVE
PDIP
N
20
CU NIPDAU
N / A for Pkg Type
TBD
POST-PLATE N / A for Pkg Type
Call TI
Call TI
20
Pb-Free
(RoHS)
TBD
Call TI
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC273N3
OBSOLETE
PDIP
N
20
SN74HC273NE4
ACTIVE
PDIP
N
20
SN74HC273NSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273NSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273PWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
SN74HC273PWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273PWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74HC273PWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273PWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273PWTE4
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC273PWTG4
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54HC273FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54HC273J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
SNJ54HC273W
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC273, SN54HC273-SP, SN74HC273 :
• Automotive: SN74HC273-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HC273DBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
SN74HC273DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
SN74HC273NSR
SO
NS
20
2000
330.0
24.4
8.2
13.0
2.5
12.0
24.0
Q1
SN74HC273PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HC273DBR
SN74HC273DWR
SSOP
DB
20
2000
346.0
346.0
33.0
SOIC
DW
20
2000
346.0
346.0
41.0
SN74HC273NSR
SO
NS
20
2000
346.0
346.0
41.0
SN74HC273PWR
TSSOP
PW
20
2000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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