ESDALC5-1BM2, ESDALC5-1BT2 Single line low capacitance Transil™ for ESD protection Features ■ Single line low capacitance Transil diode ■ Bidirectional ESD protection ■ Breakdown Voltage Vbr = 5 V min. ■ Low diode capacitance (26 pF typ at 0 V) ■ Low leakage current < 50 nA @ 3 V ■ Very small PCB area: 0.6 mm² SOD882 ESDALC5-1BM2 Benefits ■ High ESD protection level ■ High integration ■ Suitable for high density boards ■ Lead-free ■ “Halogen-free” according to ECOPACK®2 Figure 1. SOD882T ESDALC5-1BT2 Functional diagram I/O1 Complies with the following standards: ■ ■ IEC 61000-4-2 level 4 – 15 kV (air discharge) – 8 kV (contact discharge) I/O2 MIL STD 883G - Method 3015-7: class 3 – Human body model Description Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems ■ Cellular phone handsets and accessories ■ Video equipment The ESDALC5-1BM2 and ESDALC5-1BT2 are bidirectional single line TVS diodes designed to protect datalines or other I/O ports against ESD transients. These devices are ideal for applications where both reduced line capacitance and board space saving are required. TM: Transil is a trademark of STMicroelectronics February 2010 Doc ID 16936 Rev 1 1/14 www.st.com 14 Characteristics 1 ESDALC5-1BM2, ESDALC5-1BT2 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol VPP PPP (1) Parameter Peak pulse voltage Value Unit ± 30 kV 150 W 9 A IEC 61000-4-2 contact discharge Peak pulse power dissipation (8/20 µs) Tj initial = Tamb IPP Peak pulse current (8/20 µs) Tj Junction temperature - 55 to + 150 °C Storage temperature range - 65 to + 150 °C 260 °C Tstg TL Maximum lead temperature for soldering during 10 s 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Symbol VBR VCL IRM VRM IPP IR IPP RI/O Cline Table 2. Electrical characteristics (definitions) = = = = = = = = = Parameter Breakdown voltage Clamping voltage Leakage current @ VRM Stand-off voltage Peak pulse current Breakdown current Forward current Series resistanc between input and output Input capacitance per line IR IRM IRM IR Test condition Min. Typ. From pin1 to pin2, IR = 1 mA (direct) 11 13 From pin2 to pin1, IR = 1 mA (reverse) 5 8 VRM V VBR Max. VRM = 3 V Rd Square pulse, IPP = 1 A tp = 2.5 µs 650 F = 1 MHz, VR = 0 V 26 50 Doc ID 16936 Rev 1 Unit V IRM Cline 2/14 VBR VRM Electrical characteristics (values, Tamb = 25 °C) Symbol VBR I nA mΩ 30 pF ESDALC5-1BM2, ESDALC5-1BT2 Figure 3. 1.1 Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. PPP[Tjinitial]/PPP[Tjinitial = 25°C] 1000 Relative variation of leakage current versus junction temperature (typical values) IR[Tj]/IR[Tj = 25 °C] 1.0 0.9 0.8 100 0.7 0.6 0.5 0.4 10 0.3 0.2 0.1 0.0 Tj(°C) 0 25 Figure 5. 50 75 100 125 25 10000 1000 1000 100 100 10 10 TP(µs) 1 1 10 Figure 7. 100.0 100 Clamping voltage versus peak pulse current (typical values, exponential waveform, direct) 10.0 1.0 1.0 VCL(V) 12 14 16 18 20 125 PPP(W) TP(µs) Figure 8. 100.0 10 100 Peak pulse power versus exponential pulse duration (reverse) 1 1000 IPP(A) 8 75 1 10.0 0.1 50 Peak pulse power versus Figure 6. exponential pulse duration (direct) PPP(W) 10000 Tj(°C) 1 150 22 10 100 1000 Clamping voltage versus peak pulse current (typical values, exponential waveform, reverse) IPP(A) VCL(V) 0.1 6 Doc ID 16936 Rev 1 8 10 12 14 16 3/14 Characteristics Figure 9. 50 ESDALC5-1BM2, ESDALC5-1BT2 Junction capacitance versus reverse applied voltage (typical values, direct) Figure 10. Junction capacitance versus reverse applied voltage (typical values, reverse) C(pF) 50 40 40 30 30 20 20 10 10 VLINE(V) 0 0 1 2 3 4 VLINE(V) 0 5 Figure 11. ESD response to IEC 61000-4-2 (+15kV air discharge) C(pF) 0 1 2 3 4 5 Figure 12. ESD response to IEC 61000-4-2 (-15kV air discharge) 5 V/Div 5 V/Div C2 C2 100 ns/Div 100 ns/Div Figure 13. S21 attenuation measurement result 0 Figure 14. Static characteristic dB -5 Direct - 10 - 15 - 20 - 25 - 30 Reverse - 35 F(Hz) - 40 100k 4/14 1M 10M 100M 1G Doc ID 16936 Rev 1 ESDALC5-1BM2, ESDALC5-1BT2 2 Ordering information scheme Ordering information scheme Figure 15. Ordering information scheme ESDA LC 5 - 1 B x2 ESD array Low capacitance Breakdown voltage 5 = 5 Volts min Number of lines Directional B = Bi-directional Package M2 = SOD882 T2 = Thin SOD882 Doc ID 16936 Rev 1 5/14 Package information 3 ESDALC5-1BM2, ESDALC5-1BT2 Package information ● Epoxy meets UL94, V0 ● Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 16. SOD882 dimension definitions D INDEX AREA (D/2 x E/2) E A A1 b1 b2 INDEX AREA (D/2 x E/2) L1 L2 OPTIONAL PIN # 1 ID Table 3. e SOD882 dimension values Dimensions Ref. 6/14 Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.40 0.47 0.50 0.016 0.019 0.020 A1 0.00 0.05 0.000 b1 0.20 0.25 0.30 0.008 0.010 0.012 b2 0.20 0.25 0.30 0.008 0.010 0.012 0.002 D 1.00 0.039 E 0.60 0.024 e 0.65 0.026 L1 0.45 0.50 0.55 0.018 0.020 0.022 L2 0.45 0.50 0.55 0.018 0.020 0.022 Doc ID 16936 Rev 1 ESDALC5-1BM2, ESDALC5-1BT2 Package information Figure 17. SOD882 footprint in mm (inches) 0.55 0.022 0.020 0.55 0.022 Figure 18. SOD882 marking 0.50 G Pin1 Pin 2 0.40 0.016 Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 19. SOD882 tape and reel specifications 2.0 ± 0.05 Ø 1.50 ± 0.10 4.0 ± 0.1 1.75 ± 0.1 Bar indicates Pin 1 3.5 ±- 0.05 X X X 0.68 ± 0.05 X X X All dimensions in mm X 0.66 ± 0.05 1.10 ± 0.05 0.20 ± 0.05 8.0 + 0.3 /-0.1 Note: 2.0 ± 0.10 User direction of unreeling Doc ID 16936 Rev 1 7/14 Package information ESDALC5-1BM2, ESDALC5-1BT2 Figure 20. SOD882T dimension definitions D INDEX AREA (D/2 x E/2) E A1 A b1 b2 INDEX AREA (D/2 x E/2) L1 L2 OPTIONAL PIN # 1 ID Table 4. e SOD882T dimension values Dimensions Ref. Millimeters Min. Inches Typ. Max. Min. Typ. Max. A 0.30 0.40 0.012 0.016 A1 0.00 0.05 0.000 0.002 b1 0.20 0.25 0.30 0.008 0.010 0.012 b2 0.20 0.25 0.30 0.008 0.010 0.012 D 1.00 0.039 E 0.60 0.024 e 0.65 0.026 L1 0.45 0.50 0.55 0.018 0.020 0.022 L2 0.45 0.50 0.55 0.018 0.020 0.022 Figure 21. SOD882T footprint 0.55 0.022 0.020 0.55 0.022 Figure 22. SOD882T marking 0.50 Pin1 H Pin 2 0.40 0.016 Note: 8/14 Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Doc ID 16936 Rev 1 ESDALC5-1BM2, ESDALC5-1BT2 Package information Figure 23. SOD882T tape and reel specifications 2.0 ± 0.05 Ø 1.50 ± 0.10 4.0 ± 0.1 1.75 ± 0.1 Bar indicates Pin 1 3.5 ±- 0.05 1.15 ± 0.05 8.0 ±0.1 0.20 ± 0.05 X X X 0.70 ± 0.05 X X All dimensions in mm X X 0.47 ± 0.05 2.0 ± 0.10 User direction of unreeling Doc ID 16936 Rev 1 9/14 Recommendation on PCB assembly ESDALC5-1BM2, ESDALC5-1BT2 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 24. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 25. Recommended stencil window position Package footprint Lead footprint on PCB Lead footprint on PCB Stencil window position 0.39 mm Stencil window position 0.45 mm 0.05 mm 10/14 Doc ID 16936 Rev 1 0.05 mm ESDALC5-1BM2, ESDALC5-1BT2 4.2 4.3 4.4 Recommendation on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Doc ID 16936 Rev 1 11/14 Recommendation on PCB assembly 4.5 ESDALC5-1BM2, ESDALC5-1BT2 Reflow profile Figure 26. ST ECOPACK® recommended soldering reflow profile for PCB mounting Note: 12/14 Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 16936 Rev 1 ESDALC5-1BM2, ESDALC5-1BT2 5 Ordering information Ordering information Table 5. Ordering information Order code Marking(1) Package Weight Base qty Delivery mode ESDALC5-1BM2 G SOD882 0.92 mg 12000 Tape and reel ESDALC5-1BT2 H SOD882T 0.76 mg 12000 Tape and reel 1. The marking can be rotated by 90° to differentiate assembly location 6 Revision history Table 6. Document revision history Date Revision 02-Feb-2010 1 Changes Initial release. Doc ID 16936 Rev 1 13/14 ESDALC5-1BM2, ESDALC5-1BT2 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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