STMICROELECTRONICS L3G4200D

L3G4200D
MEMS motion sensor:
three-axis digital output gyroscope
Features
■
Three selectable full scales
(±250/500/2000 dps)
■
I2C/SPI digital output interface
■
16 bit rate value data output
■
Two digital output lines (interrupt and
dataready)
■
Integrated low and high pass filters with user
selectable bandwidth
■
Embedded self-test
■
Wide supply voltage, 2.4 V to 3.6 V
■
Low voltage compatible IOs, 1.8 V
■
Embedded power-down and sleep mode
■
High shock survivability
■
Extended operating temperature range
(-40 °C to +85 °C)
■
ECOPACK® RoHS and “Green” compliant
(see Section 6)
LGA-16 (4x4x1 mm)
The L3G4200D is a low-power three-axis
gyroscope providing three different user
selectable full scales (±250/±500/±2000 dps).
Applications
■
Gaming and virtual reality input devices
■
Motion control with MMI (man-machine
interface)
■
GPS navigation systems
■
Appliances and robotics
Table 1.
Description
It includes a sensing element and an IC interface
able to provide the detected angular rate to the
external world through a digital interface
(I2C/SPI).
The sensing element is manufactured using
specialized micromachining processes, while the
IC interface is realized using a CMOS technology
that allows designing a dedicated circuit which is
trimmed to better match the sensing element
characteristics.
The L3G4200D is available in a plastic land grid
array (LGA) package and provides excellent
temperature stability and high resolution over an
extend operating temperature range (-40 °C to
+85 °C).
Device summary
Order code
Temperature range (°C)
Package
-40 to + 85
LGA-16 (4x4x1)
L3G4200D
Tray
L3G4200DTR
February 2010
Packing
Tape and reel
Doc ID 17116 Rev 1
1/24
www.st.com
24
Contents
L3G4200D
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
2
3
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2
I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.2
Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.3
Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
5
2.3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1
5.2
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.3
SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24
Doc ID 17116 Rev 1
L3G4200D
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Mechanical characteristics @ Vdd = 3.0 V, T = 25 °C unless otherwise noted . . . . . . . . . . 8
Electrical characteristics @ Vdd =3.0 V, T=25 °C unless otherwise noted. . . . . . . . . . . . . . 9
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 17
Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Doc ID 17116 Rev 1
3/24
List of figures
L3G4200D
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
4/24
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
L3G4200D external low-pass filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C slave timing diagram (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Doc ID 17116 Rev 1
L3G4200D
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
+Ω
Block diagram
x,y,z
X+
CHARGE
AMP
Y+
MIXER
LOW-PASS
FILTER
A
D
C
M
U
X
Z-
F
I
L
T
E
R
I
N
G
D
I
G
I
T
A
L
Z+
YX-
I2C
SPI
CS
SCL/SPC
SDA/SDO/SDI
SDO
DRIVING MASS
Feedback loop
TRIMMING
CIRCUITS
REFERENCE
CONTROL LOGIC
&
INTERRUPT GEN.
CLOCK
&
PHASE GENERATOR
INT
DRDY
AM06080v1
The vibration of the structure is maintained by a drive circuitry in a feedback loop.The
sensing signal is filtered and appears as digital signal at the output.
1.1
Pin description
Figure 2.
Pin connection
13
Y
RES
1
BOTTOM
VIEW
RES
X
RES
9
SDA/SDI/SDO
SDO/SA0
5
CS
DRDY
INT
DIRECTIONS OF THE
DETECTABLE
ANGULAR RATES
Vdd_IO
SCL/SPC
4
8
RES
(TOP VIEW)
16
12
RES
+Ω
Vdd
+Ω
RES
X
GND
1
Z
PLLFILT
+Ω
AM06081v1
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Block diagram and pin description
Table 2.
L3G4200D
Pin description
Pin#
Name
1
Vdd_IO
2
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
3
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
4
SDO
SA0
SPI serial data output (SDO)
I2C less significant bit of the device address (SA0)
5
CS
6
DRDY
7
INT
8
Reserved
Connect to GND
9
Reserved
Connect to GND
10
Reserved
Connect to GND
11
Reserved
Connect to GND
12
Reserved
Connect to GND
13
GND
14
PLLFILT
Phase Locked Loop Filter (see Figure_3)
15
Reserved
Connect to Vdd
16
Vdd
Figure 3.
Function
Power supply for I/O pins
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
Data ready
Programmable Interrupt
0 V supply
Power supply
L3G4200D external low-pass filter values(a)
#APACITORFOR
,OWPASSFILTER
TOPIN
#
#
2
'.$
".W
6/24
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L3G4200D
Block diagram and pin description
Table 3.
Filter values
Component
Typical values
C1
10 nF
R2
10 kΩ
C2
470 pF
a. Pin 14 PLLFILT maximum voltage level is equal to Vdd.
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Mechanical and electrical specifications
L3G4200D
2
Mechanical and electrical specifications
2.1
Mechanical characteristics
Table 4.
Mechanical characteristics @ Vdd = 3.0 V, T = 25 °C unless otherwise noted(1)
Symbol
Parameter
Test condition
Min.
Typ.(2)
Max.
Unit
±250
FS
Angular rate range
User selectable
±500
dps
±2000
So
SoDr
DVoff
OffDr
NL
DST
Rn
Sensitivity
Sensitivity change vs.
temperature
Digital zero-rate level
FS = 250 dps
8.75
FS = 500 dps
17.50
FS = 2000 dps
70
From -40 °C to +85 °C
±2
FS = 250 dps
±10
FS = 500 dps
±15
FS = 2000 dps
±75
%
dps
Zero-rate level change
vs temperature
FS = 250 dps
±0.03
dps/°C
FS = 2000 dps
±0.04
dps/°C
Non linearity(3)
Best fit straight line
0.2
% FS
FS = 250 dps
130
Self-test output change FS = 500 dps
200
Rate noise density
ODR
Digital output data rate
Top
Operating temperature
range
dps
FS = 2000 dps
530
BW = 40 Hz
0.03
dps/vHz
100/200/
400/800
Hz
-40
1. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 5.
2. Typical specifications are not guaranteed.
3. Guaranteed by design.
8/24
mdps/digit
Doc ID 17116 Rev 1
+85
°C
L3G4200D
Mechanical and electrical specifications
2.2
Electrical characteristics
Table 5.
Electrical characteristics @ Vdd =3.0 V, T=25 °C unless otherwise noted(1)
Symbol
Vdd
Vdd_IO
Idd
IddSL
IddPdn
Top
Parameter
Test condition
Supply voltage
I/O pins supply voltage
(3)
Min.
Typ.(2)
Max.
Unit
2.4
3.0
3.6
V
Vdd+0.1
V
1.71
Supply current
Supply current in sleep
mode(4)
Supply current in
power-down mode
6.1
mA
1.5
mA
5
µA
Selectable by digital
interface
Operating temperature
range
-40
+85
°C
1. The product is factory calibrated at 3.0V.
2. Typical specifications are not guaranteed.
3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the reading
chain is powered off.
4. Sleep mode allows to reduce turn on time compared to Power down.
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Mechanical and electrical specifications
L3G4200D
2.3
Communication interface characteristics
2.3.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6.
SPI slave timing values
Value(1)
Symbol
Parameter
Unit
Min.
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
8
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
Max.
100
ns
10
MHz
ns
50
6
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
Figure 4.
#3
SPI slave timing diagram (2)
TC30#
TSU#3
TH#3
30# TSU3)
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TH3)
,3").
-3").
TV3/
3$/ -3"/54
TDIS3/
TH3/
,3"/54
!-V
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port
10/24
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L3G4200D
Mechanical and electrical specifications
I2C - Inter IC control interface
2.3.2
Subject to general operating conditions for Vdd and Top.
Table 7.
I2C slave timing values
I2C Standard mode(1)
Symbol
I2C Fast mode (1)
Parameter
f(SCL)
Unit
SCL clock frequency
Min
Max
Min
Max
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
kHz
µs
0
ns
3.45
0
0.9
tr(SDA) tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb (2)
300
tf(SDA) tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb (2)
300
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
µs
ns
µs
tw(SP:SR)
Bus free time between STOP
and START condition
1. Data based on standard I2C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.
I2C slave timing diagram (3)
Figure 5.
REPEATED
START
START
tsu(SR)
tw(SP:SR)
SDA
tf(SDA)
tsu(SDA)
tr(SDA)
START
th(SDA)
tsu(SP)
STOP
SCL
th(ST)
3
tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports
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Absolute maximum ratings
3
L3G4200D
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 8.
Absolute maximum ratings
Symbol
Ratings
Maximum value
Unit
Vdd
Supply voltage
-0.3 to 4.8
V
TSTG
Storage temperature range
-40 to +125
°C
10,000
g
2 (HBM)
kV
Sg
ESD
Acceleration g for 0.1 ms
Electrostatic discharge protection
This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part
This is an ESD sensitive device, improper handling can cause permanent damage to
the part
12/24
Doc ID 17116 Rev 1
L3G4200D
Absolute maximum ratings
3.1
Terminology
3.1.1
Sensitivity
An angular rate gyroscope is device that produces a positive-going digital output for
counterclockwise rotation around the sensible axis considered. Sensitivity describes the
gain of the sensor and can be determined by applying a defined angular velocity to it. This
value changes very little over temperature and time.
3.1.2
Zero-rate level
Zero-rate level describes the actual output signal if there is no angular rate present. Zerorate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and
therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit
board or after exposing it to extensive mechanical stress. This value changes very little over
temperature and time.
3.1.3
Self-test
Self-test allows to test the mechanical and electric part of the sensor, allowing the seismic
mass to be moved by means of an electrostatic test-force. When the ST is activated by IC,
an actuation force is applied to the sensor, emulating a definite Coriolis force. In this case
the sensor output will exhibit an output change.
3.2
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/mems.
Doc ID 17116 Rev 1
13/24
Digital main blocks
L3G4200D
4
Digital main blocks
4.1
Block diagram
Figure 6.
Block diagram
/UT?3EL
$ATA2EG
,0&
!$#
,0&
(0&
(0EN
)#
30)
).4?3EL
)NTERRUPT
GENERATOR
3#22%'
#/.&2%'
).4
!-V
14/24
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L3G4200D
5
Digital interfaces
Digital interfaces
The registers embedded inside the L3G4200D may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, CS
line must be tied high (i.e connected to Vdd_IO).
Table 9.
Serial interface pin description
Pin name
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
CS
SCL/SPC
SDA/SDI/SDO
I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I2C less significant bit of the device address
SDO
5.1
Pin description
I2C serial interface
The L3G4200D I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 10.
I2C terminology
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistor. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the
normal mode.
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Digital interfaces
5.1.1
L3G4200D
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the L3G4200D is 110100xb. SDO pin can be used
to modify less significant bit of the device address. If SDO pin is connected to voltage supply
LSb is ‘1’ (address 1101001b) else if SDO pin is connected to ground LSb value is ‘0’
(address 1101000b). This solution permits to connect and address two different gyroscopes
to the same I2C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the L3G4200D behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7
LSb represent the actual register address while the MSB enables address auto increment. If
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented
to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged. Table 11 explains how
the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 11.
Command
SAD[6:1]
SAD[0] = SDO
R/W
SAD+R/W
Read
110100
0
1
11010001 (D1h)
Write
110100
0
0
11010000 (D0h)
Read
110100
1
1
11010011 (D3h)
Write
110100
1
0
11010010 (D2h)
Table 12.
Master
Slave
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SAD+Read/Write patterns
Transfer when Master is writing one byte to slave
ST
SAD + W
SUB
SAK
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DATA
SAK
SP
SAK
L3G4200D
Digital interfaces
Table 13.
Master
Transfer when Master is writing multiple bytes to slave
ST
SAD + W
Slave
SAK
Table 14.
Master
ST
SAD + W
DATA
SAK
SUB
SAK
SAK
SP
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Transfer when Master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
Slave
DATA
Transfer when Master is receiving (reading) one byte of data from slave
Slave
Table 15.
SUB
SUB
SAK
SR SAD+R
SAK
MAK
SAK DATA
MAK
DATA
NMAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
5.2
SPI bus interface
The SPI is a bus slave. The SPI allows to write and read the registers of the device.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
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Digital interfaces
L3G4200D
Figure 7.
Read and write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the Read Register and Write Register commands are completed in 16 clock pulses or
in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address will be auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb
first).
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is 0 the address used to read/write data remains the same for every block. When MS bit
is 1 the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
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L3G4200D
5.2.1
Digital interfaces
SPI read
Figure 8.
SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
Figure 9.
Multiple bytes SPI read protocol (2 bytes example)
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8
5.2.2
SPI write
Figure 10. SPI write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
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Digital interfaces
L3G4200D
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device
(MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
Figure 11. Multiple bytes SPI write protocol (2 bytes example)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
5.2.3
SPI read in 3-wires mode
3-wires mode is entered by setting to 1 bit SIM (SPI serial interface mode selection) in
CTRL_REG2.
Figure 12. SPI read protocol in 3-wires mode
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI Read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
Multiple read command is also available in 3-wires mode.
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L3G4200D
6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
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Package information
L3G4200D
Figure 13. LGA-16: mechanical data and package dimensions
Dimensions
Ref.
mm
Min.
Typ.
A1
Outline and
mechanical data
1.100
A2
0.855
A3
0.200
d
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Max.
0.300
D1
3.850
4.000
4.150
E1
3.850
4.000
4.150
L2
1.950
M
0.100
N1
0.650
N2
0.975
P1
1.750
P2
1.525
T1
0.400
T2
0.300
k
0.050
LGA-16 (4x4x1 mm)
Land Grid Array Package
Doc ID 17116 Rev 1
L3G4200D
7
Revision history
Revision history
Table 16.
Document revision history
Date
Revision
11-Feb-2010
1
Changes
First release.
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L3G4200D
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