STMICROELECTRONICS L9951XP

L9951
L9951XP
Rear door actuator driver
Features
Type
Outputs(1)
Ron(2)
IOUT
VS
L9951
L9951XP
OUT1
OUT2
OUT3
OUT4
OUT5
150 mΩ
200 mΩ
200 mΩ
800 mΩ
800 mΩ
7.4 A
5A
5A
1.25 A
1.25 A
28 V
PowerSO-36
PowerSSO-36
1. See block diagram.
2. Typical values.
Applications
■
One half bridge for 7.4 A load (Ron = 150 mΩ)
■
■
Two half bridges for 5 A load (Ron = 200 mΩ)
■
Two highside drivers for 1.25 A load
(Ron = 800 mΩ)
■
Programmable softstart function to drive loads
with higher inrush currents (i.e.current > 7.4A,
>5A, >1.25A)
■
Very low current consumption in standby mode
(IS < 3µA, typ. Tj ≤ 85°C)
■
All outputs short circuit protected
■
Current monitor output for all highside drivers
■
All outputs over temperature protected
■
Open-load diagnostic for all outputs
■
Overload diagnostic for all outputs
■
Programmable PWM control of all outputs
■
Charge pump output for reverse polarity
protection
Table 1.
Rear door actuator driver with bridges for door
lock and safe lock and two 5W or 10W - light
bulbs.
Description
The L9951 and L9951XP are microcontroller
driven, multifunctional rear door actuator drivers
for automotive applications. Up to two DC motors
and two grounded resistive loads can be driven
with three half bridges and two hide side drivers.
The integrated standard serial peripheral interface
(SPI) controls all operation modes (forward,
reverse, brake and high impedance). All
diagnostic information is available via the SPI.
Device summary
Order codes
Package
May 2010
Tube
Tape and reel
PowerSO-36
L9951
L9951TR
PowerSSO-36
L9951XP
L9951XPTR
Doc ID 14173 Rev 8
1/36
www.st.com
1
Contents
L9951 / L9951XP
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
2/36
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10
2.5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2
Standby - mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5
Over-voltage and under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20
3.7
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8
Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10
PWM input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12
Programmable softstart function to drive loads with higher inrush current 21
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3
Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5
Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6
Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Doc ID 14173 Rev 8
L9951 / L9951XP
4.8
Contents
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7
6.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2
PowerSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3
PowerSSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4
PowerSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5
PowerSSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 14173 Rev 8
3/36
List of tables
L9951 / L9951XP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
4/36
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OUT 1 - OUT 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
EN, CSN timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI - Input data and status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI - Input data and status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 14173 Rev 8
L9951 / L9951XP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI - driver turn-on/off timing, minimum CSN HI time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 21
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSO-36TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSO-36TM tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSSO-36TM tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-36TM tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 14173 Rev 8
5/36
Block diagram and pin description
1
L9951 / L9951XP
Block diagram and pin description
Figure 1.
Block diagram
* Note: Value of capacitor has to be choosen carefully to limit the VS
voltage below absolute maximum ratings in case of an unexpected
*
VS
100µF
VREG
100k
10k
freewheeling condition of inductive loads (e.g. TSD, POR)
VBAT
Reverse
Polarity
Protection
CP
100nF
Charge
Pump
EMC
Optimization
100
+ 10
VCC
**1k
DI
DO
CLK
CSN
EN
SPI
Interface
100nF
** 1k
** 1k
** 1k
** 1k
OUT1
OUT2
Driver Interface & Diagnostic
VCC
Lock
M
Safe Lock
OUT3
M
Exterior Light
OUT4
OUT5
Safety Light
µC
**1k
CM / PWM
MUX
5
GND ** Note: Resistors between µC and L9951 are recommended to limit currents
for negative voltage transients at VBAT (e.g. ISO type 1 pulse)
+ Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior
6/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Block diagram and pin description
Table 2.
Pin
Pin definitions and functions
Symbol
Function
GND
Ground .
Reference potential.
Note: For the capability of driving the full current at the outputs all pins of
GND must be externally connected.
VS
Power supply voltage (external reverse protection required).
For EMI reason a ceramic capacitor as close as possible to GND is
recommended.
Note: for the capability of driving the full current at the outputs all pins of
VS must be externally connected.
OUT1
Half-bridge output 1.
The output is built by a high side and a low side switch, which are
internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal reverse diode (bulk-draindiode: high side driver from output to VS, low side driver from GND to
output). This output is over-current and open-load protected.
Note: for the capability of driving the full current at the outputs all pins of
OUT1 must be externally connected.
DI
Serial data input.
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is a 16bit control word and the least significant
bit (LSB, bit 0) is transferred first.
CM/PWM
Current monitor output/PWM input.
Depending on the selected multiplexer bits (bit 9, 10, 11) of Input Data
Register this output sources an image of the instant current through the
corresponding high side driver with a ratio of 1/10.000. This pin is
bidirectional. The microcontroller can overwrite the current monitor signal
to provide a PWM input for all outputs.
Testmode:
If CSN is raised above 7.5V the device will enter the test mode. In test
mode this output can be used to measure some internal signals (see
Table 18).
CSN
Chip select not input / Testmode .
This input is low active and requires CMOS logic levels. The serial data
transfer between L9951 and micro controller is enabled by pulling the
input CSN to low level. If an input voltage of more than 7.5V is applied to
CSN pin the L9951 will be switched into a test mode.
11
DO
Serial data output .
The diagnosis data is available via the SPI and this tristate-output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high).
12
VCC
Logic supply voltage .
For this input a ceramic capacitor as close as possible to GND is
recommended.
13
CLK
Serial clock input .
This input controls the internal shift register of the SPI and requires
CMOS logic levels.
1, 18, 19,
36
6, 7, 14,
15, 23, 24,
29, 32
3, 4, 34
8
9
10
Doc ID 14173 Rev 8
7/36
Block diagram and pin description
Table 2.
Pin definitions and functions (continued)
Pin
Symbol
Function
16, 17
OUT2
Half-bridge output 2 (see OUT1 - pin 3, 4).
Note: for the capability of driving the full current at the outputs all pins of
OUT2 must be externally connected.
20, 21
OUT3
Half-bridge output 3 (see OUT1 - pin 3, 4).
Note: for the capability of driving the full current at the outputs all pins of
OUT3 must be externally connected.
26
CP
Charge Pump Output .
This output is provided to drive the gate of an external n-channel power
MOS used for reverse polarity protection (see Figure 1).
27
EN
Enable input.
If Enable input is forced to GND the device will enter Standby-Mode. The
outputs will be switched off and all registers will be cleared
33, 35
Figure 2.
8/36
L9951 / L9951XP
High side driver output 4, 5 .
The output is built by a high side switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
OUT4, OUT5 missing. For ESD reason a diode to GND is present but the energy which
can be dissipated is limited. The high side driver is a power DMOS
transistor with an internal reverse diode from the output to VS (bulkdrain-diode). The output is over-current and open-load protected.
Configuration diagram (top view)
GND
1
36
GND
N.C.
2
35
OUT5
OUT1
3
34
OUT1
OUT1
4
33
OUT4
N.C.
5
32
VS
VS
6
31
VS
7
30
N.C.
N.C.
N.C.
DI
8
29
CM/PWM
9
CSN
DO
28
VS
VS..
N.C.
10
27
EN
11
26
CP
VCC
12
25
N.C.
CLK
13
24
VS
VS
14
23
VS
15
22
VS
N.C.
OUT2
16
21
OUT3
OUT2
17
20
OUT3
GND
18
19
GND
Chip
Leadframe
Doc ID 14173 Rev 8
L9951 / L9951XP
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics sure
program and other relevant quality document
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
-0.3 to 28
V
40
V
-0.3 to 5.5
V
Digital input / output voltage
-0.3 to VCC + 0.3
V
VCM
Current monitor output
-0.3 to VCC + 0.3
V
VCP
Charge pump output
-25 to VS + 11
V
DC supply voltage
VS
Single pulse tmax < 400ms
Stabilized supply voltage, logic supply
VCC
VDI,VDO,VCLK,VCSN,VEN
2.2
IOUT1,2,3
Output current
±10
A
IOUT4,5
Output current
±5
A
Parameter
Value
Unit
All pins
± 4(1)
kV
(2)
±8
kV
ESD protection
Table 4.
ESD protection
Output pins: OUT1 - OUT5
1. HBM according to CDF-AEC-Q100-002.
2. HBM with all unzapped pins grounded.
2.3
Thermal data
Table 5.
Thermal data
Symbol
Parameter
Value
Unit
Tj
Operating junction temperature
-40 to 150
°C
Doc ID 14173 Rev 8
9/36
Electrical specifications
2.4
L9951 / L9951XP
Temperature warning and thermal shutdown
Table 6.
Temperature warning and thermal shutdown
Symbol
Parameter
Min.
TjTW ON
Temperature warning threshold junction
temperature
Tj
increasing
TjTW OFF
Temperature warning threshold junction
temperature
Tj
decreasing
Max.
Unit
150
°C
130
TjTW HYS Temperature warning hysteresis
°C
5
TjSD ON
Thermal shutdown threshold junction
temperature
Tj
increasing
TjSD OFF
Thermal shutdown threshold junction
temperature
Tj
decreasing
°K
170
°C
150
TjSD HYS Thermal shutdown hysteresis
2.5
Typ.
°C
5
°K
Electrical characteristics
VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 7.
Symbol
VS
Supply
Parameter
Test condition
Operating supply voltage
range
VS DC supply current
IS
VS quiescent supply current
10/36
Min.
Typ.
7
Max.
Unit
28
V
VS = 13V, VCC = 5.0V
active mode
OUT1 - OUT5 floating
7
20
mA
VS = 13V, VCC = 0V
standby mode
OUT1 - OUT5 floating
Ttest =-40°C, 25°C
3
10
µA
Ttest = 130°C
6
20
µA
Doc ID 14173 Rev 8
L9951 / L9951XP
Table 7.
Symbol
Electrical specifications
Supply (continued)
Parameter
Test condition
Typ.
Max.
Unit
VCC DC supply current
VS = 13V, VCC = 5.0V
CSN = VCC
active mode
1
3
mA
VCC quiescent supply
current
VS = 13V, VCC = 5.0V
CSN = VCC
standby mode
OUT1 - OUT5 floating
1
3
µA
Sum quiescent supply
current
VS = 13V, VCC = 5.0V
CSN = VCC
standby mode
OUT1 - OUT5 floating
7
23
µA
Typ.
Max.
Unit
ICC
IS + ICC
Table 8.
Symbol
Min.
Overvoltage and undervoltage detection
Parameter
Test condition
Min.
VSUV ON VS UV-threshold voltage
VS increasing
6.0
7.2
V
VSUV OFF VS UV-threshold voltage
VS decreasing
5.4
6.5
V
VSUV hyst VS UV-hysteresis
VSUV ON - VSUV OFF
VSOV OFF VS OV-threshold voltage
VS increasing
18
VSOV ON VS OV-threshold voltage
VS decreasing
17.5
VSOV hyst VS OV-hysteresis
VSOV OFF - VSOV ON
VPOR OFF Power-on-reset threshold
VCC increasing
VPOR ON Power-on-reset threshold
VCC decreasing
VPOR hyst Power-on-reset hysteresis
VPOR OFF - VPOR ON
Table 9.
Symbol
0.55
24.5
V
V
0.5
V
4.4
3.1
V
V
0.3
V
Current monitor output
Parameter
Test condition
Min.
Typ.
VCM
Functional voltage range
VCC = 5V
ICM,r
Current monitor output
ratio:
ICM / IOUT1,2,3,4,5
0V ≤ VCM ≤ 4V, VCC=5V
1:10000
Current monitor accuracy
0V ≤ VCM≤ 4V,
VCC=5V,
IOUT1-5,low =500mA
IOUT1,high =6A
IOUT2,3,high =4.9A
IOUT4,5,high =1.2A
(FS=full scale=600 μA)
4% +
1%FS
ICM acc
V
Doc ID 14173 Rev 8
0
Max.
Unit
4
V
-
8% +
2%FS
-
11/36
Electrical specifications
Table 10.
Symbol
VCP
L9951 / L9951XP
Charge pump output
Parameter
Charge pump output
voltage
ICP
Charge pump output
current
Table 11.
OUT 1 - OUT 5
Symbol
RON OUT1
Parameter
On-resistance to supply
or GND
RON OUT2 On-resistance to supply
RON OUT3 or GND
rON OUT4, On-resistance to supply
rON OUT5 or GND
12/36
Test condition
Min.
VS=8V, ICP = -60µA
Typ.
Max.
Unit
6
13
V
VS=10V, ICP = -80µA
8
13
V
VS≥12V, ICP = -100µA
10
13
V
VCP = VS+10V
VS =13.5V
100
150
300
µA
Test condition
Min.
Typ.
Max.
Unit
VS = 13.5 V, Tj = 25 °C,
IOUT1 = ± 3 A
150
200
mΩ
VS = 13.5 V, Tj = 125 °C,
IOUT1 = ± 3 A
225
300
mΩ
VS = 8.0 V, Tj = 25 °C,
IOUT1 = ± 3 A
150
200
mΩ
VS = 13.5 V, Tj = 25 °C,
IOUT2,3 = ± 3 A
200
270
mΩ
VS = 13.5 V, Tj = 125 °C,
IOUT2,3 = ± 3 A
300
400
mΩ
VS = 8.0 V, Tj = 25 °C,
IOUT2,3 = ± 3 A
200
270
mΩ
VS = 13.5 V, Tj = 25 °C,
IOUT4,5 = ± 0.8 A
800
1100
mΩ
VS = 13.5 V, Tj = 125 °C,
IOUT4,5 = ± 0.8 A
1250
1700
mΩ
VS = 8.0 V, Tj = 25 °C,
IOUT4,5 = ± 0.8 A
800
1100
mΩ
|IOUT1|
Output current limitation
to supply or GND
Sink and source
7.4
15.5
A
|IOUT2|,
|IOUT3|
Output current limitation
to supply or GND
Sink and source
5.0
10.5
A
|IOUT4|,
|IOUT5|
Output current limitation
to GND
Source
1.25
2.6
A
td ON H
Output delay time,
highside driver on
VS = 13.5 V,
corresponding lowside
driver is not active
20
40
90
µs
td OFF H
Output delay time,
highside driver off
VS = 13.5 V
80
200
300
µs
td ON L
Output delay time,
lowside driver on
VS = 13.5 V,
corresponding highside
driver is not active
20
60
80
µs
Doc ID 14173 Rev 8
L9951 / L9951XP
Table 11.
Electrical specifications
OUT 1 - OUT 5 (continued)
Symbol
Parameter
td OFF L
Output delay time,
lowside driver off
VS = 13.5 V
tD HL
Cross current protection
time, source to sink
tD LH
Cross current protection
time, sink to source
IQLH
VOUT1-5 = 0V, standby
Switched-off output
current highside drivers of mode
OUT1-5
VOUT1-5 = 0V, active mode
IQLL
Test condition
Switched-off output
current lowside drivers of
OUT1-3
Min.
Typ.
Max.
Unit
80
150
300
µs
td ON L - td OFF H,
200
400
µs
td ON H - td OFF L
200
400
µs
0
-2
-5
µA
-40
-15
0
µA
0
50
100
µA
-40
-15
0
µA
VOUT1-3 = VS, standby
mode
VOUT1-3= VS, active mode
IOLD1
Open-load detection
current of OUT1
70
160
240
mA
IOLD23
Open-load detection
current of OUT2, OUT3
70
160
240
mA
IOLD45
Open-load detection
current of OUT4 and
OUT5
5
15
40
mA
tdOL
Minimum duration of
open-load condition to set
the status bit
500
3000
µs
tISC
Minimum duration of
over-current condition to
switch off the driver
10
100
µs
dVOUT1/dt Slew rate of OUT1
VS =13.5 V
Iload = ±1.5 A
0.1
0.2
0.4
V/µs
dVOUT23/dt Slew rate of OUT2, OUT3
VS = 13.5 V
Iload = ±1.5 A
0.1
0.2
0.4
V/µs
dVOUT45/dt Slew rate of OUT4, OUT5
VS = 13.5 V
Iload = - 0.8 A
0.1
0.2
0.4
V/µs
Doc ID 14173 Rev 8
13/36
Electrical specifications
2.6
L9951 / L9951XP
SPI - electrical characteristics
(VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin).
Table 12.
Symbol
tset
Table 13.
Symbol
Test condition
Internal startup time
Switching from standby
to active mode. Time
until not Ready Bit goes
low.
Min.
Typ.
Max.
Unit
80
300
µs
Max.
Unit
Inputs: CSN, CLK, PWM1/2 and DI
Parameter
Test condition
Min.
Typ.
1.5
2.0
Input low level
VCC = 5V
VinH
Input high level
VCC = 5V
VinHyst
Input hysteresis
VCC = 5V
0.5
ICSN in
Pull up current at input CSN
VCSN = 3.5V VCC = 5V
-50
-25
-10
µA
ICLK in
Pull down current at input CLK
VCLK = 1.5V
10
25
50
µA
VDI = 1.5V
10
25
50
µA
100
210
480
kΩ
10
15
pF
IDI in
Pull down current at input DI
IEN in
Pull down resistance at input
EN
Input capacitance at input
CLK, DI and PWM
3.0
VCC = 0 to 5.3V
V
3.5
V
V
Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 14.
Symbol
14/36
Parameter
VinL
C in
Note:
Delay time from standby to active mode
DI timing(1)
Parameter
Test condition
Min.
Typ.
Max.
Unit
tCLK
Clock period
VCC = 5V
1000
ns
tCLKH
Clock high time
VCC = 5V
400
ns
tCLKL
Clock low time
VCC = 5V
400
ns
tset CSN
CSN setup time, CSN low
before rising edge of CLK
VCC = 5V
400
ns
tset CLK
CLK setup time, CLK high
before rising edge of CSN
VCC = 5V
400
ns
tset DI
DI setup time
VCC = 5V
200
ns
thold time
DI hold time
VCC = 5V
200
ns
Doc ID 14173 Rev 8
L9951 / L9951XP
Electrical specifications
DI timing(1) (continued)
Table 14.
Symbol
1.
Note:
Parameter
Test condition
Min.
Typ.
Max.
Unit
tr in
Rise time of input signal DI,
CLK, CSN
VCC = 5V
100
ns
tf in
Fall time of input signal DI,
CLK, CSN
VCC = 5V
100
ns
Typ.
Max.
Unit
0.2
0.4
V
See Figure 3 and Figure 4
DI timing parameters tested in production by a passed/failed test:
Tj= -40°C/+25°C: SPI communication @2MHZ.
Tj= +125°C: SPI communication @1.25MHZ.
Table 15.
Symbol
DO
Parameter
Test condition
Min.
VDOL
Output low level
VCC = 5 V, ID = -4mA
VDOH
Output high level
VCC = 5 V, ID = 4 mA
VCC
-0.4
IDOLK
Tristate leakage current
VCSN = VCC,
0V < VDO < VCC
-10
Tristate input capacitance
VCSN = VCC,
0V < VCC < 5.3V
CDO (1)
VCC
-0.2
V
10
µA
15
pF
Typ.
Max.
Unit
10
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16.
Symbol
DO timing(1)
Parameter
Test condition
Min.
tr DO
DO rise time
CL = 100 pF, Iload = -1mA
80
140
ns
tf DO
DO fall time
CL = 100 pF, Iload = 1mA
50
100
ns
ten DO tri L
DO enable time
from tristate to low level
CL = 100 pF, Iload = 1mA
pull-up load to VCC
100
250
ns
tdis DO L tri
DO disable time
from low level to tristate
CL = 100 pF, Iload = 4 mA
pull-up load to VCC
380
450
ns
ten DO tri H
DO enable time
CL =100 pF, Iload = -1mA
from tristate to high level pull-down load to GND
100
250
ns
tdis DO H tri
DO disable time
CL = 100 pF, Iload = -4mA
from high level to tristate pull-down load to GND
380
450
ns
50
250
ns
td DO
DO delay time
VDO < 0.3 VCC, VDO > 0.7VCC,
CL = 100pF
1. See Figure 5 and Figure 6.
Doc ID 14173 Rev 8
15/36
Electrical specifications
Table 17.
L9951 / L9951XP
EN, CSN timing(1)
Symbol
Parameter
Test condition
Minimum EN high before
tEN_CSN_LO sending first SPI frame, i.e.
CSN going low
tCSN_HI,min
Minimum CSN HI time
between two SPI frames
Min.
Typ.
Max.
Unit
Transfer of SPI-command
to input register
20
50
µs
Transfer of SPI-command
to input register
2
4
µs
1. See Figure 7
Figure 3.
SPI - transfer timing diagram
CSN high to low: DO enabled
CSN
time
CLK
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
0
1
time
DI: data will be accepted on the rising edge of CLK signal
actual data
DI
0
1
2
3
4
5
6
7
8
9
new data
10 11 12
13 14 15
0
1
time
DO: data will change on the falling edge of CLK signal
status information
DO
0
1
2
3
4
fault bit
5
6
7
8
9
10 11 12
13 14 15
0
1
time
CSN low to high: actual data is
transfered to output power switches
e.g.OUT1
old data
actual data
time
Figure 4.
SPI - input timing
0.8 VCC
CSN
0.2 VCC
t set CSN
t CLKH
t set CLK
0.8 VCC
CLK
0.2 VCC
t set DI
t hold DI
t CLKL
0.8 VCC
DI
16/36
Valid
Valid
0.2 VCC
Doc ID 14173 Rev 8
L9951 / L9951XP
Electrical specifications
Figure 5.
SPI - DO valid data delay time and valid time
t f in
t r in
0.8 VCC
0.5 VCC
0.2 VCC
CLK
t r DO
DO
(low to high)
0.8 VCC
0.2 VCC
t d DO
t f DO
0.8 VCC
DO
(high to low)
Figure 6.
0.2 VCC
SPI - DO enable and disable time
tf in
tr in
0.8 VCC
50%
0.2 VCC
CSN
DO
pull-up load to VCC
CL = 100 pF
50%
ten DO tri L
t dis DO L tri
50%
DO
pull-down load to GND
CL = 100 pF
ten DO tri H
Doc ID 14173 Rev 8
t dis DO H tri
17/36
Electrical specifications
Figure 7.
L9951 / L9951XP
SPI - driver turn-on/off timing, minimum CSN HI time
CSN low to high: data from shift register
is transferred to output power switches
t r in
t f in
tCSN_HI,min
80%
50%
20%
CSN
tdOFF
output current
of a driver
ON state
OFF state
80%
50%
20%
t OFF
tdON
t ON
output current
of a driver
Figure 8.
OFF state
ON state
80%
50%
20%
SPI - timing of status bit 0 (fault condition)
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
CSN
time
CLK
time
DI
time
DI: data is not accepted
DO
0time
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
18/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Application information
3
Application information
3.1
Dual power supply: VS and VCC
The power supply voltage VS supplies the half bridges and the high side drivers. An internal
charge-pump is used to drive the high side switches. The logic supply voltage VCC
(stabilized 5V) is used for the logic part and the SPI of the device. Due to the independent
logic supply voltage the control and status information will not be lost, if there are temporary
spikes or glitches on the power supply voltage. In case of power-on (VCC increases from
under voltage to VPOR OFF = 4.0V, typical) the circuit is initialized by an internally generated
power-on-reset (POR).
If the voltage VCC decreases under the minimum threshold (VPOR ON =3.6V, typical), the
outputs are switched to tristate (high impedance) and the status registers are cleared.
3.2
Standby - mode
The standby mode of the L9951 is activated by switching the EN input do GND. All latched
data will be cleared and the inputs and outputs are switched to high impedance. In the
standby mode the current at VS (VCC) is less than 3 µA (1µA) for CSN = high (DO in tristate).
If EN is switched to 5V the device will enter the active mode. In the active mode the chargepump and the supervisor functions are activated.
3.3
Inductive loads
Each half bridge is built by an internally connected high side and a low side power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high side
drivers OUT4 to OUT5 are intended to drive resistive loads. Hence only a limited energy
(E<0.5mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For
inductive loads (L > 50µH) an external free-wheeling diode connected to GND and the
corresponding output is needed.
3.4
Diagnostic functions
All diagnostic functions (over/open-load, power supply over-/undervoltage, temperature
warning and thermal shutdown) are internally filtered and the condition has to be valid for at
least 32µs (open-load: 1ms, respectively) before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Openload and temperature warning function are intended for information purpose and will not
change the state of the output drivers. On contrary, the over load and thermal shutdown
condition will disable the corresponding driver (over load) or all drivers (thermal shutdown),
respectively. Without setting the over-current recovery bit in the Input Data Register to logic
high, the microcontroller has to clear the over-current status bit to reactivate the
corresponding driver. Each driver has a corresponding over-current recovery bit. If this bit is
set, the device will automatically switch-on the outputs again after a short recovery time. The
duty cycle in over-current condition can be programmed by the SPI interface (12% or 25%).
With this feature the device can drive loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, cold resistance of motors and heaters).
Doc ID 14173 Rev 8
19/36
Application information
3.5
L9951 / L9951XP
Over-voltage and under-voltage detection
If the power supply voltage VS rises above the over-voltage threshold VSOV OFF (typical
21V), the outputs OUT1 to OUT5 are switched to high impedance state to protect the load
and the internal charge-pump is turned-off. When the voltage VS drops below the
undervoltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages are switched
to the high impedance to avoid the operation of the power devices without sufficient gate
driving voltage (increased power dissipation). If the supply voltage VS recovers to normal
operating voltage the output stages return to the programmed state (input register 0: bit
12=0). If the undervoltage / overvoltage recovery disable bit is set, the automatic turn-on of
the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the
drivers.
3.6
Temperature warning and thermal shutdown
If junction temperature rises above Tj TW a temperature warning flag is set and is detectable
via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal
shutdown bit will be set and power DMOS transistors of all output stages are switched off to
protect the device. In order to reactivate the output stages the junction temperature must
decrease below TjSD - TjSD HYS and the thermal shutdown bit has to be cleared by the
microcontroller.
3.7
Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load
current is below the open-load detection threshold for at least 1 ms (tdOL) the corresponding
open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without
changing the mechanical/electrical state of the loads.
3.8
Over load detection
In case of an over-current condition a flag is set in the status register in the same way as
open-load detection. If the over-current signal is valid for at least tISC=32µs, the over-current
flag is set and the corresponding driver is switched off to reduce the power dissipation and
to protect the integrated circuit. If the over-current recovery bit of the output is zero the
microcontroller has to clear the status bits to reactivate the corresponding driver.
3.9
Current monitor
The current monitor output sources a current image at the current monitor output which has
a fixed ratio (1/10000) of the instantaneous current of the selected high side driver. The bits
9, 10 and 11 of the input data register 0 control which of the outputs OUT1 to OUT5 will be
multiplexed to the current monitor output. The current monitor output allows a more precise
analysis of the actual state of the load rather than the detection of an open- or overload
condition. For example this can be used to detect the motor state (starting, free-running,
stalled). Moreover, it is possible to regulate the power of the defroster more precise by
measuring the monitor current.
20/36
Doc ID 14173 Rev 8
L9951 / L9951XP
3.10
Application information
PWM input
Each driver has a corresponding PWM enable bit which can be programmed by the SPI
interface. If the PWM enable bit is set, the outputs OUT1 to OUT5 are controlled by the
logically AND-combination of the signal applied to the PWM input and the output control bit
in input data register1.
3.11
Cross-current protection
The three half-brides of the device are cross-current protected by an internal delay time. If
one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge
will be automatically delayed by the cross-current protection time. After the cross-current
protection time is expired the slew-rate limited switch-off phase of the driver will be changed
to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to
this behavior it is always guaranteed that the previously activated driver is totally turned-off
before the opposite driver will start to conduct.
3.12
Programmable softstart function to drive loads with higher
inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable softstart function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to be about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition.
The device itself cannot distinguish between a real overload and a non linear load like a light
bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first
50ms. After clearing the recovery bit the output will be automatically disabled if the overload
condition still exits.
Figure 9.
Example of programmable softstart function for inductive loads
Doc ID 14173 Rev 8
21/36
Functional description of the SPI
L9951 / L9951XP
4
Functional description of the SPI
4.1
Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the
status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers
0 and 1. The microcontroller can poll the status of the device without the need of a full SPIcommunication cycle.
Note:
In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see
Figure 3).
4.2
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started.
The state when CSN is going low until the rising edge of CSN will be called a
communication frame. If the CSN-input pin is driven above 7.5V, the L9951 will go into a test
mode. In the test mode the DO will go from tristate to active mode.
4.3
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 16 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register.
The writing to the selected Data Input Register is only enabled if exactly 16 bits are
transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are
counted within one frame the complete frame will be ignored. This safety function is
implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
22/36
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
Doc ID 14173 Rev 8
L9951 / L9951XP
4.4
Functional description of the SPI
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.5
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
4.6
Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of
the two input registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected input data
register only if a frame of exact 16 data bits are detected. Depending on bit 0 the contents of
the selected status register will be transferred to DO during the current communication
frame. Bit 1-8 control the behavior of the corresponding driver. The bits 9,10 and 11 are
used to control the current monitor multiplexer. Bit 15 is used to reset all status bits in both
status registers. The bits in the status registers will be cleared after the current
communication frame (rising edge of CSN).
4.7
Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is
used as a fault bit and is a logical-NOR combination of bits 1-14 in both status registers. The
state of this bit can be polled by the microcontroller without the need of a full SPIcommunication cycle (see Figure 8.). If one of the over-current bits is set, the corresponding
driver will be disabled. If the over-current recovery bit of the output is not set the
microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown
bit is set, all drivers will go into a high impedance state. Again the microcontroller has to
clear the bit to enable the drivers.
4.8
Test mode
The test mode can be entered by rising the CSN input to a voltage higher than 7.5V. In the
test mode the inputs CLK, DI, PWM and the internal 2MHz CLK can be multiplexed to data
output DO for testing purpose. Furthermore the over-current thresholds are reduced by a
factor of 4 to allow EWS testing at lower current. The internal logic prevents that the Hi-Side
and Low-Side driver of the same half-bridge can be switched-on at the same time. In the test
mode this combination is used to multiplex the desired signals to the CM output according to
table 18 and 19.
Doc ID 14173 Rev 8
23/36
Functional description of the SPI
Table 18.
L9951 / L9951XP
Test mode
LS1 HS1
LS2 HS2
LS3 HS3
DO
LS1 HS1
LS2 HS2
LS3 HS3
CM
! (both HI)
! (both HI)
! (both HI)
NoError
! (both HI)
! (both HI)
! (both HI)
N.C
both HI
! (both HI)
! (both HI)
DI
both HI
! (both HI)
! (both HI)
Tsense1
! (both HI)
both HI
! (both HI)
CLK
! (both HI)
both HI
! (both HI)
Tsense2
both HI
both HI
! (both HI)
INT_CLK
both HI
both HI
! (both HI)
Tsense3
! (both HI)
! (both HI)
both HI
PWM
! (both HI)
! (both HI)
both HI
Tsense4
both HI
! (both HI)
both HI
N.C
! (both HI)
both HI
both HI
5µA Iref
both HI
both HI
both HI
Vbandgap
Table 19.
SPI - Input data and status register 0
Input register 0 (write)
Bit
Name
Comment
15
Reset bit
If reset bit is set both status
registers will be cleared after
rising edge of CSN input.
14
Disable openload
If the disable open-load bit is
set, the open-load status
bits will be ignored for the
NonErrorBit calculation.
13
This bit defines in
combination with the overcurrent recovery bit (input
register 1) the duty cycle in
over-current condition of an
activated driver. If
temperature warning bit is
0: 12% 1: 25% set, L9951 will always use
the lower duty cycle
12
Overvoltage/
under-voltage
recovery
disable
OC recovery
duty cycle
24/36
If this bit is set the
microcontroller has to clear
the status register after
undervoltage/overvoltage
event to enable the outputs.
Doc ID 14173 Rev 8
Status register 0 (read)
Name
Comment
Always 1
A broken VCC-or SPIconnection of the L9951 can
be detected by the
microcontroller, because all 16
bits low or high is not a valid
frame.
In case of an over-voltage or
VS
undervoltage event the
over-voltage corresponding bit is set and
the outputs are deactivated.
If VS voltage recovers to
normal operating conditions
VS
undervoltage outputs are reactivated
automatically.
Thermal
shutdown
In case of an thermal
shutdown all outputs are
switched off. The
microcontroller has to clear the
TSD bit by setting the reset bit
to reactivate the outputs.
L9951 / L9951XP
Functional description of the SPI
Table 19.
SPI - Input data and status register 0 (continued)
Input register 0 (write)
Bit
Name
Status register 0 (read)
Comment
Name
Following current image
(1/10.000) of the HS driver
will be multiplexed to CM
output:
11
Current monitor
select bits
10
Bit 11 Bit 10 Bit 9
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Output
OUT1
OUT2
OUT3
OUT4
OUT5
9
OUT5 - HS
on/off
7
OUT4 - HS
on/off
6
OUT3 - HS
on/off
5
OUT3 - LS
on/off
4
OUT2 - HS
on/off
3
OUT2 - LS
on/off
2
OUT1 - HS
on/off
1
OUT1 - LS
on/off
0
This bit is for information
purpose only. It can be used
Temperature
for a thermal management by
warning
the microcontroller to avoid a
thermal shutdown.
After switching the device from
standby mode to active mode
an internal timer is started to
allow charge pump to settle
before the outputs can be
activated. This bit is cleared
Not ready bit
automatically after start up
time has finished. Since this bit
is controlled by internal clock it
can be used for synchronizing
testing events (e.g. measuring
filter times).
0
8
Comment
Not used
OUT5-HS
over - current
If a bit is set the selected
output driver is switched on.
If the corresponding PWM
enable bit is set (Input
Register 1) the driver is only
activated if PWM input
signal is high. The outputs of
OUT1-OUT3 are half
bridges. If the bits of HSand LS-driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal current
from VS to GND.
OUT4-HS In case of an over-current
over - current event the corresponding status
bit is set and the output driver
OUT3-HS is disabled. If the over-current
over - current recovery enable bit is set
(Input Register 1) the output
OUT3-LS
will be automatically
over - current reactivated after a delay time
OUT2-HS resulting in a PWM modulated
current with a programmable
over - current
duty cycle (Bit 13).
OUT2-LS
If the over-current recovery bit
over - current is not set the microcontroller
has to clear the over-current bit
OUT1-HS (reset bit) to reactivate the
over - current output driver.
OUT1-LS
over - current
0
No error bit
Doc ID 14173 Rev 8
A logical NOR-combination of
all bits 1 to 14 in both status
registers. If bit 14 (disable
open-load) is set, the openload status will be ignored.
25/36
Functional description of the SPI
Table 20.
L9951 / L9951XP
SPI - Input data and status register 1
Input register 1 (write)
Bit
15
14
13
12
11
26/36
Name
Status register 1 (read)
Comment
Name
Not used
Always 1
Comment
A broken VCC-or SPIconnection of the L9951 can
be detected by the
microcontroller, because all
16 bits low or high is not a
valid frame.
Not used
In case of an over-voltage or
undervoltage event the
VS over-voltage
corresponding bit is set and
the outputs are deactivated.
Not used
In case of an over-voltage or
undervoltage event the
VS undervoltage
corresponding bit is set and
the outputs are deactivated.
Thermal
shutdown
Not used
Temperature
warning
Not used
Doc ID 14173 Rev 8
In case of an thermal
shutdown all outputs are
switched off. The
microcontroller has to clear
the TSD bit by setting the
reset bit to reactivate the
outputs.
This bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.
L9951 / L9951XP
Functional description of the SPI
Table 20.
SPI - Input data and status register 1 (continued)
Input register 1 (write)
Bit
10
9
8
7
6
Name
In case of an over-current
event the over-current
status bit (status register
0) is set and the output is
switched off. If the overcurrent recovery enable bit
OUT5 OC
is set the output will be
recovery enable
automatically reactivated
after a delay time resulting
in a PWM modulated
current with a
programmable duty cycle
(Bit 13 of Input data
register 1).
OUT4 OC
recovery enable
OUT3 OC
Depending on occurrence
recovery enable of overcurrent event and
internal clock phase it is
OUT2 OC
recovery enable possible that one recovery
cycle is executed even if
this bit is set to zero.
OUT1 OC
recovery enable
5
OUT5 PWM
enable
4
OUT4 PWM
enable
3
OUT3 PWM
enable
2
OUT2 PWM
enable
1
OUT1 PWM
enable
0
Comment
Status register 1 (read)
Name
Comment
Not ready bit
After switching the device
from standby mode to active
mode an internal timer is
started to allow charge pump
to settle before the outputs
can be activated. This bit is
cleared automatically after
start up time has finished.
Since this bit is controlled by
internal clock it can be used
for synchronizing testing
events(e.g. measuring filter
times).
0
OUT5-HS
open-load
OUT4-HS
open-load
OUT3-HS
open-load
OUT3-LS
open-load
If the PWM enable bit is
set and the output is
enabled (input register 0)
the output is switched on if
PWM input is high and
switched off if PWM input
is low.
Not used.
OUT2-HS
open-load
OUT2-LS
open-load
OUT1-HS
open-load
The open-load detection
monitors the load current in
each activated output stage. If
the load current is below the
open-load detection threshold
for at least 1 ms (tdOL) the
corresponding open-load bit
is set. Due to mechanical
/electrical inertia of typical
loads a short activation of the
outputs (e.g. 3ms) can be
used to test the open-load
status without changing the
mechanical/electrical state of
the loads.
OUT1-LS
open-load
1
No error bit
Doc ID 14173 Rev 8
A logical NOR-combination of
all bits 1 to 14 in both status
registers. If bit 14 (Disable
Open-Load) is set, the openload status will be ignored
27/36
Packages thermal data
5
L9951 / L9951XP
Packages thermal data
Figure 10. Packages thermal data
28/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Package and packing information
6
Package and packing information
6.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.2
PowerSO-36™ package information
Figure 11.
PowerSO-36™ package dimensions
Table 21.
PowerSO-36™ mechanical data
Millimeters
Symbol
Min.
A
a1
Typ.
Max.
3.60
0.10
a2
0.30
3.30
a3
0
0.10
b
0.22
0.38
c
0.23
0.32
Doc ID 14173 Rev 8
29/36
Package and packing information
Table 21.
L9951 / L9951XP
PowerSO-36™ mechanical data (continued)
Millimeters
Symbol
Min.
Typ.
Max.
D*
15.80
16.00
D1
9.40
9.80
E
13.90
14.5
E1 *
10.90
11.10
E2
E3
2.90
5.80
6.20
e
0.65
e3
11.05
G
0
0.10
H
15.50
15.90
h
L
1.10
0.8
1.10
M
N
10 deg
R
s
30/36
8 deg
Doc ID 14173 Rev 8
L9951 / L9951XP
6.3
Package and packing information
PowerSSO-36™ package information
Figure 12. PowerSSO-36™ package dimensions
Table 22.
PowerSSO-36™ mechanical data
Symbol
Millimeters
Min.
Typ.
Max.
A
-
-
2.45
A2
2.15
-
2.35
a1
0
-
0.1
b
0.18
-
0.36
c
0.23
-
0.32
D*
10.10
-
10.50
E*
7.4
-
7.6
e
-
0.5
-
e3
-
8.5
-
F
2.3
G
-
-
0.1
G1
-
-
0.06
H
10.1
-
10.5
h
-
-
0.4
k
0°
L
0.55
-
0.85
N
-
-
10 deg
Doc ID 14173 Rev 8
8°
31/36
Package and packing information
Table 22.
PowerSSO-36™ mechanical data (continued)
Symbol
6.4
L9951 / L9951XP
Millimeters
Min.
Typ.
Max.
X
4.3
-
5.2
Y
6.9
-
7.5
PowerSO-36™ packing information
Figure 13. PowerSO-36TM tube shipment (no suffix)
32/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Package and packing information
Figure 14. PowerSO-36TM tape and reel shipment (suffix “TR”)
TAPE DIMENSIONS
A0
B0
K0
K1
F
P1
W
15.20 ± 0.1
16.60 ± 0.1
3.90 ± 0.1
3.50 ± 0.1
11.50 ± 0.1
24.00 ± 0.1
24.00 ± 0.3
All dimensions are in mm.
Doc ID 14173 Rev 8
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
D (min)
G (+2 / -0)
N (min)
T (max)
600
600
330
1.5
13
20.2
24.4
60
30.4
33/36
Package and packing information
6.5
L9951 / L9951XP
PowerSSO-36™ packing information
Figure 15. PowerSSO-36TM tube shipment (no suffix)
C
Base Qty
Bulk Qty
Tube length (±0.5)
A
B
C (±0.1)
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 16. PowerSSO-36TM tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (±0.1)
P
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
34/36
Doc ID 14173 Rev 8
No components
L9951 / L9951XP
7
Revision history
Revision history
Table 23.
Document revision history
Date
Revision
Mar-2004
1
First issue
Jun-2005
2
Added PowerSO-36™ package information, PowerSO-36™ package
information.
Jul-2005
3
Updated Figure 1.: Block diagram .
Sep-2005
4
Note 1 removal;
Updated Figure 10.: Packages thermal data.
Feb-2006
5
Updated Table 4.: ESD protection.
15-Nov-2007
6
Document restructured and reformatted.
Added PowerSO-36™ packing information and PowerSSO-36™
packing information.
7
Table 22: PowerSSO-36™ mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F and k rows
8
Table 22: PowerSSO-36™ mechanical data:
– Changed X: minimum value from 4.1 to 4.3 and
maximum value from 4.7 to 5.2
– Changed Y: minimum value from 6.5 to 6.9 and
maximum value from 7.1 to 7.5
24-Jun-2009
14-May-2010
Description of changes
Doc ID 14173 Rev 8
35/36
L9951 / L9951XP
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Doc ID 14173 Rev 8