PM6681A Dual step-down controller with adjustable LDO Target Specification Features ■ 6V to 36V input voltage range ■ Adjustable output voltages ■ 0.9-3.3V LDO adjustable delivers 100mA peak current ■ 5V LDO delivers 100mA peak current ■ 1.237V ±1% reference voltage available ■ NO RSENSE current sensing using low side MOSFETs' RDS(on) ■ Negative current limit ■ Soft start internally fixed at 2ms ■ Soft output discharge ■ Latched UVP ■ Not-latched OVP ■ Selectable pulse skipping at light loads ■ Selectable minimum frequency(33kHz) in pulse skip mode ■ 5mW maximum quiescent power ■ Indipendent power good signals ■ Output voltage ripple compensation Applications ■ Embedded computer system ■ FPGA system power ■ Industrial applications on 24V ■ High performance and high density DC/DC modules VFQFPN-32 (5mm x 5mm) Description PM6681A is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 33kHz is selectable to avoid audio noise issues. The PM6681A provides a selectable switching frequency, allowing three different values of switching frequencies for the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0.9V to 5V and from 0.9V to 3.3V respectively. The device provides also 2 LDOs, 5V fixed and 0.9V-3.3V adjustable. Order codes Part number Package Packaging PM6681A VFQFPN-32 (5mm x 5mm) Tube PM6681ATR VFQFPN-32 (5mm x 5mm) Tape and Reel November 2006 Rev 1 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. 1/12 www.st.com 12 Contents PM6681A Contents 1 Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 OUT1- 1 OUT1+ 1 SGND FB1 VIN + PGND SGND PGOOD2 PGOOD1 V+ V+ PGND LDO FB SGND 5 27 26 16 30 29 17 20 15 21 22 23 SGND SHDN PGOOD2 PGOOD1 LDO FB COMP1 OUT1 V5SW LGATE2 PHASE2 HGATE2 BOOT2 U1 SGND LDO FB1 FB2 COMP2 OUT2 SGND PGND CSENSE2 PM6681A PM6681 CSENSE1 LGATE1 PHASE1 HGATE1 BOOT1 SGND EN1 BOOT2 18 LDO5 VREF V+ VCC V+ VIN + 19 SKIP BOOT1 FSEL 31 EN2 4 7 SGND PGND SGND LDO FB 28 FB1 6 2 8 1 14 12 13 11 10 SGND 9 SGND PGND PGND + VIN SGND 1 1 OUT2- OUT2+ Simplified application schematic 25 Figure 1. 32 Simplified application schematic 24 1 3 PM6681A Simplified application schematic 3/12 Pin settings PM6681A 2 Pin settings 2.1 Connections Figure 2. Pin connection (top view) 27 26 EN1 28 PG O O D 29 PG O O D2 30 FB1 31 O UT CO M P1 VCC VR EF 32 25 1 24 SK IP SG N D 2 23 C O M P2 FSEL B O OT 1 3 22 H G AT E1 4 21 EN 2 PH ASE1 PM 6681A 5 20 SH D N FB2 C SEN S E1 6 19 VIN 7 18 8 17 LDO O U T2 LD O 5 V5SW 9 11 12 13 14 15 16 LDO FB LG ATE1 PG ND LG ATE2 CSEN S E2 PHASE2 HG ATE2 BO O T2 4/12 10 PM6681A 2.2 Pin settings Functions Table 1. N° Pin functions Pin Function 1 SGND1 Signal ground. Reference for internal logic circuitry. It must be connected to the signal ground plan of the power supply. The signal ground plan and the power ground plan must be connected together in one point near the PGND pin. 2 COMP2 DC voltage error compensation pin for the switching section 2 3 FSEL Frequency selection pin. It provides a selectable switching frequency, allowing three different values of switching frequencies for the switching sections. EN2 Enable input for the switching section 2. – The section 2 is enabled applying a voltage greater than 2.4V to this pin. – The section 2 is disabled applying a voltage lower than 0.8V. When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin is high the device enters in standby mode. 5 SHDN Shutdown control input. – The device switch off if the SHDN voltage is lower than the device off thershold (Shutdown mode) – The device switch on if the SHDN voltage is greater than the device on threshold. The SHDN pin can be connected to the battery through a voltage divider to program an undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in high impedance (high-Z). 6 FB2 Feedback input for the switching section 2 This pin is connected to a resistive voltage-divider from OUT2 to PGND to adjust the output voltage from 0.9V to 3.3V. 7 LDO Adjustable internal regulator output. It can be set from 0.9V to 3.3V. LDO pin can provide a 100mA peak current. 8 OUT2 Output voltage sense for the switching section 2.This pin must be directly connected to the output votage of the switching section. 9 BOOT2 Bootstrap capacitor connection for the switching section 2. It supplies the high-side gate driver. 10 HGATE2 High-side gate driver ouput for section 2. This is the floating gate driver output. 11 PHASE2 Switch node connection and return path for the high side driver for the section 2. It is also used as negative current sense input. 12 CSENSE2 13 LGATE2 14 PGND 15 LGATE1 4 Positive current sense input for the switching section 2. This pin must be connected through a resistor to the drain of the synchronous rectifier to obtain a positive current limit threshold for the power supply controller. Low-side gate driver output for the section 2. Power ground. This pin must be connected to the power ground plan of the power supply. Low-side gate driver output for the section 1. 5/12 Pin settings PM6681A Table 1. N° Pin 16 LDO FB Function Feedback input for the adjustable internal linear regulator. This pin is connected to a resistive voltage-divider from LDO to SGND to adjust the output voltage from 0.9V to 3.3V. 17 V5SW Internal 5V regulator bypass connection. – If V5SW is connected to OUT5 (or to an external 5V supply) and V5SW is greater than 4.9V, the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through a 3W (max) switch. If V5SW is connected to GND, the LDO5 linear regulator is always on. 18 LDO5 5V internal regulator output. It can provide up to 100mA peak current. LDO5 pin supplies embedded low side gate drivers and an external load. 19 VIN Device supply voltage input and battery voltage sense. A bypass filter (4Ω and 4.7mF) between the battery and this pin is recommended. 20 CSENSE1 21 PHASE1 Switch node connection and return path for the high side driver for the section 1.It is also used as negative current sense input. 22 HGATE1 High-side gate driver ouput for section 1. This is the floating gate driver output. 23 BOOT1 Bootstrap capacitor connection for the switching section 1. It supplies the high-side gate driver. SKIP Pulse skipping mode control input. – If the pin is connected to LDO5 the PWM mode is enabled. – If the pin is connected to GND, the pulse skip mode is enabled. – If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is kept higher than 33KHz (No-audible puse skip mode). 25 EN1 Enable input for the switching section 1. – The section 1 is enabled applying a voltage greater than 2.4V to this pin. – The section 1 is disabled applying a voltage lower than 0.8V. When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. 26 PGOOD1 Power Good ouput signal for the section 1. This pin is an open drain ouput and when the ouput of the switching section 1 is out of +/- 10% of its nominal value.It is pulled down. 27 PGOOD2 Power Good ouput signal for the section 2. This pin is an open drain ouput and when the ouput of the switching section 2 is out of +/- 10% of its nominal value.It is pulled down. 28 FB1 Feedback input for the switching section 1. This pin is connected to a resistive voltage-divider from OUT1 to PGND to adjust the output voltage from 0.9V to 5.5V. 29 OUT1 Output voltage sense for the switching section 1.This pin must be directly connected to the output votage of the switching section. 24 6/12 Pin functions (continued) Positive current sense input for the switching section 1. This pin must be connected through a resistor to the drain of the synchronous rectifier to obtain a positive current limit threshold for the power supply controller. PM6681A Pin settings Table 1. Pin functions (continued) N° Pin Function 30 COMP1 31 VCC Device Supply Voltage pin. It supplies all the internal analog circuitry except the gate drivers (see LDO5). Connect this pin to LDO5. 32 VREF Internal 1.237V high accuracy voltage reference. It can deliver 50uA. Bypass to SGND with a 100nF capacitor to reduce noise. DC voltage error compensation pin for the switching section 1. 7/12 Functional block diagram 3 Functional block diagram Figure 3. 8/12 Functional block diagram PM6681A PM6681A 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 2. VFQFPN 5x5x1.0 32L Pitch 0.50 Databook (mm) Dim. Min Typ Max A 0.8 0.9 1 A1 0 0.02 0.05 A3 0.2 b 0.18 0.25 D 4.85 5 D2 0.3 5.15 See exposed pad variations E 4.85 E2 (2) 5 5.15 See exposed pad variations e (2) 0.5 L 0.3 0.4 0.5 ddd Table 3. 0.05 Exposed pad variations (1)(2)D2 E2 Min Typ Max Min Typ Max 2.90 3.10 3.20 2.90 3.10 3.20 1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. Very thin: A = 1.00mm Max. 2. Dimensions D2 & E2 are not in accordance with JEDEC. 9/12 Package mechanical data Figure 4. 10/12 Package dimensions PM6681A PM6681A 5 Revision history Revision history Table 4. Revision history Date Revision 02-Nov-2006 1 Changes Initial release 11/12 PM6681A Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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