STEVAL-IFP007V1 16-bit PLC digital input card demonstration board based on the SCLT3 Data brief Features ■ 8/16 input channel topology (SCLT3-8 chip/STEVAL-IFP007V1 board) ■ Fully integrated current limiter ■ Termination for IEC61131-2 type 1 and 3 inputs ■ Digital filter in each input ■ SPI communication peripheral ■ Voltage regulator integrated on the chip ■ Thermal alarm ■ Wide range supply voltage operation Description STEVAL-IFP007V1 The STEVAL-IFP07V1 demonstration board is based on the SCLT3-8 protected digital input termination with serialized state transfer, and allows the user to evaluate the behavior of the SCLT3-8 device in industrial environmental conditions. interface and indicates each sensor logic state with an LED. The SCLT3-8 is an eight channel termination used to interface automation digital inputs. It is designed for 24 VDC applications, and supports the type 3 input characteristic in accordance with standard IEC61131-2 (programmable controllers). The device integrates an SPI peripheral for communication with logic devices, ASICs and microcontrollers. This demonstration board is capable of transferring not only the data but also additional information such as thermal alarms, under voltage indications and parity bits. The STEVALIFP07V1 is ideal for applications with a high channel count, while the serial communication reduces the number of lines which, in most final applications, require galvanic isolation. The board accommodates two SCLT3-8 chips connected to the SPI bus in a "daisy-chain" configuration. It offers a 16-bit digital input May 2009 Doc ID 15371 Rev 2 For further information contact your local STMicroelectronics sales office. 1/4 www.st.com 4 0 1 2 3 8 9 10 11 12 13 14 15 Input nput nput Input nput Input Input nput Input nput Input nput Input nput Input nput nput 4 Input nput 5 Input Input nput 6 nput 7 Input Input nput Input nput nput Input Input nput 3 1 3 3 3 1 Doc ID 15371 Rev 2 1 2 ST04 2pin CN CN9 ST70 2x2 4 2 ST70 2x2 CN4 CN 4 2 1 ST70 2x2 CN3 CN 4 2 1 ST70 2x2 CN2 CN 4 2 R1 R17 R18 R1 R20 R2 R21 R2 R1 R13 R14 R1 R15 R1 R16 R1 R8 R10 R1 R11 R1 R12 R1 R1 R3 R4 R5 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 2k2 C4 C44 C45 C4 C46 C4 C47 C4 C4 C40 C41 C4 C42 C4 C43 C4 GND GN 1n 1nF 1n 1nF 1n 1nF 1n 1nF 1n 1nF 1n 1nF 1nF 1n 1nF 1n 1nF 1n 1nF 1n 1n 1nF 1nF 1n 1n 1nF 1n 1nF 1nF 1n 1n 1nF Test poin point 1 GND_ GND_P WR VCC 1k0 R6 1k0 R22 R2 VCS VC R4 R44 120k SGND SGN VCC 1M5 R43 R4 GND GN SGND SGN VCC GND GN IN1 N12 C5 C52 IN1 N13 C5 C53 IN1 N14 C5 C54 IN1 N15 C5 C55 C48 IN8 C4 C49 IN9 C4 N10 C5 C50 IN1 N11 C5 C51 IN1 IN4 IN5 IN6 IN7 IN0 IN1 IN2 IN3 SGND SGN C6 33nF 33n SGND SGN SGND SGN C4 33nF 33n SGND SGN 51k R19 R1 51k R2 GND GN IN1 N12 IN1 N13 N14 IN1 N15 IN1 IN8 IN9 IN1 N10 IN1 N11 GND GN VC_U2 VC_U VCS VC SPM DVR DV IN4 IN5 IN6 IN7 IN0 IN1 IN2 IN3 VC_U VC_U1 VCS VC SPM DVR DV DVR DV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SGND SGN JMP 1 JM VDD4 VDD DV DVR OSC OS SPM COMp COM VC VCS VC COMp COM IN1 IN2 IN3 IN4 COMp COM IN5 IN6 IN7 IN8 COMp COM NC NC U2 DV DVR OSC OS SPM COMp COM VC VCS VC COMp COM IN1 IN2 IN3 IN4 COMp COM IN5 IN6 IN7 IN8 COMp COM NC NC U1 C OM p 2/4 39 SPM SGND SGN JMP 2 JM VDD4 VDD SC SCL T3- 8BT 8BT8 VD VDD NC NC CS SCK SC MOSI MOS MI SO MI SO COMs REF RE NC L D1 L D2 L D3 L D4 L D5 L D6 L D7 L D8 SCL T3- 8BT 8BT8 SC VD VDD NC NC CS SCK SC MOSI MOS MI SO MI SO COMs REF RE NC L D1 L D2 L D3 L D4 L D5 L D6 L D7 L D8 L SB 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 SGND SGN C1 C18 33nF 33n R51 22 R5 22R L ED ED7 L ED ED5 L ED ED3 L ED ED1 R7 L ED14 L ED12 L ED10 L ED8 ED L ED15 L ED13 L ED11 L ED ED9 R24 R2 MI SO_SCL SO_SC T nCS_SCL T2 nCS_SC SCK _SCL _S T2 SC SD_0f VDD4 VDD L ED6 ED L ED4 ED L ED2 ED L ED0 ED SD_ SD_0 nCS_SCL T1 nCS_SC SC SCK _SCL _S T1 SGND SGN C1 33n 33nF R50 22 R5 22R SGND SGN 15k VDD VD SGND SGN 15k VDD VD C2 C20 100pF 100p R53 220R R5 SD_0f C22 C2 100pF 100p R55 220R R5 SGND SGN C23 C2 100pF 100p R56 220R R5 SGND SGN nCS_SCL T2 nCS_SC SGND SGN C2 C21 100p 100pF R54 220R R5 SCK _S SC _SCL T2 SGND SGN nCS_SCL T1 nCS_SC SGND SGN C1 C19 100pF 100p R52 220R R5 SCK _S SC _SCL T1 SD_0 SD_ nCS_OP T nCS_O SCK _OPT _O SC nCS_O nCS_OP T SCK _OPT _O SC R58 330R R5 R57 330R R5 SGND SGN MI SO_SCL SO_SC T 7 6 Vo1 Vo U5 3 2 NC C U6 1 A Vo2 C2 Vo 100n 100nF 5 GND GN SGND SGN nCS_OP T nCS_O SCK _OPT SC _O VDD VD 8 VDD VD C1 C13 10uF/6.3V 10u /6.3V SGND SGN VDD VD GND GN W70L ACP L -W70 Vo VDD VD 73L ACP L -K 73 solation barrie barrier Isolation Shield Shi Shield Shi A2 C2 C1 A1 R60 330R R6 R49 330R R4 R59 330R R5 R48 330R R4 C2 C25 100nF 100n nCS_uC nCS_u nCS_uC nCS_u Test point poin 1 MI SO Test point poin 1 CS poin Test point 1 SC SCK ML W20G W20 2 4 6 8 10 12 14 16 18 20 Test point poin GND_MI CR CRO MI CR CRO_GN GND 1 MI SO_u SO_uC nCS_uC nCS_u CL K _u _uC MI CRO_VC CRO_VCC MI CRO_GN CR GND CL K _u _uC MI SO_uC SO_u MI CRO_GN CR GND 4 5 MI CRO_VCC CRO_VC 6 4 3 2 1 MI CR CRO_GN GND C1 C14 10uF/6.3V 10u /6.3V MI CRO_VCC CRO_VC 1 3 5 7 9 11 13 15 17 19 CN10 CN1 MI CRO_GN CR GND CL K _uC _u MI SO_u SO_uC SPI_MASTER _MASTER to be connected Figure 1. C OM p 1 39 CN1 CN SPI_S _SL AVE AV Circuit schematic STEVAL-IFP007V1 Circuit schematic Schematic diagram STEVAL-IFP007V1 2 Revision history Revision history Table 1. Document revision history Date Revision Changes 17-Feb-2009 1 Initial release. 05-May-2009 2 Updated picture on cover page and schematic diagram (Figure 1) Doc ID 15371 Rev 2 3/4 STEVAL-IFP007V1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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