MICROCHIP SST25VF020B_13

2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
The 25 series Serial Flash family features a four-wire, SPI compatible interface
that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF020B devices are enhanced with
improved operating frequency and even lower power consumption.
SST25VF020B SPI serial flash memories are manufactured with SST proprietary,
high performance CMOS SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.
Features
• Single Voltage Read and Write Operations
• End-of-Write Detection
– 2.7-3.6V
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin in AAI Mode
• Serial Interface Architecture
• Hold Pin (HOLD#)
– SPI Compatible: Mode 0 and Mode 3
– Suspends a serial sequence to the memory
without deselecting the device
• High Speed Clock Frequency
– Up to 80 MHz
• Write Protection (WP#)
• Superior Reliability
– Enables/Disables the Lock-Down function of the status
register
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Software Write Protection
• Low Power Consumption:
– Write protection through Block-Protection bits in status
register
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Temperature Range
• Flexible Erase Capability
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Packages Available
– 8-lead SOIC (150 mils)
– 8-contact WSON (6mm x 5mm)
– 8-contact USON (3mm x 2mm)
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• All non-Pb (lead-free) devices are RoHS compliant
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Program operations
©2013 Silicon Storage Technology, Inc.
www.microchip.com
DS20005054C
04/13
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Product Description
The 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low
pin-count package which occupies less board space and ultimately lowers total system costs. The
SST25VF020B devices are enhanced with improved operating frequency and even lower power consumption. SST25VF020B SPI serial flash memories are manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with alternate approaches.
The SST25VF020B devices significantly improve performance and reliability, while lowering power
consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for
SST25VF020B. The total energy consumed is a function of the applied voltage, current, and time of
application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation
is less than alternative flash memory technologies.
The SST25VF020B device is offered in 8-lead SOIC (150 mils) 8-contact WSON (6mm x 5mm), and 8contact USON (3mm x 2mm) packages. See Figure 2 for pin assignments.
©2013 Silicon Storage Technology, Inc.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Functional Block Diagram
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
CE#
SCK
SI
SO
WP#
HOLD#
1417 B1.0
Figure 1: Functional Block Diagram
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Pin Description
CE#
1
SO
2
8
VDD
7
HOLD#
CE#
1
SO
2
8
VDD
7
HOLD#
Top View
Top View
WP#
3
6
SCK
WP#
3
6
SCK
VSS
4
5
SI
VSS
4
5
SI
8-Contact WSON
8-Lead SOIC
1417 08-wson QA P2.0
1417 08-soic S2A P1.0
CE#
1
SO
2
Top View
8
VDD
7
HOLD#
WP#
3
6
SCK
VSS
4
5
SI
8-Contact USON
1417 08-uson Q3A P1.0
Figure 2: Pin Assignments
Table 1: Pin Description
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/
BY# pin. See “Hardware End-of-Write Detection” on page 14 for details.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting the device.
VDD
Power Supply
To provide power supply voltage: 2.7-3.6V for SST25VF020B
VSS
Ground
T1.0 25054
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Memory Organization
The SST25VF020B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable blocks.
Device Operation
The SST25VF020B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF020B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
SCK
SI
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
1417 SPIprot.0
Figure 3: SPI Protocol
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Hold Operation
The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode
when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or
VIH.
If CE# is driven high during a Hold condition, the device returns to Standby mode. As long as HOLD#
signal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 4 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1417 HoldCond.0
Figure 4: Hold Condition Waveform
Write Protection
SST25VF020B provides software Write protection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register, and the Top/Bottom Sector Protection Status bits (TSP and BSP) in Status Register 1, provide Write protection to the memory array and the status register. See Table 5 for the Block-Protection
description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined
by the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is
disabled.
Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction
WP#
BPL
L
1
Not Allowed
Execute WRSR Instruction
L
0
Allowed
H
X
Allowed
T2.0 25054
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Status Register
The software status register provides status on whether the flash memory array is available for any
Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 3 describes the function of each bit in the
software status register.
Table 3: Software Status Register
Default at
Power-up
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicates current level of block write protection (See Table
5)
1
R/W
3
BP1
Indicates current level of block write protection (See Table
5)
1
R/W
4:5
RES
Reserved for future use
0
N/A
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0
R
7
BPL
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
0
R/W
Bit
Name
Function
0
BUSY
1
T3.0 25054
Software Status Register 1
The Software Status Register 1 is an additional register that contains Top Sector and Bottom Sector
Protection bits. These register bits are read/writable and determine the lock and unlock status of the
top and bottom sectors.
Table 4 describes the function of each bit in the Software Status Register 1.
Table 4: Software Status Register 1
Default at
Power-up
Read/Write
Reserved for future use
0
N/A
TSP
Top Sector Protection status
1 = Indicates highest sector is write locked
0 = Indicates highest sector is Write accessible
0
R/W
3
BSP
Bottom Sector Protection status
1 = Indicates lowest sector is write locked
0 = Indicates lowest sector is Write accessible
0
R/W
4:7
RES
Reserved for future use
0
N/A
Bit
Name
Function
0:1
RES
2
T4.0 25054
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for
the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is
ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the
Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),
it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)
commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
•
•
•
•
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instructions
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI
programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 5, to be
software protected against any memory Write (Program or Erase) operation. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the BlockProtect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After
power-up, BP1 and BP0 are set to 1.
Block Protection Lock-Down (BPL)
WP# pin driven low (VIL), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it
prevents any further alteration of the BPL, BP1, and BP0 bits of the status register and BSP and TSP
of Status Register 1. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is
“Don’t Care”. After power-up, the BPL bit is reset to 0.
Table 5: Software Status Register Block Protection FOR SST25VF020B1
Status Register Bit2
Protected Memory Address
BP1
BP0
0
0
0
None
1 (1/4 Memory Array)
0
1
030000H-03FFFFH
Protection Level
2 Mbit
1 (1/2 Memory Array)
1
0
020000H-03FFFFH
1 (Full Memory Array)
1
1
000000H-03FFFFH
T5.0 25054
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP1 and BP0 is ‘11’. (All Blocks Protected)
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Top-Sector Protection/Bottom-Sector Protection
The Top-Sector Protection (TSP) and Bottom-Sector Protection (BSP) bits independently indicate
whether the highest and lowest sector locations are Write locked or Write accessible. When TSP or
BSP is set to ‘1’, the respective sector is Write locked; when set to ‘0’ the respective sector is Write
accessible. If TSP or BSP is set to '1' and if the top or bottom sector is within the boundary of the target
address range of the program or erase instruction, the initiated instruction (Byte-Program, AAI-Word
Program, Sector-Erase, Block-Erase, and Chip-Erase) will not be executed. Upon power-up, the TSP
and BSP bits are automatically reset to ‘0’.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF020B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, WriteStatus-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in Table 6. All instructions are synchronized off a high
to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 6: Device Operation Instructions
Instruction
Description
Op Code Cycle1
Address
Cycle(s)2
Read
Read Memory
0000 0011b (03H)
3
0
1 to ∞
High-Speed Read
Read Memory at higher speed
0000 1011b (0BH)
3
1
1 to ∞
0010 0000b (20H)
3
0
0
4 KByte Sector-Erase3 Erase 4 KByte of memory array
32 KByte Block-Erase4
Dummy
Data
Cycle(s) Cycle(s)
Erase 32 KByte block of memory array 0101 0010b (52H)
3
0
0
64 KByte Block-Erase5 Erase 64 KByte block of memory array 1101 1000b (D8H)
3
0
0
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
0
0
0
Byte-Program
To Program One Data Byte
0000 0010b (02H)
3
0
1
AAI-Word-Program6 Auto Address Increment Programming 1010 1101b (ADH)
3
0
2 to ∞
RDSR7
Read-Status-Register
0
0
1 to ∞
RDSR1
Read-Status-Register 1
0011 0101b (35H)
0
0
1 to ∞
EWSR
Enable-Write-Status-Register
0101b 0000b (50H)
0
0
0
WRSR
Write-Status-Register
0000 0001b (01H)
0
0
1 or 2
WREN
Write-Enable
0000 0110b (06H)
0
0
0
WRDI
Write-Disable
0000 0100b (04H)
0
0
0
RDID8
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
3
0
1 to ∞
JEDEC-ID
JEDEC ID read
1001 1111b (9FH)
0
0
3 to ∞
EBSY
Enable SO to output RY/BY# status 0111 0000b (70H)
during AAI programming
0
0
0
DBSY
Disable SO as RY/BY#
status during AAI programming
0
0
0
0000 0101b (05H)
1000 0000b (80H)
T6.0 25054
1.
2.
3.
4.
5.
6.
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be VIL or VIH.
4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of
data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be
programmed into the
initial address [A23-A1] with A0=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Read (33 MHz)
The Read instruction, 03H, supports up to 33 MHz Read. The device outputs the data starting from the
specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until
the highest memory address is reached. Once the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-around) of the address space. Once the
data from address location 3FFFFH has been read, the next output will be from address location
000000H.
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23A0]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read
sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
ADD.
ADD.
03
SI
MSB
MSB
SO
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
MODE 0
HIGH IMPEDANCE
ADD.
N
DOUT
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
1417 ReadSeq.0
Figure 5: Read Sequence
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
High-Speed-Read (80 MHz)
The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the
duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a
low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. Once the data from
address location 3FFFH has been read, the next output will be from address location 00000H.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
0B
SI
MSB
SO
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
MODE 0
ADD.
MSB
ADD.
ADD.
X
N
DOUT
HIGH IMPEDANCE
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)
1417 HSRdSeq.0
Figure 6: High-Speed-Read Sequence
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39
MODE 0
02
SI
ADD.
ADD.
MSB
MSB
ADD.
DIN
MSB
LSB
HIGH IMPEDANCE
SO
1417 ByteProg.0
Figure 7: Byte-Program Sequence
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Auto Address Increment (AAI) Word-Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the
next sequential address location. This feature decreases total programming time when multiple bytes
or entire memory array is to be programmed. An AAI Word program instruction pointing to a protected
memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI Word Program operation. While within AAI Word Programming sequence, only the following instructions are valid: for software end-of-write detection—AAI Word (ADH), WRDI (04H), and
RDSR (05H); for hardware end-of-write detection—AAI Word (ADH) and WRDI (04H). There are three
options to determine the completion of each AAI Word program cycle: hardware detection by reading
the Serial Output, software detection by polling the BUSY bit in the software status register, or wait TBP.
Refer to“End-of-Write Detection” for details.
Prior to any write operation, the Write-Enable (WREN) instruction must be executed. Initiate the AAI
Word Program instruction by executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data are input sequentially, each one from MSB (Bit 7) to LSB (Bit
0). The first byte of data (D0) is programmed into the initial address [A23-A1] with A0=0, the second
byte of Data (D1) is programmed into the initial address [A23-A1] with A0=1. CE# must be driven high
before executing the AAI Word Program instruction. Check the BUSY status before entering the next
valid command. Once the device indicates it is no longer busy, data for the next two sequential
addresses may be programmed, followed by the next two, and so on.
When programming the last desired word, or the highest unprotected memory address, check the busy
status using either the hardware or software (RDSR instruction) method to check for program completion. Once programming is complete, use the applicable method to terminate AAI. If the device is in
Software End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction, 04H. If the
device is in AAI Hardware End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction,
04H, followed by the 8-bit DBSY command, 80H. There is no wrap mode during AAI programming
once the highest unprotected memory address is reached. See Figures 10 and 11 for the AAI Word
programming sequence.
End-of-Write Detection
There are three methods to determine completion of a program cycle during AAI Word programming:
hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the Software Status Register, or wait TBP. The Hardware End-of-Write detection method is described in the
section below.
Hardware End-of-Write Detection
The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the
Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures
the Serial Output (SO) pin to indicate Flash Busy status during AAI Word programming. (see Figure 8)
The 8-bit command, 70H, must be executed prior to initiating an AAI Word-Program instruction. Once
an internal programming operation begins, asserting CE# will immediately drive the status of the internal flash status on the SO pin. A ‘0’ indicates the device is busy and a ‘1’ indicates the device is ready
for the next instruction. De-asserting CE# will return the SO pin to tri-state. While in AAI and Hardware
End-of-Write detection mode, the only valid instructions are AAI Word (ADH) and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first execute WRDI instruction, 04H, to reset the WriteEnable-Latch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/
BY# status during the AAI command. See Figures 9 and 10.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
70
SI
MSB
HIGH IMPEDANCE
SO
1417 EnableSO.0
Figure 8: Enable SO as Hardware RY/BY# During AAI Programming
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
80
SI
MSB
HIGH IMPEDANCE
SO
1417 DisableSO.0
Figure 9: Disable SO as Hardware RY/BY# During AAI Programming
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
CE#
MODE 3
0
0
7
0
7
7 8
15 16 23 24
31 32
39 40 47
0
7 8
15 16 23
SCK MODE 0
SI
AD
WREN
EBSY
A
A
A
D0
D1
AD
D2
D3
Load AAI command, Address, 2 bytes data
SO
Check for Flash Busy Status to load next valid1 command
CE# cont.
0
7 8
15 16 23
0
7
0
7
0
7 8
15
SCK cont.
Dn-1
AD
SI cont.
WRDI
Dn
Last 2
Data Bytes
DBSY
RDSR
WRDI followed by DBSY
to exit AAI Mode
DOUT
SO cont.
Check for Flash Busy Status to load next valid1 command
Note:
1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
1417 AAI.HW.3
Figure 10:Auto Address Increment (AAI) Word-Program Sequence with
Hardware End-of-Write Detection
Wait TBP or poll Software Status
register to load next valid1 command
CE#
MODE 3
0
7 8
15 16 23 24
31 32 39 40 47
0
7 8
15 16 23
0
7 8
15 16 23
0
7
0
7 8
15
SCK MODE 0
SI
AD
A
A
A
D0
D1
AD
D2
D3
AD
Dn-1
Dn
Last 2
Data Bytes
Load AAI command, Address, 2 bytes data
WRDI
RDSR
WRDI to exit
AAI Mode
SO
Note:
DOUT
1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command
1417 AAI.SW.2
Figure 11:Auto Address Increment (AAI) Word-Program Sequence with
Software End-of-Write Detection
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
4-KByte Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the WriteEnable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to
determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait
TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 12 for the SectorErase sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
20
SI
MSB
ADD.
ADD.
ADD.
MSB
HIGH IMPEDANCE
SO
1417 SecErase.0
Figure 12:Sector-Erase Sequence
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A BlockErase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed.
CE# must remain active low for the duration of any command sequence. The 32-KByte Block-Erase
instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A23-A0]. Address
bits [AMS-A15] (AMS = Most Significant Address) are used to determine block address (BAX), remaining
address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The 64-KByte BlockErase instruction is initiated by executing an 8-bit command D8H, followed by address bits [A23-A0]. Address bits
[AMS-A15] are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be
driven high before the instruction is executed. The user may poll the Busy bit in the software status register or
wait TBE for the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 13 and 14 for the 32-KByte Block-Erase and 64-KByte Block-Erase sequences.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31
MODE 0
ADDR
52
SI
MSB
ADDR
ADDR
MSB
HIGH IMPEDANCE
SO
1417 32KBklEr.0
Figure 13:32-KByte Block-Erase Sequence
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
ADDR
D8
SI
MSB
ADDR
ADDR
MSB
HIGH IMPEDANCE
SO
1417 63KBlkEr.0
Figure 14:64-KByte Block-Erase Sequence
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven
high before the instruction is executed. The user may poll the Busy bit in the software status register or wait
TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase
sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60 or C7
SI
MSB
HIGH IMPEDANCE
SO
1417 ChEr.0
Figure 15:Chip-Erase Sequence
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The Status Register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is
in progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR
instruction sequence.
CE#
MODE 3
SCK
SI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
05
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
1417 RDSRseq.0
Figure 16:Read-Status-Register (RDSR) Sequence
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Read-Status-Register (RDSR1)
The Read-Status-Register 1 (RDSR1) instruction allows reading of the status register 1. CE# must be
driven low before the RDSR instruction is entered and remain low until the status data is read. ReadStatus-Register 1 is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 17 for the RDSR instruction sequence.
CE#
MODE 3
SCK
SI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
35
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status
Register Out
1417 RDSR1seq.0
Figure 17:Read-Status-Register 1 (RDSR1) Sequence
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/
Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared
upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSB
HIGH IMPEDANCE
SO
1417 WREN.0
Figure 18:Write Enable (WREN) Sequence
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any
new Write operations from occurring. The WRDI instruction will not terminate any programming operation in progress. Any program operation in progress may continue up to TBP after executing the WRDI
instruction. CE# must be driven high before the WRDI instruction is executed.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSB
HIGH IMPEDANCE
SO
1417 WRDI.0
Figure 19:Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)
instruction and opens the status register for alteration. The Write-Status-Register instruction must be
executed immediately after the execution of the Enable-Write-Status-Register instruction. This twostep instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP
(software data protection) command structure which prevents any accidental alteration of the status
register values. CE# must be driven low before the EWSR instruction is entered and must be driven
high before the EWSR instruction is executed.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status
register. CE# must be driven low before the command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 20 for EWSR or WREN and
WRSR for byte-data input sequences.
Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to
“1”. When the WP# is low, the BPL bit can only be set from “0” to “1” to lock-down the status register,
but cannot be reset from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled
and the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0
or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR
instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the
BP0, BP1, and BP2 bits at the same time. See Table 2 for a summary description of WP# and BPL
functions.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
01
50 or 06
SI
MSB
MSB
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
SO
1417 EWSR.0
Figure 20:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and
Write-Status-Register (WRSR) Byte-Data Input Sequence
The Write-Status-Register instruction also writes new values to the Status Register 1. To write values
to Status Register 1, the WRSR sequence needs a word-data input—the first byte being the Status
Register bits, followed by the second byte Status Register 1 bits. CE# must be driven low before the
command sequence of the WRSR instruction is entered and driven high before the WRSR instruction
is executed. See Figure 21 for EWSR or WREN and WRSR instruction word-data input sequences.
Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to
‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status registers,
but cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled
and the BPL, BP0, BP1, TSP, and BSP bits in the status register can all be changed. As long as BPL
bit is set to 0 or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end
of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well
as altering the BPL, BP0, BP1, TSP, and BSP bits at the same time. See Table 2 for a summary
description of WP# and BPL functions.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MODE 3
MODE 0
MODE 0
50 or 06
SI
01
MSB
MSB
STATUS
STATUS
REGISTER
REGISTER 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
HIGH IMPEDANCE
SO
1417 EWSR1.0
Figure 21:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and
Write-Status-Register (WRSR) Word-Data Input Sequence
The WRSR instruction can either execute a byte-data or a word-data input. Extra data/clock input, or
within byte-/word-data input, will not be executed. The reason for the byte support is for backward compatibility to products where WRSR instruction sequence is followed by only a byte-data.
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as SST25VF020B and the manufacturer as SST.
The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC
Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit
device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H,
identifies the memory type as SPI Serial Flash. Byte 3, 8CH, identifies the device as SST25VF020B.
The instruction sequence is shown in Figure 22. The JEDEC Read ID instruction is terminated by a low
to high transition on CE# at any time during data output.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MODE 0
9F
SI
SO
HIGH IMPEDANCE
BF
25
MSB
8C
MSB
1417 JEDECID.1
Figure 22:JEDEC Read-ID Sequence
Table 7: JEDEC Read-ID Data
Device ID
Manufacturer’s ID
Memory Type
Memory Capacity
Byte1
Byte 2
Byte 3
BFH
25H
8CH
T7.0 25054
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as SST25VF020B and manufacturer as SST. The
device information can be read from executing an 8-bit command, 90H or ABH, followed by address
bits [A23-A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H
and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a
low to high transition on CE#.
Refer to Tables 7 and 8 for device identification data.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
90 or AB
SI
00
00
MSB
ADD1
MSB
HIGH IMPEDANCE
SO
BF
Device ID
BF
Device ID
HIGH
IMPEDANCE
MSB
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
Device ID = 8CH for SST25VF020B
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
1417 RdID.0
Figure 23:Read-ID Sequence
Table 8: Product Identification
Manufacturer’s ID
Address
Data
00000H
BFH
00001H
8CH
Device ID
SST25VF020B
T8.0 25054
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
Table 9: Operating Range
Range
Commercial
Industrial
Ambient Temp
VDD
0°C to +70°C
2.7-3.6V
-40°C to +85°C
2.7-3.6V
T9.1 25054
Table 10: AC Conditions of Test1
Input Rise/Fall Time
Output Load
5ns
CL = 30 pF
T10.1 25054
1. See Figures 29 and 30
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Table 11: DC Operating Characteristics
Limits
Symbol Parameter
Min
Max Units Test Conditions
IDDR
Read Current
12
IDDR3
Read Current
20
mA
CE#=0.1 VDD/0.9 VDD@80 MHz, SO=open
IDDW
Program and Erase Current
30
mA
CE#=VDD
ISB
Standby Current
20
µA
CE#=VDD, VIN=VDD or VSS
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOL2
Output Low Voltage
VOH
Output High Voltage
mA
CE#=0.1 VDD/0.9 VDD@33 MHz, SO=open
1
µA
VOUT=GND to VDD, VDD=VDD Max
0.8
V
VDD=VDD Min
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
0.7 VDD
0.4
VDD-0.2
V
IOL=1.6 mA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
T11.0 25054
Table 12: Capacitance (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
COUT1
CIN1
Output Pin Capacitance
Input Capacitance
Test Condition
Maximum
VOUT = 0V
12 pF
VIN = 0V
6 pF
T12.0 25054
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 13: Reliability Characteristics
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1
Endurance
100,000
Cycles
JEDEC Standard A117
100
Years
100 + IDD
mA
TDR
1
ILTH1
Data Retention
Latch Up
JEDEC Standard A103
JEDEC Standard 78
T13.0 25054
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Table 14: AC Operating Characteristics
33 MHz
Symbol
Parameter
Min
80 MHz
Max
Min
Max
Units
80
MHz
FCLK1
Serial Clock Frequency
TSCKH
Serial Clock High Time
13
6
ns
TSCKL
Serial Clock Low Time
13
6
ns
TSCKR
2
33
Serial Clock Rise Time (Slew Rate)
0.1
0.1
V/ns
TSCKF
Serial Clock Fall Time (Slew Rate)
0.1
0.1
V/ns
TCES3
CE# Active Setup Time
5
5
ns
TCEH3
CE# Active Hold Time
5
5
ns
TCHS
3
CE# Not Active Setup Time
5
5
ns
TCHH3
CE# Not Active Hold Time
5
5
ns
TCPH
CE# High Time
50
TCHZ
CE# High to High-Z Output
TCLZ
SCK Low to Low-Z Output
0
0
ns
TDS
Data In Setup Time
2
2
ns
TDH
Data In Hold Time
4
4
ns
THLS
HOLD# Low Setup Time
5
5
ns
THHS
HOLD# High Setup Time
5
5
ns
THLH
HOLD# Low Hold Time
5
5
ns
THHH
HOLD# High Hold Time
5
THZ
HOLD# Low to High-Z Output
TLZ
HOLD# High to Low-Z Output
TOH
Output Hold from SCK Change
TV
Output Valid from SCK
10
6
ns
TSE
Sector-Erase
25
25
ms
50
15
ns
7
ns
5
7
7
0
ns
7
ns
7
ns
0
ns
TBE
Block-Erase
25
25
ms
TSCE
Chip-Erase
50
50
ms
TBP
Byte-Program
10
10
µs
T14.0 25054
1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz
2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
3. Relative to SCK.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
TCPH
CE#
TCHH
TCES
TCEH
TSCKF
TCHS
SCK
TDS
SI
SO
TDH
TSCKR
MSB
LSB
HIGH-Z
HIGH-Z
1417 SerIn.0
Figure 24:Serial Input Timing Diagram
CE#
TSCKH
TSCKL
SCK
TOH
TCLZ
SO
TCHZ
LSB
MSB
TV
SI
1417 SerOut.0
Figure 25:Serial Output Timing Diagram
CE#
THHH
THHS
THLS
SCK
THLH
THZ
TLZ
SO
SI
HOLD#
1417 Hold.0
Figure 26:Hold Timing Diagram
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Power-Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100
ms (0v - 3.0V in less than 300 ms). See Table 15 and Figure 27 for more information.
Table 15: Recommended System Power-up Timings
Symbol
Parameter
Minimum
Units
TPU-READ1
VDD Min to Read Operation
100
µs
VDD Min to Write Operation
100
µs
TPU-WRITE
1
T15.0 25054
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
VDD
VDD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
VDD Min
TPU-READ
TPU-WRITE
Device fully accessible
Time
1417 PwrUp.0
Figure 27:Power-up Timing Diagram
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Table 16: Recommended Power-up/-down Limits
Limits
Symbol
Parameter
Min
Max
Units
TPF
VDD Falling Time
1
100
ms/V
TPR
VDD Rising Time
0.033
100
ms/V
TOFF
VDD Off Time
VOFF
VDD Off Level
100
Conditions
ms
0.3
V
0V (recommended)
T16.0 25054
VDD
VOFF
GND
TOFF
1417 F28.0
Figure 28:Recommended Power-up/-down Waveform
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
VIHT
VHT
INPUT?
VHT
REFERENCE POINTS
OUTPUT
VLT
VLT
VILT
1417 IORef.0
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and
fall times (10% ↔ 90%) are <5 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH
Test
Figure 29:AC Input/Output Reference Waveforms
TO TESTER
TO DUT
CL
1417 TstLd.0
Figure 30:A Test Load Example
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Product Ordering Information
SST
25
VF
020B
-
80
-
4C
-
SAE
XX XX
XXXX
-
XX -
XX
-
XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
A = 8 leads or contacts
Package Type
S = SOIC 150 mil body width
Q = WSON(6mm x 5mm)
Q3 = USON (3mm x 2mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles2
Operating Frequency
80 = 80 MHz
Device Density
020 = 2 Mbit
Voltage
V = 2.7-3.6V
Product Series
25 = Serial Peripheral Interface flash
memory
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
2. Meets 100K minimum Endurance cycles.
Valid combinations for SST25VF020B
SST25VF020B-80-4C-QAE
SST25VF020B-80-4I-QAE
SST25VF020B-80-4C-SAE
SST25VF020B-80-4I-SAE
SST25VF020B-80-4C-Q3AE1
SST25VF020B-80-4I-Q3AE1
1. This product is only available in Tape and Reel format.
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2013 Silicon Storage Technology, Inc.
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Packaging Diagrams
Pin #1
Identifier
SIDE VIEW
TOP VIEW
7°
4 places
0.51
0.33
5.0
4.8
1.27 BSC
END VIEW
45°
0.25
0.10
4.00
3.80
1.75
1.35
6.20
5.80
7°
4 places
0.25
0.19
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
0°
8°
08-soic-5x6-SA-8
1.27
0.40
1mm
Figure 31: 8-Lead Small Outline Integrated Circuit (SOIC) 150mil Body Width (5mm x 6mm)
SST Package Code: SA
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Pin #1
0.2
Pin #1
Corner
1.27 BSC
5.00 ± 0.10
0.076
4.0
0.48
0.35
3.4
0.70
0.50
0.05 Max
6.00 ± 0.10
0.80
0.70
Note: 1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions.
3. The external paddle is electrically connected to the
1mm
die back-side and possibly to certain VSS leads.
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the VSS of the unit.
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.
CROSS SECTION
0.80
0.70
8-wson-5x6-QA-9.0
Figure 32:8-Contact Very-very-thin Small Outline No-lead (WSON)
SST Package Code: QA
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
2.45
3.00
±0.10
0.25
±0.05
Pin #1
(laser
engraved
see note 2)
See notes
3 &4
Pin # 1
1.60
2.00
±0.10
0.5 BSC
0.15 max
0.08
0.05 Max
0.60
0.45
0.40
±0.05
0.2
0.35
±0.05
1mm
8-uson-2x2-Q3A-1.1
Note: 1.
2.
3.
4.
5.
6.
Similar to JEDEC JEP95 MO-252 variant U2030D, though number of contacts and some dimensions may be different.
The topside pin #1 indicator is laser engraved; its approximate shape and location is as shown.
From the bottom view, the pin #1 indicator may be either a curved indent or a 45-degree chamfer.
Untoleranced dimensions are nominal target dimensions.
All linear dimensions are in millimeters (max/min).
Lead-frame nominal thickness 0.127mm or 0.15mm (supplier-dependent).
Figure 33:8-Contact Ultra-thin Small Outline No-lead (USON)
SST Package Code: Q3A
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2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Table 17: Revision History
Revision
00
01
02
03
A
B
C
Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Initial release of data sheet
Updated Table 4 on page 7
Added Figure 28 and Table 16 on page 30
Changed TDS value in Table 14 on page 27
Updated SST address on page 33
Changed document status to “Data Sheet”
Updated “Auto Address Increment (AAI) Word-Program”, “End-ofWrite Detection”, and “Hardware End-of-Write Detection” on page 14.
Revised Figures 10 and 11 on page 16.
Updated document to new format.
Removed duplicate Power-up table on page 26
Updated Endurance information on page 26 and page 32
Released document under new letter revision
Updated Spec number from S71417 to DS25054
Added Q3AE package
Updated “Product Ordering Information” on page 32
Date
Dec 2009
Feb 2010
Apr 2010
Feb 2011
Jan 2012
Sep 2012
Apr 2013
ISBN:978-1-62077-178-5
© 2013 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office locations and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
©2013 Silicon Storage Technology, Inc.
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