STMICROELECTRONICS STK20N75F3

STK20N75F3
N-channel 75 V, 0.0065 Ω, 20 A, PolarPAK®
STripFET™ Power MOSFET
Features
Type
VDSS
RDS(on) max
STK20N75F3
75 V
< 0.0079 Ω
■
Ultra low top and bottom junction to case
thermal resistance
■
Extremely low on-resistance RDS(on)
■
Very low switching gate charge
■
Fully encapsulated die
■
100% matte tin finish (in compliance with the
2002/95/EC european directive)
■
High avalanche ruggedness
■
PolarPAK® is a trademark of VISHAY
PolarPAK®
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Figure 1.
Application
■
Switching applications
Description
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This STripFET™ III Power MOSFET technology
is among the latest improvements, which have
been especially tailored to minimize on-state
resistance providing superior switching
performances.
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Internal schematic diagram
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Bottom View
Top View
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Table 1.
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Device summary
Order code
Marking
Package
Packaging
STK20N75F3
20753
PolarPAK®
Tape and reel
June 2009
Doc ID 14849 Rev 2
1/15
www.st.com
15
Contents
STK20N75F3
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
........................... 6
3
Test circuits
.............................................. 8
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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Doc ID 14849 Rev 2
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STK20N75F3
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
75
V
± 20
V
VDS
Drain-source voltage (VGS = 0)
VGS
Gate-source voltage
ID (1)
Drain current (continuous) at TC = 25°C
20
A
ID
Drain current (continuous) at TC = 100°C
12.5
A
Drain current (pulsed)
80
A
Total dissipation at TC = 25°C
5.2
W
IDM (2)
PTOT (1)
Derating factor
0.0416
EAS (3)
Single pulse avalanche energy
600
Tj
Operating junction temperature
Storage temperature
-55 to 150
Tstg
2. Pulse width limited by package
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3. Starting TJ = 25 °C, ID = 20 A, VDD = 50 V
Table 3.
Thermal data
Symbol
Rthj-amb(1)
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Parameter
(s)
Thermal resistance junction-amb
ct
mJ
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1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤ 10 sec
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W/°C
°C
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Typ.
Max.
Unit
20
24
°C/W
Rthj-c(2)
Thermal resistance junction-case (top drain)
0.8
1
°C/W
Rthj-c(3)
Thermal resistance junction-case (source)
2.2
2.7
°C/W
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1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤ 10sec
2. Steady state
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3. Measured at source pin when the device is mounted on FR-4 board in steady state
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Electrical characteristics
2
STK20N75F3
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 4.
On/off states
Symbol
Parameter
Drain-source breakdown
voltage
ID = 250 µA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
IGSS
Gate body leakage current
(VDS = 0)
VGS = ± 20V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 10 A
V(BR)DSS
Table 5.
Ciss
Coss
Crss
Qg
RG
Gate input resistance
Table 6.
Symbol
td(on)
tr
td(off)
tf
4/15
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Max.
75
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1
10
µA
µA
±100
nA
4
V
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Ω
Min.
Typ.
Max.
Unit
-
2480
446
41
-
pF
pF
pF
-
40.4
11.6
9.9
-
nC
nC
nC
-
0.85
-
Ω
(see Figure 14)
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
)
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0.0065 0.0079
VDD= 38 V, ID = 20 A
VGS =10 V
Unit
V
2
VDS =25 V, f=1 MHz, VGS=0
(s)
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Test conditions
Input capacitance
Output capacitance
Reverse transfer
capacitance
Qgd
Typ.
c
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Parameter
Total gate charge
Gate-source charge
Gate-drain charge
Qgs
Min.
VDS = Max rating,Tc=125°C
Dynamic
Symbol
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Test conditions
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
Typ.
Max.
Unit
-
15.6
16.2
-
ns
ns
-
37.8
4
-
ns
ns
VDD= 37.5 V, ID= 10 A,
RG=4.7 Ω, VGS= 10 V
(see Figure 13)
VDD=37.5 V, ID= 10 A,
RG=4.7 Ω, VGS= 10 V
(see Figure 13)
Doc ID 14849 Rev 2
STK20N75F3
Electrical characteristics
Table 7.
Source drain diode
Symbol
ISD
ISDM
(1)
VSD(2)
trr
Qrr
IRRM
Parameter
Test conditions
Source-drain current
Source-drain current
(pulsed)
Min.
Max.
Unit
-
20
80
A
A
1.2
V
Forward on Voltage
ISD= 20 A, VGS=0
-
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 20 A, di/dt = 100 A/µs,
VDD=60 V, Tj=150°C
-
Typ.
(see Figure 18)
49.7
103.6
4.2
ns
nC
A
1. Pulse width limited by package
2.
Pulsed: pulse duration = 300µs, duty cycle 1.5%
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Electrical characteristics
STK20N75F3
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
AM04908v1
ID
(A)
Tj=150°C
Tc=25°C
is
rea
s a S(on)
i
h
nt
RD
n i ax
tio
m
era d by
p
O
ite
Lim
100
Sinlge
pulse
10
1
10ms
100ms
1s
0.1
0.01
0.1
Figure 4.
ID
(A)
10
1
VDS(V)
Output characteristics
AM04909v1
VGS=10V
6V
200
ID
(A)
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200
150
100
AM04910v1
od
VDS=4V
250
150
uc
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100
5V
50
0
0
Figure 6.
50
2
1
3
4
5
)
s
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ct
6
7
du
Normalized BVDSS vs temperature
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BVDSS
(norm)
AM04911v1
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1.10
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Figure 7.
2
4
8
6
10 VGS(V)
Static drain-source on resistance
AM04912v1
RDS(on)
(Ω)
7.0
6.9
6.8
1.05
6.7
6.6
1.00
6.5
6.4
0.95
6.3
0.90
6.2
6.1
0
-50
6/15
0
0
8 VDS(V)
0
50
100
150
TJ(°C)
Doc ID 14849 Rev 2
5
10
15
20
ID(A)
STK20N75F3
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
AM04913v1
VGS
(V)
VDD=37.5V
12
Capacitance variations
AM04914v1
C (pF)
7000
ID=20A
6000
10
5000
8
4000
6
3000
Ciss
4
2000
2
1000
Crss
Coss
0
20
10
0
30
40
0
0
50 Qg(nC)
Figure 10. Normalized gate threshold voltage
vs temperature
AM04915v1
VGS(th)
(norm)
1.2
10
20
30
40
RDS(on)
(norm)
2.1
1.7
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1.5
1.3
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1.1
c
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ID=10A
1.9
0.8
VDS(V)
Figure 11. Normalized on resistance vs
temperature
VGS=10V
1.0
50
60 70
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AM00895v1
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0.9
0.6
0.7
0.4
-50
0
50
100
(t s)
150
c
u
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TJ(°C)
0.5
-50
0
50
100
150
TJ(°C)
Figure 12. Source-drain diode forward
characteristics
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VSD
(V)
0.9
AM04917v1
TJ=-50°C
t
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0.8
O
bs
TJ=25°C
0.7
0.6
TJ=175°C
0.5
0.4
0
5
10
15
20
ISD(A)
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Test circuits
3
STK20N75F3
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
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AM01469v1
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Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
A
e
t
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D
G
VD
L=100µH
S
3.3
µF
B
25 Ω
1000
µF
D
G
RG
S
)
s
(
ct
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o
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s
b
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VDD
t
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l
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s
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VDD
2200
µF
3.3
µF
VDD
ID
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
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AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/15
0
Doc ID 14849 Rev 2
10%
AM01473v1
STK20N75F3
Test circuits
Figure 19. Gate charge waveform
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
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Package mechanical data
4
STK20N75F3
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
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STK20N75F3
Package mechanical data
Table 8.
PolarPAK® (option “L”) mechanical data
mm
inch
Ref.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
0.75
0.80
0.85
0.030
0.031
0.033
A1
0.05
b1
0.48
0.58
0.68
0.019
0.023
0.027
b2
0.41
0.51
0.61
0.016
0.020
0.024
b3
2.19
2.29
2.39
0.086
0.090
0.094
b4
0.89
1.04
1.19
0.035
0.041
0.047
b5
0.23
0.33
0.43
0.009
0.013
0.017
c
0.20
0.25
0.30
0.008
0.010
0.012
D
6
6.15
6.30
0.236
0.242
0.248
D1
5.74
5.89
6.04
0.226
0.232
E
5.01
5.16
5.31
0.197
0.203
E1
4.75
4.90
5.05
0.187
0.193
H1
0.23
H2
0.45
H3
0.31
H4
0.45
K1
4.22
4.37
K2
1.08
1.13
K3
1.37
K4
0.24
M1
4.30
)
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M3
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3.43
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0.009
0.56
0.41
0.51
so
0.56
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M2
t
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0.002
b
O
-
0.012
uc
od
0.018
)
s
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0.238
0.209
0.199
0.022
0.016
0.018
0.020
0.022
4.52
0.166
0.172
0.178
1.18
0.043
0.044
0.046
0.054
0.009
4.50
4.70
0.169
0.177
0.185
3.58
3.73
0.135
0.141
0.147
0.22
0.009
M4
0.05
0.002
P1
0.15
0.20
0.25
0.006
0.008
0.010
T1
3.48
3.64
4.10
0.137
0.143
0.161
T2
0.56
0.76
0.95
0.022
0.030
0.037
T3
1.20
0.047
T4
3.90
0.154
0.007
0.014
10°
12°
T5
<
0°
0.18
0.36
10°
12°
Doc ID 14849 Rev 2
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11/15
Package mechanical data
STK20N75F3
Figure 20. PolarPAK® (option “L”) drawings
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STK20N75F3
Package mechanical data
Figure 21. Recommended PAD layout
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Revision history
5
STK20N75F3
Revision history
Table 9.
Document revision history
Date
Revision
Changes
01-Jul-2008
1
First release
22-Jun-2009
2
Document status promoted from preliminary data to datasheet.
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STK20N75F3
Please Read Carefully:
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time, without notice.
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UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
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ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
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Doc ID 14849 Rev 2
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