STL100NH3LL N-channel 30 V - 0.0032 Ω - 25 A - PowerFLAT™ (6x5) STripFET™ III Power MOSFET Features Type VDSS RDS(on) max ID STL100NH3LL 30 V <0.0035 Ω 25A (1) 1. The value is rated according Rthj-pcb ■ Improved die-to-footprint ratio ■ Very low profile package (1 mm max) ■ Very low thermal resistance ■ Conduction losses reduced ■ Switching losses reduced PowerFLAT™( 6x5 ) Application ■ Figure 1. Switching applications Internal schematic diagram Description This series utilizes the last advanced design rules of ST’s proprietary STripFET™ technology. This process complete to unique metallization technique realised the most advanced low voltage Power MOSFET in PowerFLAT™(6x5). The chipscaled PowerFLAT™ package allows a significant board space saving, still boosting the performance. Table 1. Device summary Order code Marking Package Packaging STL100NH3LL L100NH3LL PowerFLAT™ (6x5) Tape and reel March 2008 Rev 11 1/12 www.st.com 12 Contents STL100NH3LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 ................................................ 8 STL100NH3LL 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol VDS Parameter Drain-source voltage (VGS = 0) Value Unit 30 V VGS(1) Gate-source voltage ± 16 V VGS(2) Gate-source voltage ± 18 V ID(3) Drain current (continuous) at TC = 25 °C 100 A ID (3) Drain current (continuous) at TC = 100 °C 71 A ID (5) Drain current (continuous) at TC=100 °C 15.6 A (4) Drain current (pulsed) 100 A IDM ID(5) Drain current (continuous) at TC = 25 °C 25 A PTOT (3) Total dissipation at TC = 25 °C 80 W PTOT (5) Total dissipation at TC = 25 °C 4 W 0.03 W/°C -55 to 150 °C Derating factor TJ Operating junction temperature Storage temperature Tstg 1. Continuous mode 2. Guaranteed for test time ≤15ms 3. The value is rated according Rthj-c 4. Pulse width limited by safe operating area 5. The value is rated according Rthj-pcb Table 3. Thermal resistance Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case (drain) (steady state) 1.56 °C/W Thermal resistance junction-ambient 31.3 °C/W Value Unit Rthj-pcb (1) 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec Table 4. Symbol Avalanche data Parameter IAV Not-repetitive avalanche current 7.5 A EAS Single pulse avalanche energy (starting TJ=25 °C, ID=7.5 A) 150 mJ 3/12 Electrical characteristics 2 STL100NH3LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 5. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Test conditions ID = 250 µA, VGS= 0 Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = ±16 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 10 V, ID= 12.5 A Symbol gfs (1) Ciss Coss Crss Qg 30 1 1 10 µA µA ±100 nA 2.5 V 0.0032 0.0035 0.004 0.005 VGS= 4.5 V, ID= 12.5 A Unit V VDS = Max rating @125 °C Parameter Test conditions Forward transconductance VDS =10 V, ID = 12.5 A Input capacitance Output capacitance Reverse transfer capacitance VDS =25 V, f=1 MHz, VGS=0 Qgd RG Gate input resistance Min. VDD=15 V, ID = 25 A VGS =4.5 V (see Figure 8) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain 1. Pulsed: pulse duration=300 µs, duty cycle 1.5% 4/12 Max. Ω Ω Dynamic Total gate charge Gate-source charge Gate-drain charge Qgs Typ. VDS = Max rating, IDSS Table 6. Min. 1 Typ. Max. Unit 30 S 4450 655 50 pF pF pF 30 12.5 10 40 nC nC nC 2 3 Ω STL100NH3LL Electrical characteristics Table 7. Symbol td(on) tr td(off) tf Table 8. Symbol Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. 18 50 75 8 VDD=15 V, ID= 12.5 A, RG=4.7 Ω, VGS=10 V (see Figure 14) Unit ns ns ns ns Source drain diode Max Unit Source-drain current 25 A ISDM(1) Source-drain current (pulsed) 100 A VSD(2) Forward on voltage ISD=25 A, VGS=0 1.3 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD=25 A, ISD trr Qrr IRRM Parameter Test conditions di/dt = 100 A/µs, VDD=25 V, Tj=150 °C Min Typ. 32 34 2.1 ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/12 Electrical characteristics STL100NH3LL 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Transconductance Figure 7. Static drain-source on resistance 6/12 STL100NH3LL Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs temperature Figure 11. Normalized on resistance vs temperature Figure 12. Source-drain diode forward characteristics Figure 13. Normalized BVDSS vs temperature 7/12 Test circuit 3 STL100NH3LL Test circuit Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit Figure 18. Unclamped inductive waveform 8/12 Figure 19. Switching time waveform STL100NH3LL 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12 Package mechanical data STL100NH3LL PowerFLAT™ (6x5) MECHANICAL DATA mm. inch DIM. A MIN. TYP MAX. MIN. TYP. MAX. 0.80 0.83 0.93 0.031 0.032 0.036 0.02 0.05 0.0007 0.0019 A1 A3 b 0.20 0.35 0.007 0.47 0.013 0.015 D 5.00 0.196 D1 4.75 0.187 D2 4.15 4.20 4.25 0.163 0.165 E 6.00 0.236 E1 5.75 0.226 E2 3.43 3.48 3.53 E4 2.58 2.63 2.68 e L 10/12 0.40 0.135 1.27 0.70 0.80 0.018 0.167 0.137 0.139 0.103 0.105 0.050 0.90 0.027 0.031 0.035 STL100NH3LL 5 Revision history Revision history Table 9. Document revision history Date Revision Changes 18-Apr-2005 1 First Release 20-Jun-2005 2 Updated mechanical data 22-Jun-2005 3 New Rg value on Table 7 10-Oct-2005 4 Inserted ecopack indication 09-Jan-2006 5 New footprint 08-Mar-2006 6 New template 29-Jun-2006 7 Modified curves, see Figure 2 and Figure 3 04-Sep-2006 8 The document has been reformatted, no content change 04-Jan-2007 9 New updated on Table 2 10-Dec-2007 10 Updated data on Table 4: Avalanche data 20-Mar-2008 11 New VGS max. value inserted on Table 4: Avalanche data 11/12 STL100NH3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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