STMICROELECTRONICS STM8L151G4U3

STM8L151xx, STM8L152xx
8-bit ultralow power MCU, up to 32 KB Flash, 1 KB Data EEPROM
RTC, LCD, timers, USART, I2C, SPI, ADC, DAC, comparators
Preliminary data
Features
■
■
Operating conditions
– Operating power supply range 1.8 V to
3.6 V (down to 1.65 V at power down)
– Temperature range: - 40 °C to 85 or 125 °C
Low power features
– 5 low power modes: Wait , Low power run
(5.4 µA), Low power wait (3 µA), Active-halt
with RTC (1 µA), Halt (400 nA)
– Dynamic consumption: 192 µA/MHz
– Ultralow leakage per I/0: 50 nA
– Fast wakeup from Halt: 5 µs
■
Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq. 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
■
Reset and supply management
– Low power, ultrasafe BOR reset with 5
selectable thresholds
– Ultralow power POR/PDR
– Programmable voltage detector (PVD)
■
Clock management
– 1 to 16 MHz crystal oscillator
– 32 kHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– Internal 38 kHz low consumption RC
– Clock security system
■
Low power RTC
– BCD calendar with alarm interrupt
– Auto-wakeup from Halt w/ periodic interrupt
■
LCD: up to 4x28 segments w/ step-up converter
■
Memories
– Up to 32 KB of Flash program memory and
1 Kbyte of data EEPROM with ECC, RWW
– Flexible write and read protection modes
– Up to 2 Kbytes of RAM
■
■
LQFP48
VFQFPN48
LQFP32
WFQFPN32
WFQFPN28
■
12-bit ADC up to 1 Msps/25 channels
– T. sensor and internal reference voltage
■
2 Ultralow power comparators
– 1 with fixed threshold and 1 rail to rail
– Wakeup capability
■
Timers
– Two 16-bit timers with 2 channels (used as
IC, OC, PWM), quadrature encoder
– One 16-bit advanced control timer with 3
channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– 2 watchdogs: 1 Window, 1 Independent
– Beeper timer with 1, 2 or 4 kHz frequencies
■
Communication interfaces
– Synchronous serial interface (SPI)
– Fast I2C 400 kHz SMBus and PMBus
– USART (ISO 7816 interface and IrDA)
■
Up to 41 I/Os, all mappable on interrupt vectors
■
Up to 16 capacitive sensing channels with free
firmware
■
Development support
– Fast on-chip programming and non intrusive
debugging with SWIM
– Bootloader using USART
■
96-bit unique ID
Table 1.
Device summary
Reference
Part number
DMA
– 4 channels; supported peripherals: ADC,
DAC, SPI, I2C, USART, timers
– 1 channel for memory-to-memory
STM8L151xx
(without LCD)
STM8L151C6, STM8L151C4,
STM8L151K6, STM8L151K4,
STM8L151G6, STM8L151G4
12-bit DAC with output buffer
STM8L152xx
(with LCD)
STM8L152C6, STM8L152C4,
STM8L152K6, STM8L152K4
September 2009
Doc ID 15962 Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/101
www.st.com
1
Contents
STM8L151xx, STM8L152xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11
Ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12
System configuration controller and routing interface . . . . . . . . . . . . . . . 19
3.13
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14
3.15
2/101
3.2.1
3.13.1
TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.2
16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.3
8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1
Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.2
Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
3.16
4
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.16.1
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.16.2
I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.16.3
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17
Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.18
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
5
Contents
System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.3.2
Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 59
8.3.3
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.3.4
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3.6
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.3.7
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.3.8
LCD controller (STM8L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.3.9
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.3.10
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Doc ID 15962 Rev 2
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Contents
STM8L151xx, STM8L152xx
8.4
9
8.3.11
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3.12
12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.3.13
12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.3.14
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.1
ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8L15x low power device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 10
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM8L15x pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Total current consumption and timing in Low power run mode at VDD = 1.65 V to
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 65
Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Total current consumption and timing in Halt mode at VDD = 2 V . . . . . . . . . . . . . . . . . . 67
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 75
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DAC characteristics, output on PF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Doc ID 15962 Rev 2
5/101
List of tables
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
6/101
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ADC1 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
WFQFPN28 – 28-lead very very thin fine pitch quad flat no-lead package (4 x 4),
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
WFQFPN32 – 32-lead very very thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP32 – 32-pin low profile quad flat package, package mechanical data . . . . . . . . . . . . 96
VFQFPN48 – very thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm
pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP48 – 48-pin low profile quad flat package (7x7), package mechanical data . . . . . . . 98
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
STM8L15xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STM8L15x clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM8L151Gx 28-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM8L151Kx 32-pin package pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM8L152Kx 32-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM8L151Cx 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM8L152Cx 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 88
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 89
WFQFPN28 – 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) . 94
Recommended footprint (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
WFQFPN32 – 32-lead very very thin fine pitch quad flat no-lead package
outline (5 x 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP32 – 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Recommended footprint (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP48 – 48-pin low profile quad flat package outline (7x7) . . . . . . . . . . . . . . . . . . . . . . . 98
STM8L15xxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Doc ID 15962 Rev 2
7/101
Introduction
1
STM8L151xx, STM8L152xx
Introduction
This document describes the STM8L15xxx family features, pinout, mechanical data and
ordering information.
For more details on the whole STMicroelectronics Ultralow power family please refer to
Section 2.2: Ultralow power continuum on page 11.
The reference manual and Flash programming manuals will be available soon.
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
2
Description
The STM8L15xxx devices are members of the STM8L Ultralow power 8-bit family. They are
referred to as medium-density devices in the STM8L15xxx reference manual (RM0031) and
in the STM8L Flash programming manual (PM0054). They provide the following benefits:
●
●
●
●
Integrated system
–
Up to 32 Kbytes of medium-density embedded Flash program memory
–
1 Kbyte of data EEPROM
–
Internal high speed and low-power low speed RC.
–
Embedded reset
Ultralow power consumption
–
192 µA/MHZ (dynamic consumption)
–
1 µA in Active-halt mode
–
Clock gated system and optimized power management
–
Capability to execute from RAM for Low power wait mode and Low power run
mode
Advanced features
–
Up to 16 MIPS at 16 MHz CPU clock frequency
–
Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access.
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals.
–
Wide choice of development tools
The STM8L15xxx family operates from 1.8 V to 3.6 V (down to 1.65 V at power down) and is
available in the -40 to +85 °C and -40 to +125 °C temperature ranges.
The STM8L15xxx Ultralow power family features the enhanced STM8 CPU core providing
increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of
8/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Description
a CISC architecture with improved code density, a 24-bit linear addressing space and an
optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive In-Application debugging and ultrafast Flash programming.
All STM8L15xxx microcontrollers feature embedded data EEPROM and low power lowvoltage single-supply program Flash memory.
The STM8L15xxx family 8-bit microcontrollers incorporate an extensive range of enhanced
I/Os and peripherals. All devices offer 12-bit ADC, DAC, two comparators, Real-time clock
three 16-bit timers, one 8-bit timer as well as standard communication interface such as SPI,
I2C and USART. A 4x28-segment LCD is available on the STM8L152xx line.
The modular design of the peripheral set allows the same peripherals to be found in different
ST microcontroller families including 32-bit families. This makes any transition to a different
family very easy, and simplified even more by the use of a common set of development
tools.
These features make the STM8L15xxx microcontroller family suitable for a wide range of
applications:
●
Medical and handheld equipment
●
Application control and user interface
●
PC peripherals, gaming, GPS and sport equipment
●
Alarm systems, wired and wireless sensors
Figure 1 on page 12 shows the general block diagram of the device family.
Six different packages are proposed from 28 to 48 pins. Depending on the device chosen,
different sets of peripherals are included. Section 3 on page 12 gives an overview of the
complete range of peripherals proposed in this family.
All STM8L Ultralow power products are based on the same architecture with the same
memory mapping and a coherent pinout.
Doc ID 15962 Rev 2
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Description
STM8L151xx, STM8L152xx
2.1
Device overview
Table 2.
STM8L15x low power device features and peripheral counts
Features
Flash (Kbytes)
STM8L151Gx
16
32
STM8L15xKx
16
32
Data EEPROM (Kbytes)
RAM-Kbytes
Timers
16
32
1
2
LCD
STM8L15xCx
2
No
4x17
2
(1)
4x28 (1)
Basic
1
(8-bit)
1
(8-bit)
1
(8-bit)
General purpose
2
(16-bit)
2
(16-bit)
2
(16-bit)
Advanced control
1
(16-bit)
1
(16-bit)
1
(16-bit)
1
1
1
1
1
1
SPI
Communication
I2C
interfaces
USART
1
1
(3)
30
(2)(3)
or 29
1
(1)(3)
41(3)
GPIOs
26
12-bit synchronized ADC
(number of channels)
1
(18)
1
(22 (2) or 21 (1))
1
(25)
12-Bit DAC
(number of channels)
1
(1)
1
(1)
1
(1)
2
2
2
Comparators COMP1/COMP2
Others
RTC, window watchdog, independent watchdog,
16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator
CPU frequency
Operating voltage
16 MHz
1.8 V to 3.6 V (down to 1.65 V at power down)
Operating temperature
Packages
-40 to +85 °C / -40 to +125 °C
WFQFPN28 (4)(4x4;
0.8 mm thickness)
WFQFPN32 (5)(5x5;
0.8 mm thickness)
LQFP32(7x7)
VFQFPN48 (6)(4x4;
1 mm thickness)
LQFP48
1. STM8L152xx versions only
2. STM8L151xx versions only
3. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as
general purpose output only (PA1).
4. WFQFPN28 package used in the sampling phase. In the production phase, the UFQFPN28 package will be used with a
thickness equal to 0.6 mm.
5. WFQFPN32 package used in the sampling phase. In the production phase, the UFQFPN32 package will be used with a
thickness equal to 0.6 mm.
6. VFQFPN48 package used in the sampling phase. In the production phase, the UFQFPN48 package will be used with a
thickness equal to 0.6 mm.
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STM8L151xx, STM8L152xx
2.2
Description
Ultralow power continuum
The Ultralow power STM8L151xx and STM8L152xx are fully pin-to-pin, software and feature
compatible. Besides the full compatibility within the family, the devices are part of
STMicroelectronics microcontrollers UtraLowPower strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm ultralow leakage process.
Note:
1
The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices.
2
The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15x documentation for more information on these devices.
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the Ultralow power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
STM8L151xx/152xx and STM32L15xx share identical peripherals which ensure a very easy
migration from one family to another:
●
Analog peripherals: ADC1, DAC, and comparators COMP1/COMP2
●
Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L151xx/152xx and STM32L15xx
devices use a common architecture:
●
Same power supply range from 1.8 to 3.6 V, down to 1.65 V at power down
●
Architecture optimized to reach ultralow consumption both in low power modes and
Run mode
●
Fast startup strategy from low power modes
●
Flexible system clock
●
Ultrasafe reset: same reset strategy for both STM8L15xxx and STM32L15xxx including
power-on reset, power-down reset, brownout reset and programmable voltage detector.
Features
ST UtraLowPower continuum also lies in feature compatibility:
●
More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
●
Memory density ranging from 4 to 128 Kbytes
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Functional overview
STM8L151xx, STM8L152xx
3
Functional overview
Figure 1.
STM8L15xxx device block diagram
OSC_IN,
OSC_OUT
16 MHz internal RC
OSC32_IN,
OSC32_OUT
@VDD
1-16 MHz oscillator
32 kHz oscillator
Clock
controller
and
CSS
38 kHz internal RC
VDD18
Clocks
to core and
peripherals
Interrupt controller
Debug module
(SWIM)
BOR
16-bit Timer 2
2 channels
16-bit Timer 3
3 channels
16-bit Timer 1
8-bit Timer 4
Infrared interface
DMA1
(4 channels)
VREFINT out
COMP1_INP
COMP2_INP
COMP2_INM
DAC_OUT
VDDREF
VSSREF
VLCD = 2.5 V to
3.6 V
2 Kbytes RAM
Port C
PC[7:0]
Port D
PD[7:0]
Port E
PE[7:0]
12-bit ADC1
Port F
PF0
Temp sensor
Beeper
BEEP
RTC
ALARM, CALIB
USART1
@VDDA/VSSA
Internal reference
voltage
IWDG
(38 kHz clock)
COMP 1
WWDG
COMP 2
12-bitDAC
DAC
12-bit
LCD driver
4x28
LCD booster
1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
DAC: Digital-to-analog converter
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent watchdog
LCD: Liquid crystal display
POR/PDR: Power on reset / power down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
12/101
32 Kbytes
Program memory
1 Kbyte
Data EEPROM
PB[7:0]
SPI1
VDDREF
VSSREF
PVD_IN
Port B
I²C1
ADC1_INx
NRST
PA[7:0]
MOSI, MISO,
SCK, NSS
VDDA
VSSA
PVD
VDD =1.65 V
to 3.6 V
VSS
Port A
SCL, SDA,
SMB
RX, TX, CK
RESET
POR/PDR
2 channels
IR_TIM
VOLT. REG.
STM8 Core
Address, control and data buses
SWIM
Power
Doc ID 15962 Rev 2
SEGx, COMx
STM8L151xx, STM8L152xx
3.1
Functional overview
Low power modes
The STM8L15xxx supports five low power modes to achieve the best compromise between
low power consumption, short startup time and available wakeup sources:
●
Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal
or external interrupt or a Reset can be used to exit the microcontroller from Wait mode
(WFE or WFI mode). Wait consumption is around 350 µA.
●
Low power run mode: CPU clock runs. Flash, data EEPROM, voltage regulator and
all peripherals are stopped except RTC and one other peripheral which can remain
active (ex: one timer). Execution is done from RAM with a low speed oscillator (LSI or
LSE). The microcontroller enters Low power run mode by software and can exit from
this mode by software or by a Reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode. Low power run mode consumption is around 5.4 µA (peripherals OFF).
●
Low power wait mode: This mode is entered when executing a Wait for event in Low
power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an
event, the system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode. Low power wait mode consumption is around 3 µA (peripherals OFF).
●
Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset. Active-halt
consumption with RTC on LSI is 0.9 µA. Active-halt consumption with RTC on LSE is
1 µA.
●
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The wakeup is triggered by an external interrupt or reset. A few peripherals have also a
wakeup from Halt capability. Switching off the internal reference voltage reduces power
consumption. Through software configuration it is also possible to wake up the device
without waiting for the internal reference voltage wakeup time to have a fast wakeup
time of 6 µs. Halt consumption is 400 nA.
Dynamic consumption in run mode is 190 µA/MHz.
3.2
Central processing unit STM8
3.2.1
Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
●
Harvard architecture
●
3-stage pipeline
●
32-bit wide program memory bus - single cycle fetching most instructions
●
X and Y 16-bit index registers - enabling indexed addressing modes with or without
Doc ID 15962 Rev 2
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Functional overview
STM8L151xx, STM8L152xx
offset and read-modify-write type data manipulations
●
8-bit accumulator
●
24-bit program counter - 16 Mbyte linear memory space
●
16-bit stack pointer - access to a 64 Kbyte level stack
●
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
●
20 addressing modes
●
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
●
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
3.2.2
●
80 instructions with 2-byte average instruction size
●
Standard data movement and logic/arithmetic functions
●
8-bit by 8-bit multiplication
●
16-bit by 8-bit and 16-bit by 16-bit division
●
Bit manipulation
●
Data transfer between stack and accumulator (push/pop) with direct stack access
●
Data transfer using the X and Y registers or direct memory-to-memory transfers
Interrupt controller
The STM8L15xxx features a nested vectored interrupt controller:
14/101
●
Nested interrupts with 3 software priority levels
●
32 interrupt vectors with hardware priority
●
Up to 40 external interrupt sources on 11 vectors
●
Trap and reset interrupts
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Functional overview
3.3
Reset and supply management
3.3.1
Power supply scheme
The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:
3.3.2
●
VSS ; VDD = 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for I/Os
and for the internal regulator. Provided externally through VDD pins, the corresponding
ground pin is VSS.
●
VSSA ; VDDA = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for
analog peripherals (minimum voltage to be applied to VDDA is 1.8 V when the ADC1 is
used). VDDA and VSSA must be connected to VDD and VSS, respectively.
●
VSSIO ; VDDIO = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for
I/Os. VDDIO and VSSIO must be connected to VDD and VSS, respectively.
●
VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.
●
VREF+ (for DAC): external voltage reference for DAC must be provided externally
through VREF+.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached,
the option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently (in which case, the VDD min value at power down is 1.65 V).
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains in
reset state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for
any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3
Voltage regulator
The STM8L15xxx embeds an internal voltage regulator for generating the 1.8 V power
supply for the core and peripherals.
This regulator has two different modes:
●
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
●
Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low
power wait modes.
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Functional overview
STM8L151xx, STM8L152xx
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
3.4
Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
16/101
●
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
●
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register.
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
●
System clock sources: 4 different clock sources can be used to drive the system
clock:
–
1-16 MHz High speed external crystal (HSE)
–
16 MHz High speed internal RC oscillator (HSI)
–
32.768 Low speed external crystal (LSE)
–
38 kHz Low speed internal RC (LSI)
●
RTC and LCD clock sources: the above four sources can be chosen to clock the RTC
and the LCD, whatever the system clock.
●
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
●
Clock security system (CSS): This feature can be enabled by software. If a HSE clock
failure occurs, the system clock is automatically switched to HSI.
●
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Figure 2.
Functional overview
STM8L15x clock tree diagram
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3.5
Low power real-time clock
The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.
Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically.
It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.
●
Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is
from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours
●
Periodic alarms based on the calendar can also be generated from every second to
every year
●
Active-halt consumption with LSI and Auto-wakeup: 0.9 µA
●
Active-halt consumption with LSE, calendar and auto-wakeup: 1 µA
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Functional overview
3.6
STM8L151xx, STM8L152xx
LCD (Liquid crystal display)
The liquid crystal display drives up to 4 common terminals and up to 28 segment terminals
to drive up to 112 pixels.
●
Internal step-up converter to guarantee contrast control whatever VDD.
●
Static 1/2, 1/3, 1/4 duty supported.
●
Static 1/2, 1/3 bias supported.
●
Phase inversion to reduce power consumption and EMI.
●
Up to 4 pixels which can programmed to blink.
●
The LCD controller can operate in Halt mode.
Note:
Unnecessary segments and common pins can be used as general I/O pins.
3.7
Memories
The STM8L15xxx devices have the following main features:
●
Up to 2 Kbytes of RAM
●
The non-volatile memory is divided into three arrays:
–
Up to 32 Kbytes of medium-density embedded Flash program memory
–
1 Kbyte of Data EEPROM
–
Option bytes.
The EEPROM embeds the error correction code (ECC) feature. It supports the read-whilewrite (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.
3.8
DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, DAC, I2C1, SPI1, USART1, the 4 Timers.
3.9
Note:
18/101
Analog-to-digital converter
●
12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel),
temperature sensor and internal reference voltage
●
Conversion time down to 1 µs with fSYSCLK= 16 MHz
●
Programmable resolution
●
Programmable sampling time
●
Single and continuous mode of conversion
●
Scan capability: automatic conversion performed on a selected group of analog inputs
●
Analog watchdog
●
Triggered by timer
ADC1 can be served by DMA1.
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
3.10
Functional overview
Digital-to-analog converter (DAC)
●
12-bit DAC with output buffer
●
Synchronized update capability using TIM4
●
DMA capability
●
External triggers for conversion
●
Input reference voltage VREF+ for better resolution
Note:
DAC can be served by DMA1.
3.11
Ultralow power comparators
The STM8L15x embeds two comparators (COMP1 and COMP2) sharing the same current
bias and voltage reference. The voltage reference can be internal or external (coming from
an I/O).
●
One comparator with fixed threshold (COMP1).
●
One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one
of the following:
–
DAC output
–
External I/O
–
Internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4)
The two comparators can be used together to offer a window function. They can wake up
from Halt mode.
3.12
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.
The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1, COMP1, COMP2, DAC and the internal reference voltage VREFINT. Finally,
it provides a set of registers for efficiently managing a set of dedicated I/Os supporting up to
16 capacitive sensing channels using the ProxSenseTM technology.
3.13
Timers
STM8L15xxx devices contain one advanced control timer (TIM1), two 16-bit general
purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).
All the timers can be served by DMA1.
Table 3 compares the features of the advanced control, general-purpose and basic timers.
Doc ID 15962 Rev 2
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Functional overview
Table 3.
Timer
STM8L151xx, STM8L152xx
Timer feature comparison
Counter Counter
resolution
type
16-bit
3.13.1
Capture/compare
channels
Complementary
outputs
3+1
3
up/down
Any power of 2
from 1 to 128
TIM3
TIM4
DMA1
request
generation
Any integer
from 1 to 65536
TIM1
TIM2
Prescaler factor
Yes
2
None
8-bit
up
Any power of 2
from 1 to 32768
0
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
3.13.2
3.13.3
●
16-bit up, down and up/down autoreload counter with 16-bit prescaler
●
3 independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse
mode output
●
1 additional capture/compare channel which is not connected to an external I/O
●
Synchronization module to control the timer with external signals
●
Break input to force timer outputs into a defined state
●
3 complementary outputs with adjustable dead time
●
Encoder mode
●
Interrupt capability on various events (capture, compare, overflow, break, trigger)
16-bit general purpose timers
●
16-bit autoreload (AR) up/down-counter
●
7-bit prescaler adjustable to fixed power of 2 ratios (1…128)
●
2 individually configurable capture/compare channels
●
PWM mode
●
Interrupt capability on various events (capture, compare, overflow, break, trigger)
●
Synchronization with other timers or external signals (external clock, reset, trigger and
enable)
8-bit basic timer
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer overflow
or for DAC trigger generation.
20/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
3.14
Functional overview
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
3.14.1
Window watchdog timer
The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
3.14.2
Independent watchdog timer
The independent watchdog peripheral (IWDG) can be used to resolve processor
malfunctions due to hardware or software failures.
It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.
3.15
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
3.16
Communication interfaces
3.16.1
SPI
The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial
communication with external devices.
●
Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave
●
Full duplex synchronous transfers
●
Simplex synchronous transfers on 2 lines with a possible bidirectional data line
●
Master or slave operation - selectable by hardware or software
●
Hardware CRC calculation
●
Slave/master selection input pin
Note:
SPI1 can be served by the DMA1 Controller.
3.16.2
I²C
The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C busspecific sequencing, protocol, arbitration and timing.
●
Master, slave and multi-master capability
●
Standard mode up to 100 kHz and fast speed modes up to 400 kHz.
●
7-bit and 10-bit addressing modes.
●
SMBus 2.0 and PMBus support
●
Hardware CRC calculation
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Functional overview
STM8L151xx, STM8L152xx
Note:
I2C1 can be served by the DMA1 Controller.
3.16.3
USART
The USART interface (USART1) allows full duplex, asynchronous communications with
external devices requiring an industry standard NRZ asynchronous serial data format. It
offers a very wide range of baud rates.
●
1 Mbit/s full duplex SCI
●
SPI1 emulation
●
High precision baud rate generator
●
Smartcard emulation
●
IrDA SIR encoder decoder
●
Single wire half duplex mode
Note:
USART1 can be served by the DMA1 Controller.
3.17
Infrared (IR) interface
The STM8L15x devices contain an infrared interface which can be used with an IR LED for
remote control functions. Two timer output compare channels are used to generate the
infrared remote control signals.
3.18
Development support
Development tools
Development tools for the STM8 microcontrollers include:
●
The STice emulation system offering tracing and code profiling
●
The STVD high-level language debugger including C compiler, assembler and
integrated development environment
●
The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers.
Bootloader
A bootloader is available to reprogram the Flash memory using the USART1 interface.
22/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Pin description
PA0
PC6
PC5
PC4
PC3
PC2
PC1
STM8L151Gx 28-pin package pinout
28
27
26
25
24
23
22
PD4
PA3
3
19
PB7
PA4
4
18
PB6
PA5
5
17
PB5
VSS/VSSA/VREFVDD/VDDA/VREF+
6
16
PB4
7
15
PB3
PD0
8
10
11
12
13
14
STM8L151Kx 32-pin package pinout (without LCD)
PA0
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Figure 4.
9
PB2
20
PB1
PC0
2
PB0
21
PA2
PD3
1
PD2
NRST/PA1
PD1
Figure 3.
32
NRST/PA1
PA2
PA3
PA4
PA5
PA6
VSS
VDD
31 30 29 28
27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
17
8
10 11 12 13
14 15 16
PD0
PD1
PD2
PD3
PB0
PB1
PB2
PB3
9
PD7
PD6
PD5
PD4
PB7
PB6
PB5
PB4
1. Example given for the WFQFPN32 package. The pinout is the same for the LQFP32 package.
STM8L152Kx 32-pin package pinout (with LCD)
PA0
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Figure 5.
32
NRST/PA1
PA2
PA3
PA4
PA5
PA6
VSS
VDD
31 30 29 28
27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
18
7
17
8
9
10 11 12 13
PD7
PD6
PD5
PD4
PB7
PB6
PB5
PB4
14 15 16
VLCD
PD1
PD2
PD3
PB0
PB1
PB2
PB3
4
Pin description
1. Example given for the WFQFPN32 package. The pinout is the same for the LQFP32 package.
Doc ID 15962 Rev 2
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Pin description
STM8L151Cx 48-pin pinout (without LCD)
PE7
PE6
PC7
PC6
PC5
PC4
PC3
PC2
VSSIO
VDDIO
PC1
PC0
Figure 6.
STM8L151xx, STM8L152xx
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
PD7
PD6
PD5
PD4
PF0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
Res. (1)
PE0
PE1
PE2
PE3
PE4
PE5
PD0
PD1
PD2
PD3
PB0
PA0
NRST/PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS/VSSA/VREFVDD
VDDA
VREF+
1. Reserved. Must be tied to VDD.
STM8L152Cx 48-pin pinout (with LCD)
PE7
PE6
PC7
PC6
PC5
PC4
PC3
PC2
VSSIO
VDDIO
PC1
PC0
Figure 7.
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VLCD
PE0
PE1
PE2
PE3
PE4
PE5
PD0
PD1
PD2
PD3
PB0
PA0
NRST/PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS/VSSA/VREFVDD
VDDA
VREF+
24/101
Doc ID 15962 Rev 2
PD7
PD6
PD5
PD4
PF0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
STM8L151xx, STM8L152xx
Pin description
Legend / Abbreviations for Table 4:
Type:
I = input, O = output, S = power supply
I/O level:
FT = 5 V tolerant
Input level:
CM = CMOS
Output level:
HS = High sink/source (20 mA)
Port and control configuration:
●
Input:
float = floating, wpu = weak pull-up
●
Output:
T= true open drain, OD = open drain, PP = push-pull
Reset state is shown in bold.
STM8L15x pin description
PA2/OSC_IN/
2 [USART1_TX](3)/
[SPI1_MISO] (3)
I/O
X
X
4
3
3
PA3/OSC_OUT/[USART1
I/O
_RX](3)/[SPI1_MOSI](3)
X
5
-
PA4/TIM2_BKIN/
- LCD_COM0(2)/ADC1_IN2/ I/O
COMP1_INP
X
-
4
PA4/TIM2_BKIN/
[TIM2_TRIG](3)/
4
LCD_COM0(2)/
ADC1_IN2/COMP1_INP
6
-
7
Main function
(after reset)
2
PP
3
Output
OD
I/O
wpu
1 NRST/PA1(1)
floating
WFQFPN28
1
I/O level
WFQFPN32
2
Pin name
Type
VFQFPN48 and LQFP48
Input
High sink/source
Pin
number
Ext. interrupt
Table 4.
Default alternate function
HS X
X Reset
PA1
X
HS X
HSE oscillator input / [USART1
X Port A2 transmit] / [SPI1 master in- slave
out] /
X
X
HS X
HSE oscillator output / [USART1
X Port A3 receive]/ [SPI1 master out/slave
in]/
X
X
HS X
Timer 2 - break input /
X Port A4 LCD COM 0 / ADC1 input 2 /
Comparator 1 positive input
I/O
X
X
X
HS X
Timer 2 - break input /
[Timer 2 - trigger] / LCD_COM 0 /
X Port A4
ADC1 input 2 /
Comparator 1 positive input
-
PA5/TIM3_BKIN/
LCD_COM1(2)/ADC1_IN1/ I/O
COMP1_INP
X
X
X
HS X
Timer 3 - break input /
X Port A5 LCD_COM 1 / ADC1 input 1/
Comparator 1 positive input
5
PA5/TIM3_BKIN/
[TIM3_TRIG](3)/
5
I/O
LCD_COM1(2)/ADC1_IN1/
COMP1_INP
X
X
X
HS X
Timer 3 - break input / [Timer 3 trigger] / LCD_COM 1 /
X Port A5
ADC1 input 1 /
Comparator 1 positive input
6
PA6/[ADC1_TRIG](3)/
- LCD_COM2(2)/ADC1_IN0/ I/O
COMP1_INP
X
X
X
HS X
[ADC1 - trigger] / LCD_COM2 /
X Port A6 ADC1 input 0 /
Comparator 1 positive input
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Pin description
STM8L15x pin description (continued)
X
HS X
X Port A7 LCD segment 0
PB0/TIM2_CH1/
I/O
24 13 12 LCD_SEG10(2)/
ADC1_IN18/COMP1_INP
X
X
X
HS X
Timer 2 - channel 1 / LCD
X Port B0 segment 10 / ADC1_IN18 /
Comparator 1 positive input
PB1/TIM3_CH1/
25 14 13 LCD_SEG11(2)/
I/O
ADC1_IN17/COMP1_INP
X
X
X
HS X
Timer 3 - channel 1 / LCD
X Port B1 segment 11 / ADC1_IN17 /
Comparator 1 positive input
PB2/ TIM2_CH2/
26 15 14 LCD_SEG12(2)/
I/O
ADC1_IN16/COMP1_INP
X
X
X
HS X
Timer 2 - channel 2 / LCD
X Port B2 segment 12 / ADC1_IN16/
Comparator 1 positive input
-
PB3/TIM2_TRIG/
- LCD_SEG13(2)/
I/O
ADC1_IN15/COMP1_INP
X
X
X
HS X
Timer 2 - trigger / LCD segment
X Port B3 13 /ADC1_IN15 / Comparator 1
positive input
16
PB3/[TIM2_TRIG](3)/
TIM1_CH2N/LCD_SEG13
- (2)
I/O
/ADC1_IN15/
COMP1_INP
HS X
[Timer 2 - trigger] / Timer 1
inverted channel 2 / LCD
X Port B3
segment 13 / ADC1_IN15 /
Comparator 1 positive input
-
PB3/[TIM2_TRIG](3)/
TIM1_CH1N/
I/O
15 LCD_SEG13(2)/
ADC1_IN15/RTC_ALARM
/COMP1_INP
X
X
X
HS X
[Timer 2 - trigger] / Timer 1
inverted channel 1/ LCD segment
X Port B3 13 / ADC1_IN15 /
RTC alarm/ Comparator 1
positive input
-
PB4/[SPI1_NSS](3)/
- LCD_SEG14(2)/
I/O
ADC1_IN14/COMP1_INP
X
X
X
HS X
[SPI1 master/slave select] / LCD
X Port B4 segment 14 / ADC1_IN14 /
Comparator 1 positive input
27
-
-
28
-
29
-
PB4/[SPI1_NSS](3)/
LCD_SEG14(2)/
17 16
ADC1_IN14/
COMP1_INP/DAC_OUT
-
X
X
Default alternate function
I/O
X
X
X
HS X
[SPI1 master/slave select] / LCD
segment 14 / ADC1_IN14 /
X Port B4
DAC output /
Comparator 1 positive input
PB5/[SPI1_SCK](3)/
I/O
- LCD_SEG15(2)/
ADC1_IN13/COMP1_INP
X
X
X
HS X
[SPI1 clock] / LCD segment 15 /
X Port B5 ADC1_IN13 / Comparator 1
positive input
X
X
X
HS X
[SPI1 clock] / LCD segment 15 /
X Port B5 ADC1_IN13 / DAC output/
Comparator 1 positive input
PB5/[SPI1_SCK](3)/
LCD_SEG15(2)/
18 17
ADC1_IN13/DAC_OUT/
COMP1_INP
26/101
X
PP
X
I/O FT
OD
X
Pin name
Type
Ext. interrupt
- PA7/LCD_SEG0(2)
wpu
WFQFPN28
-
Output
floating
WFQFPN32
8
I/O level
VFQFPN48 and LQFP48
Input
Main function
(after reset)
Pin
number
High sink/source
Table 4.
STM8L151xx, STM8L152xx
I/O
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
STM8L15x pin description (continued)
X
Main function
(after reset)
X
PP
Ext. interrupt
X
OD
wpu
Output
floating
-
PB6/[SPI1_MOSI](3)/
- LCD_SEG16(2)/
I/O
ADC1_IN12/COMP1_INP
Pin name
I/O level
Type
WFQFPN28
30
Input
WFQFPN32
VFQFPN48 and LQFP48
Pin
number
High sink/source
Table 4.
Pin description
Default alternate function
HS X
[SPI1 master out/slave in]/
X Port B6 LCD segment 16 / ADC1_IN12 /
Comparator 1 positive input
PB6/[SPI1_MOSI](3)/
LCD_SEG16(2)/
19 18
I/O
ADC1_IN12/COMP1_INP/
DAC_OUT
X
X
X
HS X
[SPI1 master out]/
slave in / LCD segment 16 /
X Port B6
ADC1_IN12 / DAC output /
Comparator 1 positive input
PB7/[SPI1_MISO](3)/
I/O
31 20 19 LCD_SEG17(2)/
ADC1_IN11/COMP1_INP
X
X
X
HS X
[SPI1 master in- slave out] /
X Port B7 LCD segment 17 / ADC1_IN11 /
Comparator 1 positive input
37 25 21 PC0/I2C1_SDA
I/O FT
X
X
T(4)
Port C0 I2C1 data
38 26 22 PC1/I2C1_SCL
I/O FT
X
X
T(4)
Port C1 I2C1 clock
-
PC2/[USART1_RX](3)/
41 27 23 LCD_SEG22/ADC1_IN6/ I/O
COMP1_INP/VREF_OUT
PC3/[USART1_TX](3)/
LCD_SEG23(2)/
42 28 24
ADC1_IN5/COMP1_INP/
COMP2_INM
I/O
X
X
X
X
X
X
HS X
[USART1 receive] /
LCD segment 22 / ADC1_IN6 /
X Port C2
Comparator 1 positive input /
Voltage reference output
HS X
[USART1 transmit] /
LCD segment 23 / ADC1_IN5 /
X Port C3
Comparator 1 positive input /
Comparator 2 negative input
PC4/[USART1_CK](3)/
I2C1_SMB/CCO/
I/O
43 29 25 LCD_SEG24(2)/
ADC1_IN4/COMP2_INM/
COMP1_INP
X
X
X
HS X
[USART1 synchronous clock] /
I2C1_SMB / Configurable clock
output / LCD segment 24 /
X Port C4
ADC1_IN4 /
Comparator 2 negative input /
Comparator 1 positive input
PC5/OSC32_IN
44 30 26 /[SPI1_NSS](3)/
[USART1_TX](3)
I/O
X
X
X
HS X
LSE oscillator input / [SPI1
X Port C5 master/slave select] / [USART1
transmit]
PC6/OSC32_OUT/
45 31 27 [SPI1_SCK](3)/
[USART1_RX](3)
I/O
X
X
X
HS X
X Port C6
PC7/LCD_SEG25(2)/
- ADC1_IN3/COMP2_INM/ I/O
COMP1_INP
X
X
X
HS X
LCD segment 25 /ADC1_IN3/
X Port C7 Comparator negative input /
Comparator 1 positive input
46
-
Doc ID 15962 Rev 2
LSE oscillator output / [SPI1
clock] / [USART1 receive]
27/101
Pin description
STM8L15x pin description (continued)
X
X
PD2/TIM1_CH1
I/O
22 11 10 /LCD_SEG8(2)/
ADC1_IN20/COMP1_INP
X
X
-
23 12
PD3/ TIM1_TRIG/
- LCD_SEG9(2)/ADC1_IN1
9/COMP1_INP
PD3/ TIM1_TRIG/
LCD_SEG9(2)/
11 ADC1_IN19/TIM1_BKIN/
COMP1_INP/
RTC_CALIB
I/O
X
X
Main function
(after reset)
-
PD1/TIM1_CH3/[TIM3_TR
IG](3)/LCD_COM3(2)/
9
I/O
ADC1_IN21/COMP2_INP/
COMP1_INP
-
X
PP
10
PD1/TIM1_CH3N/[TIM3_T
RIG](3)/ LCD_COM3(2)/
I/O
ADC1_IN21/COMP2_INP/
COMP1_INP
21
X
OD
-
PD1/TIM3_TRIG/
LCD_COM3(2)/
I/O
ADC1_IN21/COMP2_INP/
COMP1_INP
-
I/O
wpu
9
PD0/TIM3_CH2/
[ADC1_TRIG](3)/
I/O
ADC1_IN22/COMP2_INP/
COMP1_INP
20
floating
-
PD0/TIM3_CH2/
[ADC1_TRIG](3)/
8 LCD_SEG7(2)/ADC1_IN2
2/COMP2_INP/
COMP1_INP
Pin name
Output
High sink/source
I/O level
WFQFPN28
Type
Input
WFQFPN32
VFQFPN48 and LQFP48
Pin
number
Ext. interrupt
Table 4.
STM8L151xx, STM8L152xx
Default alternate function
HS X
Timer 3 - channel 2 /
[ADC1_Trigger] / LCD segment 7
X Port D0 / ADC1_IN22 / Comparator 2
positive input / Comparator 1
positive input
HS X
Port
X
D0(5)
HS X
Timer 3 - trigger / LCD_COM3 /
ADC1_IN21 / comparator 2
X Port D1
positive input / Comparator 1
positive input
HS X
[Timer 3 - trigger]/ TIM1 inverted
channel 3 / LCD_COM3/
X Port D1 ADC1_IN21 / Comparator 2
positive input / Comparator 1
positive input
X
HS X
Timer 1 channel 3 / [Timer 3 trigger] / LCD_COM3/
X Port D1 ADC1_IN21 / Comparator 2
positive input / Comparator 1
positive input
X
X
HS X
Timer 1 - channel 1 / LCD
X Port D2 segment 8 / ADC1_IN20 /
Comparator 1 positive input
X
X
HS X
Timer 1 - trigger / LCD segment 9
X Port D3 / ADC1_IN19 / Comparator 1
positive input
X
X
X
X
X
X
X
X
Timer 3 - channel 2 /
[ADC1_Trigger] / ADC1_IN22 /
Comparator 2 positive input /
Comparator 1 positive input
I/O
X
X
X
HS X
Timer 1 - trigger / LCD segment 9
/ ADC1_IN19 / Timer 1 break
X Port D3
input / RTC calibration /
Comparator 1 positive input
PD4/TIM1_CH2
I/O
33 21 20 /LCD_SEG18(2)/
ADC1_IN10/COMP1_INP
X
X
X
HS X
Timer 1 - channel 2 / LCD
X Port D4 segment 18 / ADC1_IN10/
Comparator 1 positive input
-
-
28/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
STM8L15x pin description (continued)
35 23
PD6/TIM1_BKIN
/LCD_SEG20(2)/
- ADC1_IN8/RTC_CALIB/
VREF_OUT/
COMP1_INP
36 24
PD7/TIM1_CH1N
/LCD_SEG21(2)/
- ADC1_IN7/RTC_ALARM/ I/O
VREF_OUT/
COMP1_INP
X
X
14
-
- PE0/LCD_SEG1(2)
I/O FT
X
15
-
-
PE1/TIM1_CH2N
/LCD_SEG2(2)
I/O
16
-
-
PE2/TIM1_CH3N
/LCD_SEG3(2)
17
-
Main function
(after reset)
X
PP
Ext. interrupt
X
PD5/TIM1_CH3
- /LCD_SEG19(2)/
ADC1_IN9/COMP1_INP
OD
wpu
X
34 22
18
Output
floating
I/O level
Pin name
Type
Input
WFQFPN28
WFQFPN32
VFQFPN48 and LQFP48
Pin
number
High sink/source
Table 4.
Pin description
Default alternate function
HS X
Timer 1 - channel 3 / LCD
X Port D5 segment 19 / ADC1_IN9/
Comparator 1 positive input
HS X
Timer 1 - break input / LCD
segment 20 / ADC1_IN8 / RTC
X Port D6 calibration / Voltage reference
output / Comparator 1 positive
input
X
HS X
Timer 1 - inverted channel 1/
LCD segment 21 / ADC1_IN7 /
X Port D7 RTC alarm / Voltage reference
output /Comparator 1 positive
input
X
X
HS X
X Port E0
LCD segment 1
X
X
X
HS X
X Port E1
Timer 1 - inverted channel 2 /
LCD segment 2
I/O
X
X
X
HS X
X Port E2
Timer 1 - inverted channel 3 /
LCD segment 3
- PE3/LCD_SEG4(2)
I/O
X
X
X
HS X
X Port E3
LCD segment 4
(2)
I/O
X
X
X
HS X
X Port E4
LCD segment 5
X
X
X
HS X
X Port E5
LCD segment 6 / ADC1_IN23
/ Comparator 2 positive input /
Comparator 1 positive input
- PE4/LCD_SEG5
I/O
I/O
X
X
X
PE5/LCD_SEG6(2)/
19
-
- ADC1_IN23/COMP2_INP/ I/O
COMP1_INP
47
-
-
PE6/LCD_SEG26(2)/
PVD_IN
I/O
X
X
X
HS X
X Port E6
LCD segment 26/PVD_IN
48
-
- PE7/LCD_SEG27(2)
I/O
X
X
X
HS X
X Port E7
LCD segment 27
32
-
-
PF0/ADC1_IN24/
DAC_OUT
I/O
X
X
X
HS X
X Port F0
ADC1_IN24 / DAC_OUT
13
9
- VLCD(2)
13
-
- Reserved(5)
10
-
- VDD
S
Digital power supply
11
-
- VDDA
S
Analog supply voltage
12
-
- VREF+
S
ADC1 and DAC positive voltage reference
S
LCD booster external capacitor
Reserved. Must be tied to VDD
Doc ID 15962 Rev 2
29/101
Pin description
Table 4.
STM8L151xx, STM8L152xx
STM8L15x pin description (continued)
Pin
number
6 VSS/VSSA/VREF-
S
I/O ground / Analog ground voltage /
ADC1 negative voltage reference
39
-
- VDDIO
S
IOs supply voltage
40
-
- VSSIO
S
IOs ground voltage
1
PA0/[USART1_CK](3)/
32 28
SWIM/BEEP/IR_TIM (6)
I/O
X
X
Ext. interrupt
X
HS
(6)
X
Main function
(after reset)
7
PP
9
OD
Digital power supply / Analog supply
voltage / ADC1 positive voltage reference
High sink/source
S
wpu
7 VDD/VDDA/VREF+
floating
8
I/O level
WFQFPN28
-
Pin name
Type
WFQFPN32
Output
VFQFPN48 and LQFP48
Input
X Port A0
Default alternate function
[USART1 synchronous clock](3) /
SWIM input and output /
Beep output / Infrared Timer output
1. When the PA1/NRST pin is used as general purpose (PA1), it can be configured only as output push-pull, not as a general
purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15x reference manual
(RM0031).
2. Available on STM8L152xx devices only.
3. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented).
5. Available on STM8L151xx devices only.
6. High Sink LED driver capability available on PA0.
4.1
System configuration options
As shown in Table 4: STM8L15x pin description, some alternate functions can be remapped
on different I/O ports by programming one of the two remapping registers described in the “
Routing interface (RI) and system configuration controller” section in the STM8L15xxx
reference manual (RM0031).
30/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Memory and register map
5
Memory and register map
5.1
Memory mapping
The memory map is shown in Figure 8.
Figure 8.
0x00 0000
0x00 07FF
0x00 0800
Memory map
RAM
(2 Kbytes) (1)
including
Stack
(513 bytes) (1)
Reserved
0x00 0FFF
0x00 1000
0x00 5000
Data EEPROM
(1 Kbyte)
0x00 13FF
0x00 1400
0x00 5050
0x00 5070
0x00 509E
0x00 50A0
0x00 50B0
0x00 50C0
Reserved
0x00 50D3
0x00 47FF
0x00 4800
0x00 50E0
0x00 50F3
Option bytes
0x00 5140
0x00 48FF
0x00 4900
0x00 49FF
0x00 5200
0x00 5210
Reserved
0x00 5230
0x00 5000
0x00 57FF
0x00 5800
0x00 59FF
0x00 6000
0x00 67FF
0x00 7000
0x00 5250
GPIO and peripheral registers
0x00 52B0
0x00 52E0
Reserved
0x00 52FF
0x00 5340
Boot ROM
(2 Kbytes)
0x00 5380
0x00 5400
0x00 5430
Reserved
0x00 7EFF
0x00 7F00
0x00 7FFF
0x00 8000
0x00 807F
0x00 8080
0x00 5280
0x00 5440
GPIO Ports
Flash
DMA1
SYSCFG
ITC-EXTI
RST
CLK
WWDG
IWDG
BEEP
RTC
SPI1
I2C1
USART1
TIM2
TIM3
TIM1
TIM4
IRTIM
ADC1
DAC
LCD
RI
COMP
CPU/SWIM/Debug/ITC
Registers
Reset and interrupt vectors
Medium-density
Flash program memory
(up to 32 Kbytes)
0x00 FFFF
1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.
2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.
Doc ID 15962 Rev 2
31/101
Memory and register map
Table 5.
STM8L151xx, STM8L152xx
Flash and RAM boundary addresses
Memory area
Size
Start Address
End address
RAM
2 Kbytes
0x00 0000
0x00 07FF
16 Kbytes
0x00 8000
0x00 BFFF
32 Kbytes
0x00 8000
0x00 FFFF
Flash program memory
5.2
Register map
Table 6.
I/O port hardware register map
Register label
Register name
Reset
status
0x00 5000
PA_ODR
Port A data output latch register
0x00
0x00 5001
PA_IDR
Port A input pin value register
0x00
PA_DDR
Port A data direction register
0x00
0x00 5003
PA_CR1
Port A control register 1
0x00
0x00 5004
PA_CR2
Port A control register 2
0x00
0x00 5005
PB_ODR
Port B data output latch register
0x00
0x00 5006
PB_IDR
Port B input pin value register
0x00
PB_DDR
Port B data direction register
0x00
0x00 5008
PB_CR1
Port B control register 1
0x00
0x00 5009
PB_CR2
Port B control register 2
0x00
0x00 500A
PC_ODR
Port C data output latch register
0x00
0x00 500B
PB_IDR
Port C input pin value register
0x00
PC_DDR
Port C data direction register
0x00
0x00 500D
PC_CR1
Port C control register 1
0x00
0x00 500E
PC_CR2
Port C control register 2
0x00
0x00 500F
PD_ODR
Port D data output latch register
0x00
0x00 5010
PD_IDR
Port D input pin value register
0x00
PD_DDR
Port D data direction register
0x00
0x00 5012
PD_CR1
Port D control register 1
0x00
0x00 5013
PD_CR2
Port D control register 2
0x00
0x00 5014
PE_ODR
Port E data output latch register
0x00
0x00 5015
PE_IDR
Port E input pin value register
0x00
PE_DDR
Port E data direction register
0x00
0x00 5017
PE_CR1
Port E control register 1
0x00
0x00 5018
PE_CR2
Port E control register 2
0x00
Address
0x00 5002
0x00 5007
0x00 500C
0x00 5011
0x00 5016
32/101
Block
Port A
Port B
Port C
Port D
Port E
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 6.
Memory and register map
I/O port hardware register map (continued)
Register label
Register name
Reset
status
0x00 5019
PF_ODR
Port F data output latch register
0x00
0x00 501A
PF_IDR
Port F input pin value register
0x00
PF_DDR
Port F data direction register
0x00
0x00 501C
PF_CR1
Port F control register 1
0x00
0x00 501D
PF_CR2
Port F control register 2
0x00
Address
0x00 501B
Table 7.
Block
Port F
General hardware register map
Address
Block
Register label
0x00 501E
to
0x00 5049
Register name
Reset
status
Reserved area (44 bytes)
0x00 5050
FLASH_CR1
Flash control register 1
0x00
0x00 5051
FLASH_CR2
Flash control register 2
0x00
FLASH _PUKR
Flash program memory unprotection key
register
0x00
0x00 5053
FLASH _DUKR
Data EEPROM unprotection key register
0x00
0x00 5054
FLASH _IAPSR
Flash in-application programming status
register
0x00
0x00 5052
0x00 5065
to
0x00 506F
Flash
Reserved area (11 bytes)
Doc ID 15962 Rev 2
33/101
Memory and register map
Table 7.
STM8L151xx, STM8L152xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5070
DMA1_GCSR
DMA1 global configuration & status
register
0xFC
0x00 5071
DMA1_GIR1
DMA1 global interrupt register 1
0x00
Address
Block
0x00 5072 to
0x00 5074
Reserved area (3 bytes)
0x00 5075
DMA1_C0CR
DMA1 channel 0 configuration register
0x00
0x00 5076
DMA1_C0SPR
DMA1 channel 0 status & priority register
0x00
0x00 5077
DMA1_C0NDTR
DMA1 number of data to transfer register
(channel 0)
0x00
0x00 5078
DMA1_C0PARH
DMA1 peripheral address high register
(channel 0)
0x52
0x00 5079
DMA1_C0PARL
DMA1 peripheral address low register
(channel 0)
0x00
0x00 507A
Reserved area (1 byte)
DMA1
0x00 507B
DMA1_C0M0ARH
DMA1 memory 0 address high register
(channel 0)
0x00
0x00 507C
DMA1_C0M0ARL
DMA1 memory 0 address low register
(channel 0)
0x00
0x00 507D to
0x00 507E
Reserved area (2 bytes)
0x00 507F
DMA1_C1CR
DMA1 channel 1 configuration register
0x00
0x00 5080
DMA1_C1SPR
DMA1 channel 1 status & priority register
0x00
0x00 5081
DMA1_C1NDTR
DMA1 number of data to transfer register
(channel 1)
0x00
0x00 5082
DMA1_C1PARH
DMA1 peripheral address high register
(channel 1)
0x52
0x00 5083
DMA1_C1PARL
DMA1 peripheral address low register
(channel 1)
0x00
34/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 7.
Memory and register map
General hardware register map (continued)
Address
Block
Register label
0x00 5084
Register name
Reset
status
Reserved area (1 byte)
0x00 5085
DMA1_C1M0ARH
DMA1 memory 0 address high register
(channel 1)
0x00
0x00 5086
DMA1_C1M0ARL
DMA1 memory 0 address low register
(channel 1)
0x00
0x00 5087
0x00 5088
Reserved area (2 bytes)
0x00 5089
DMA1_C2CR
DMA1 channel 2 configuration register
0x00
0x00 508A
DMA1_C2SPR
DMA1 channel 2 status & priority register
0x00
0x00 508B
DMA1_C2NDTR
DMA1 number of data to transfer register
(channel 2)
0x00
0x00 508C
DMA1_C2PARH
DMA1 peripheral address high register
(channel 2)
0x52
0x00 508D
DMA1_C2PARL
DMA1 peripheral address low register
(channel 2)
0x00
0x00 508E
Reserved area (1 byte)
0x00 508F
DMA1_C2M0ARH
DMA1 memory 0 address high register
(channel 2)
0x00
DMA1_C2M0ARL
DMA1 memory 0 address low register
(channel 2)
0x00
DMA1
0x00 5090
0x00 5091
0x00 5092
Reserved area (2 bytes)
0x00 5093
DMA1_C3CR
DMA1 channel 3 configuration register
0x00
0x00 5094
DMA1_C3SPR
DMA1 channel 3 status & priority register
0x00
0x00 5095
DMA1_C3NDTR
DMA1 number of data to transfer register
(channel 3)
0x00
0x00 5096
DMA1_C3PARH_
C3M1ARH
DMA1 peripheral address high register
(channel 3)
0x40
0x00 5097
DMA1_C3PARL_
C3M1ARL
DMA1 peripheral address low register
(channel 3)
0x00
0x00 5098
Reserved area (1 byte)
0x00 5099
DMA1_C3M0ARH
DMA1 memory 0 address high register
(channel 3)
0x00
0x00 509A
DMA1_C3M0ARL
DMA1 memory 0 address low register
(channel 3)
0x00
0x00 509B to
0x00 509D
Reserved area (3 bytes)
0x00 509E
SYSCFG_RMPCR1
Remapping register 1
0x00
SYSCFG_RMPCR2
Remapping register 2
0x00
SYSCFG
0x00 509F
Doc ID 15962 Rev 2
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Memory and register map
Table 7.
STM8L151xx, STM8L152xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 50A0
EXTI_CR1
External interrupt control register 1
0x00
0x00 50A1
EXTI_CR2
External interrupt control register 2
0x00
EXTI_CR3
External interrupt control register 3
0x00
0x00 50A3
EXTI_SR1
External interrupt status register 1
0x00
0x00 50A4
EXTI_SR2
External interrupt status register 2
0x00
0x00 50A5
EXTI_CONF
External interrupt port select register
0x00
0x00 50A6
WFE_CR1
WFE control register 1
0x00
WFE_CR2
WFE control register 2
0x00
WFE_CR3
WFE control register 3
0x00
Address
Block
0x00 50A2
ITC - EXTI
0x00 50A7
WFE
0x00 50A8
0x00 50A9
to
0x00 50AF
Reserved area (7 bytes)
0x00 50B0
RST_CR
Reset control register
0x00
RST_SR
Reset status register
0x01
PWR_CSR1
Power control and status register 1
0x00
PWR_CSR2
Power control and status register 2
0x00
RST
0x00 50B1
0x00 50B2
PWR
0x00 50B3
0x00 50B4
to
0x00 50BF
Reserved area (12 bytes)
0x00 50C0
CLK_DIVR
Clock master divider register
0x03
0x00 50C1
CLK_CRTCR
Clock RTC register
0x00
0x00 50C2
CLK_ICKR
Internal clock control register
0x11
0x00 50C3
CLK_PCKENR1
Peripheral clock gating register 1
0x00
0x00 50C4
CLK_PCKENR2
Peripheral clock gating register 2
0x00
0x00 50C5
CLK_CCOR
Configurable clock control register
0x00
0x00 50C6
CLK_ECKR
External clock control register
0x00
CLK_SCSR
System clock status register
0x01
0x00 50C8
CLK_SWR
System clock switch register
0x01
0x00 50C9
CLK_SWCR
Clock switch control register
0bxxxx0000
0x00 50CA
CLK_CSSR
Clock security system register
0x00
0x00 50CB
CLK_CBEEPR
Clock BEEP register
0x00
0x00 50CC
CLK_HSICALR
HSI calibration register
0x00
0x00 50CD
CLK_HSITRIMR
HSI clock calibration trimming register
0x00
0x00 50CE
CLK_HSIUNLCKR
HSI unlock register
0x00
0x00 50CF
CLK_REGCSR
Main regulator control status register
0bxx11100x
0x00 50C7
CLK
36/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 7.
Memory and register map
General hardware register map (continued)
Address
Block
Register label
0x00 50D0
to
0x00 50D2
Register name
Reset
status
Reserved area (3 bytes)
0x00 50D3
WWDG_CR
WWDG control register
0x7F
WWDG_WR
WWDR window register
0x7F
WWDG
0x00 50D4
0x00 50D5
to
00 50DF
Reserved area (11 bytes)
0x00 50E0
0x00 50E1
IWDG
0x00 50E2
IWDG_KR
IWDG key register
0x
IWDG_PR
IWDG prescaler register
0x00
IWDG_RLR
IWDG reload register
0xFF
0x00 50E3
to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
0x00 50F2
0x00 50F3
0x00 50F4
to
0x00 513F
BEEP_CSR1
BEEP
BEEP control/status register 1
0x00
Reserved area (2 bytes)
BEEP_CSR2
BEEP control/status register 2
0x1F
Reserved area (76 bytes)
Doc ID 15962 Rev 2
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Memory and register map
Table 7.
STM8L151xx, STM8L152xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5140
RTC_TR1
Time register 1
0x00
0x00 5141
RTC_TR2
Time register 2
0x00
0x00 5142
RTC_TR3
Time register 3
0x00
Address
Block
0x00 5143
Reserved area (1 byte)
0x00 5144
RTC_DR1
Date register 1
0x00
0x00 5145
RTC_DR2
Date register 2
0x00
0x00 5146
RTC_DR3
Date register 3
0x00
0x00 5147
Reserved area (1 byte)
0x00 5148
RTC_CR1
Control register 1
0x00
0x00 5149
RTC_CR2
Control register 2
0x00
0x00 514A
RTC_CR3
Control register 3
0x00
0x00 514B
Reserved area (1 byte)
0x00 514C
RTC_ISR1
Initialization and status register 1
0x00
0x00 514D
RTC_ISR2
Initialization and Status register 2
0x00
0x00 514E
0x00 514F
Reserved area (2 bytes)
RTC
0x00 5150
RTC_SPRERH
Synchronous prescaler register high
-
0x00 5151
RTC_SPRERL
Synchronous prescaler register low
-
0x00 5152
RTC_APRER
Asynchronous prescaler register
-
0x00 5153
Reserved area (1 byte)
0x00 5154
RTC_WUTRH
Wakeup timer register high
-
0x00 5155
RTC_WUTRL
Wakeup timer register low
-
0x00 5156 to
0x00 5158
0x00 5159
Reserved area (3 bytes)
RTC_WPR
0x00 515A
0x00 515B
Write protection register
0x00
Reserved area (2 bytes)
0x00 515C
RTC_ALRMAR1
Alarm A register 1
0x00
0x00 515D
RTC_ALRMAR2
Alarm A register 2
0x00
0x00 515E
RTC_ALRMAR3
Alarm A register 3
0x00
0x00 515F
RTC_ALRMAR4
Alarm A register 4
0x00
0x00 5160 to
0x00 51FF
38/101
Reserved area (160 bytes)
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 7.
Memory and register map
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5200
SPI1_CR1
SPI1 control register 1
0x00
0x00 5201
SPI1_CR2
SPI1 control register 2
0x00
0x00 5202
SPI1_ICR
SPI1 interrupt control register
0x00
SPI1_SR
SPI1 status register
0x02
0x00 5204
SPI1_DR
SPI1 data register
0x00
0x00 5205
SPI1_CRCPR
SPI1 CRC polynomial register
0x07
0x00 5206
SPI1_RXCRCR
SPI1 Rx CRC register
0x00
0x00 5207
SPI1_TXCRCR
SPI1 Tx CRC register
0x00
Address
Block
0x00 5203
SPI1
0x00 5208
to
0x00 520F
Reserved area (8 bytes)
0x00 5210
I2C1_CR1
I2C1 control register 1
0x00
0x00 5211
I2C1_CR2
I2C1 control register 2
0x00
0x00 5212
I2C1_FREQR
I2C1 frequency register
0x00
0x00 5213
I2C1_OARL
I2C1 own address register low
0x00
0x00 5214
I2C1_OARH
I2C1 own address register high
0x00
0x00 5215
Reserved (1 byte)
0x00 5216
I2C1_DR
I2C1 data register
0x00
I2C1_SR1
I2C1 status register 1
0x00
0x00 5218
I2C1_SR2
I2C1 status register 2
0x00
0x00 5219
I2C1_SR3
I2C1 status register 3
0x0x
0x00 521A
I2C1_ITR
I2C1 interrupt control register
0x00
0x00 521B
I2C1_CCRL
I2C1 clock control register low
0x00
0x00 521C
I2C1_CCRH
I2C1 clock control register high
0x00
0x00 521D
I2C1_TRISER
I2C1 TRISE register
0x02
0x00 521E
I2C1_PECR
I2C1 packet error checking register
0x00
0x00 5217
0x00 521F
to
0x00 522F
I2C1
Reserved area (17 bytes)
Doc ID 15962 Rev 2
39/101
Memory and register map
Table 7.
STM8L151xx, STM8L152xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5230
USART1_SR
USART1 status register
0xC0
0x00 5231
USART1_DR
USART1 data register
undefined
0x00 5232
USART1_BRR1
USART1 baud rate register 1
0x00
0x00 5233
USART1_BRR2
USART1 baud rate register 2
0x00
0x00 5234
USART1_CR1
USART1 control register 1
0x00
USART1_CR2
USART1 control register 2
0x00
0x00 5236
USART1_CR3
USART1 control register 3
0x00
0x00 5237
USART1_CR4
USART1 control register 4
0x00
0x00 5238
USART1_CR5
USART1 control register 5
0x00
0x00 5239
USART1_GTR
USART1 guard time register
0x00
0x00 523A
USART1_PSCR
USART1 prescaler register
0x00
Address
0x00 5235
0x00 523B
to
0x00 524F
40/101
Block
USART1
Reserved area (21 bytes)
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 7.
Memory and register map
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5250
TIM2_CR1
TIM2 control register 1
0x00
0x00 5251
TIM2_CR2
TIM2 control register 2
0x00
0x00 5252
TIM2_SMCR
TIM2 Slave mode control register
0x00
0x00 5253
TIM2_ETR
TIM2 external trigger register
0x00
0x00 5254
TIM2_DER
TIM2 DMA1 request enable register
0x00
0x00 5255
TIM2_IER
TIM2 interrupt enable register
0x00
0x00 5256
TIM2_SR1
TIM2 status register 1
0x00
0x00 5257
TIM2_SR2
TIM2 status register 2
0x00
0x00 5258
TIM2_EGR
TIM2 event generation register
0x00
0x00 5259
TIM2_CCMR1
TIM2 capture/compare mode register 1
0x00
0x00 525A
TIM2_CCMR2
TIM2 capture/compare mode register 2
0x00
TIM2_CCER1
TIM2 capture/compare enable register 1
0x00
0x00 525C
TIM2_CNTRH
TIM2 counter high
0x00
0x00 525D
TIM2_CNTRL
TIM2 counter low
0x00
0x00 525E
TIM2_PSCR
TIM2 prescaler register
0x00
0x00 525F
TIM2_ARRH
TIM2 auto-reload register high
0xFF
0x00 5260
TIM2_ARRL
TIM2 auto-reload register low
0xFF
0x00 5261
TIM2_CCR1H
TIM2 capture/compare register 1 high
0x00
0x00 5262
TIM2_CCR1L
TIM2 capture/compare register 1 low
0x00
0x00 5263
TIM2_CCR2H
TIM2 capture/compare register 2 high
0x00
0x00 5264
TIM2_CCR2L
TIM2 capture/compare register 2 low
0x00
0x00 5265
TIM2_BKR
TIM2 break register
0x00
0x00 5266
TIM2_OISR
TIM2 output idle state register
0x00
Address
0x00 525B
0x00 5267 to
0x00 527F
Block
TIM2
Reserved area (25 bytes)
Doc ID 15962 Rev 2
41/101
Memory and register map
Table 7.
STM8L151xx, STM8L152xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5280
TIM3_CR1
TIM3 control register 1
0x00
0x00 5281
TIM3_CR2
TIM3 control register 2
0x00
0x00 5282
TIM3_SMCR
TIM3 Slave mode control register
0x00
0x00 5283
TIM3_ETR
TIM3 external trigger register
0x00
0x00 5284
TIM3_DER
TIM3 DMA1 request enable register
0x00
0x00 5285
TIM3_IER
TIM3 interrupt enable register
0x00
0x00 5286
TIM3_SR1
TIM3 status register 1
0x00
0x00 5287
TIM3_SR2
TIM3 status register 2
0x00
0x00 5288
TIM3_EGR
TIM3 event generation register
0x00
0x00 5289
TIM3_CCMR1
TIM3 Capture/Compare mode register 1
0x00
0x00 528A
TIM3_CCMR2
TIM3 Capture/Compare mode register 2
0x00
TIM3_CCER1
TIM3 Capture/Compare enable register 1
0x00
0x00 528C
TIM3_CNTRH
TIM3 counter high
0x00
0x00 528D
TIM3_CNTRL
TIM3 counter low
0x00
0x00 528E
TIM3_PSCR
TIM3 prescaler register
0x00
0x00 528F
TIM3_ARRH
TIM3 Auto-reload register high
0xFF
0x00 5290
TIM3_ARRL
TIM3 Auto-reload register low
0xFF
0x00 5291
TIM3_CCR1H
TIM3 Capture/Compare register 1 high
0x00
0x00 5292
TIM3_CCR1L
TIM3 Capture/Compare register 1 low
0x00
0x00 5293
TIM3_CCR2H
TIM3 Capture/Compare register 2 high
0x00
0x00 5294
TIM3_CCR2L
TIM3 Capture/Compare register 2 low
0x00
0x00 5295
TIM3_BKR
TIM3 break register
0x00
0x00 5296
TIM3_OISR
TIM3 output idle state register
0x00
Address
0x00 528B
0x00 5297 to
0x00 52AF
42/101
Block
TIM3
Reserved area (25 bytes)
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 7.
Memory and register map
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 52B0
TIM1_CR1
TIM1 control register 1
0x00
0x00 52B1
TIM1_CR2
TIM1 control register 2
0x00
0x00 52B2
TIM1_SMCR
TIM1 Slave mode control register
0x00
0x00 52B3
TIM1_ETR
TIM1 external trigger register
0x00
0x00 52B4
TIM1_DER
TIM1 DMA1 request enable register
0x00
0x00 52B5
TIM1_IER
TIM1 Interrupt enable register
0x00
0x00 52B6
TIM1_SR1
TIM1 status register 1
0x00
0x00 52B7
TIM1_SR2
TIM1 status register 2
0x00
0x00 52B8
TIM1_EGR
TIM1 event generation register
0x00
0x00 52B9
TIM1_CCMR1
TIM1 Capture/Compare mode register 1
0x00
0x00 52BA
TIM1_CCMR2
TIM1 Capture/Compare mode register 2
0x00
0x00 52BB
TIM1_CCMR3
TIM1 Capture/Compare mode register 3
0x00
0x00 52BC
TIM1_CCMR4
TIM1 Capture/Compare mode register 4
0x00
0x00 52BD
TIM1_CCER1
TIM1 Capture/Compare enable register 1
0x00
0x00 52BE
TIM1_CCER2
TIM1 Capture/Compare enable register 2
0x00
0x00 52BF
TIM1_CNTRH
TIM1 counter high
0x00
TIM1_CNTRL
TIM1 counter low
0x00
0x00 52C1
TIM1_PSCRH
TIM1 prescaler register high
0x00
0x00 52C2
TIM1_PSCRL
TIM1 prescaler register low
0x00
0x00 52C3
TIM1_ARRH
TIM1 Auto-reload register high
0xFF
0x00 52C4
TIM1_ARRL
TIM1 Auto-reload register low
0xFF
0x00 52C5
TIM1_RCR
TIM1 Repetition counter register
0x00
0x00 52C6
TIM1_CCR1H
TIM1 Capture/Compare register 1 high
0x00
0x00 52C7
TIM1_CCR1L
TIM1 Capture/Compare register 1 low
0x00
0x00 52C8
TIM1_CCR2H
TIM1 Capture/Compare register 2 high
0x00
0x00 52C9
TIM1_CCR2L
TIM1 Capture/Compare register 2 low
0x00
0x00 52CA
TIM1_CCR3H
TIM1 Capture/Compare register 3 high
0x00
0x00 52CB
TIM1_CCR3L
TIM1 Capture/Compare register 3 low
0x00
0x00 52CC
TIM1_CCR4H
TIM1 Capture/Compare register 4 high
0x00
0x00 52CD
TIM1_CCR4L
TIM1 Capture/Compare register 4 low
0x00
0x00 52CE
TIM1_BKR
TIM1 break register
0x00
0x00 52CF
TIM1_DTR
TIM1 dead-time register
0x00
0x00 52D0
TIM1_OISR
TIM1 output idle state register
0x00
0x00 52D1
TIM1_DCR1
DMA1 control register 1
Address
Block
0x00 52C0
TIM1
Doc ID 15962 Rev 2
43/101
Memory and register map
Table 7.
STM8L151xx, STM8L152xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 52D2
TIM1_DCR2
TIM1 DMA1 control register 2
0x00
0x00 52D3
TIM1_DMA1R
TIM1 DMA1 address for burst mode
0x00
Address
Block
0x00 52D4
to
0x00 52DF
Reserved area (12 bytes)
0x00 52E0
TIM4_CR1
TIM4 control register 1
0x00
0x00 52E1
TIM4_CR2
TIM4 control register 2
0x00
0x00 52E2
TIM4_SMCR
TIM4 Slave mode control register
0x00
0x00 52E3
TIM4_DER
TIM4 DMA1 request enable register
0x00
TIM4_IER
TIM4 Interrupt enable register
0x00
0x00 52E5
TIM4_SR1
TIM4 status register 1
0x00
0x00 52E6
TIM4_EGR
TIM4 Event generation register
0x00
0x00 52E7
TIM4_CNTR
TIM4 counter
0x00
0x00 52E8
TIM4_PSCR
TIM4 prescaler register
0x00
0x00 52E9
TIM4_ARR
TIM4 Auto-reload register
0x00
0x00 52E4
TIM4
0x00 52EA
to
0x00 52FE
0x00 52FF
Reserved area (21 bytes)
IRTIM
IR_CR
0x00 5300
to
0x00 533F
Infrared control register
0x00
Reserved area (64 bytes)
0x00 5340
ADC1_CR1
ADC1 configuration register 1
0x00
0x00 5341
ADC1_CR2
ADC1 configuration register 2
0x00
0x00 5342
ADC1_CR3
ADC1 configuration register 3
0x1F
0x00 5343
ADC1_SR
ADC1 status register
0x00
0x00 5344
ADC1_DRH
ADC1 data register high
0x00
0x00 5345
ADC1_DRL
ADC1 data register low
0x00
ADC1_HTRH
ADC1 high threshold register high
0x0F
0x00 5347
ADC1_HTRL
ADC1 high threshold register low
0xFF
0x00 5348
ADC1_LTRH
ADC1 low threshold register high
0x00
0x00 5349
ADC1_LTRL
ADC1 low threshold register low
0x00
0x00 534A
ADC1_SQR1
ADC1 channel sequence 1 register
0x00
0x00 534B
ADC1_SQR2
ADC1 channel sequence 2 register
0x00
0x00 534C
ADC1_SQR3
ADC1 channel sequence 3 register
0x00
0x00 534D
ADC1_SQR4
ADC1 channel sequence 4 register
0x00
0x00 5346
ADC1
44/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 7.
Memory and register map
General hardware register map (continued)
Register label
Register name
Reset
status
ADC1_TRIGR1
ADC1 trigger disable 1
0x00
ADC1_TRIGR2
ADC1 trigger disable 2
0x00
0x00 5350
ADC1_TRIGR3
ADC1 trigger disable 3
0x00
0x00 5351
ADC1_TRIGR4
ADC1 trigger disable 4
0x00
Address
Block
0x00 534E
0x00 534F
ADC1
0x00 5352 to
0x00 537F
Reserved area (46 bytes)
0x00 5380
DAC_CR1
DAC control register 1
0x00
0x00 5381
DAC_CR2
DAC control register 2
0x00
0x00 5382
to 0x00 5383
Reserved area (2 bytes)
0x00 5384
DAC_SWTRIGR
DAC software trigger register
0x00
0x00 5385
DAC_SR
DAC status register
0x00
0x00 5386 to
0x00 5387
Reserved area (2 bytes)
0x00 5388
0x00 5389
DAC_RDHRH
DAC right aligned data holding register
high
0x00
DAC_RDHRL
DAC right aligned data holding register low
0x00
DAC
0x00 538A to
0x00 538B
Reserved area (2 bytes)
0x00 538C
DAC_LDHRH
DAC left aligned data holding register high
0x00
0x00 538D
DAC_LDHRL
DAC left aligned data holding register low
0x00
0x00 538E
to 0x00 538F
0x00 5390
Reserved area (2 bytes)
DAC_DHR8
0x00 5391 to
0x00 53AB
DAC 8-bit data holding register
0x00
Reserved area (27 bytes)
0x00 53AC
DAC_DORH
DAC data output register high
0x00
0x00 53AD
DAC_DORL
DAC data output register low
0x00
0x00 53AE to
0x00 53FF
Reserved area (82 bytes)
Doc ID 15962 Rev 2
45/101
Memory and register map
Table 7.
STM8L151xx, STM8L152xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5400
LCD_CR1
LCD control register 1
0x00
0x00 5401
LCD_CR2
LCD control register 2
0x00
0x00 5402
LCD_CR3
LCD control register 3
0x00
LCD_FRQ
LCD frequency selection register
0x00
0x00 5404
LCD_PM0
LCD Port mask register 0
0x00
0x00 5405
LCD_PM1
LCD Port mask register 1
0x00
0x00 5406
LCD_PM2
LCD Port mask register 2
0x00
0x00 5407
LCD_PM3
LCD Port mask register 3
0x00
Address
Block
0x00 5403
LCD
0x00 5408 to
0x00 540B
Reserved area (4 bytes)
0x00 540C
LCD_RAM0
LCD display memory 0
0x00
0x00 540D
LCD_RAM1
LCD display memory 1
0x00
0x00 540E
LCD_RAM2
LCD display memory 2
0x00
0x00 540F
LCD_RAM3
LCD display memory 3
0x00
0x00 5410
LCD_RAM4
LCD display memory 4
0x00
LCD_RAM5
LCD display memory 5
0x00
LCD_RAM6
LCD display memory 6
0x00
0x00 5413
LCD_RAM7
LCD display memory 7
0x00
0x00 5414
LCD_RAM8
LCD display memory 8
0x00
0x00 5415
LCD_RAM9
LCD display memory 9
0x00
0x00 5416
LCD_RAM10
LCD display memory 10
0x00
0x00 5417
LCD_RAM11
LCD display memory 11
0x00
0x00 5418
LCD_RAM12
LCD display memory 12
0x00
0x00 5419
LCD_RAM13
LCD display memory 13
0x00
0x00 5411
0x00 5412
0x00 541A to
0x00 542F
46/101
LCD
Reserved area (22 bytes)
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 7.
Memory and register map
General hardware register map (continued)
Address
Block
Register label
0x00 5430
Register name
Reserved area (1 byte)
Reset
status
0x00
0x00 5431
RI_ICR1
Timer input capture routing register 1
0x00
0x00 5432
RI_ICR2
Timer input capture routing register 2
0x00
0x00 5433
RI_IOIR1
I/O input register 1
undefined
0x00 5434
RI_IOIR2
I/O input register 2
undefined
0x00 5435
RI_IOIR3
I/O input register 3
undefined
0x00 5436
RI_IOCMR1
I/O control mode register 1
0x00
RI_IOCMR3
I/O control mode register 2
0x00
0x00 5438
RI_IOCMR3
I/O control mode register 3
0x00
0x00 5439
RI_IOSR1
I/O switch register 1
0x00
0x00 543A
RI_IOSR2
I/O switch register 2
0x00
0x00 543B
RI_IOSR3
I/O switch register 3
0x00
0x00 5437
RI
0x00 543C
Reserved area (1 byte)
0x3F
0x00 543D
RI_ASCR1
Analog switch register 1
0x00
0x00 543E
RI_ASCR2
Analog switch register 2
0x00
0x00 543F
RI_RCR
Resistor control register 1
0x00
0x00 5440
COMP_CSR1
Comparator control and status register 1
0x00
0x00 5441
COMP_CSR2
Comparator control and status register 2
0x00
COMP_CSR3
Comparator control and status register 3
0x00
0x00 5443
COMP_CSR4
Comparator control and status register 4
0x00
0x00 5444
COMP_CSR5
Comparator control and status register 5
0x00
0x00 5442
COMP
Doc ID 15962 Rev 2
47/101
Memory and register map
Table 8.
STM8L151xx, STM8L152xx
CPU/SWIM/debug module/interrupt controller registers
Register Label
Register Name
Reset
Status
0x00 7F00
A
Accumulator
0x00
0x00 7F01
PCE
Program counter extended
0x00
0x00 7F02
PCH
Program counter high
0x00
0x00 7F03
PCL
Program counter low
0x00
XH
X index register high
0x00
XL
X index register low
0x00
0x00 7F06
YH
Y index register high
0x00
0x00 7F07
YL
Y index register low
0x00
0x00 7F08
SPH
Stack pointer high
0x03
0x00 7F09
SPL
Stack pointer low
0xFF
0x00 7F0A
CCR
Condition code register
0x28
Address
Block
0x00 7F04
0x00 7F05
0x00 7F0B to
0x00 7F5F
CPU(1)
Reserved area (85 bytes)
CPU
0x00 7F60
CFG_GCR
Global configuration register
0x00
0x00 7F70
ITC_SPR1
Interrupt Software priority register 1
0xFF
0x00 7F71
ITC_SPR2
Interrupt Software priority register 2
0xFF
0x00 7F72
ITC_SPR3
Interrupt Software priority register 3
0xFF
ITC_SPR4
Interrupt Software priority register 4
0xFF
0x00 7F74
ITC_SPR5
Interrupt Software priority register 5
0xFF
0x00 7F75
ITC_SPR6
Interrupt Software priority register 6
0xFF
0x00 7F76
ITC_SPR7
Interrupt Software priority register 7
0xFF
0x00 7F77
ITC_SPR8
Interrupt Software priority register 8
0xFF
0x00 7F73
ITC-SPR
0x00 7F78
to
0x00 7F79
0x00 7F80
0x00 7F81
to
0x00 7F8F
48/101
Reserved area (2 bytes)
SWIM
SWIM_CSR
SWIM control status register
Reserved area (15 bytes)
Doc ID 15962 Rev 2
0x00
STM8L151xx, STM8L152xx
Table 8.
Memory and register map
CPU/SWIM/debug module/interrupt controller registers (continued)
Register Label
Register Name
Reset
Status
0x00 7F90
DM_BK1RE
DM breakpoint 1 register extended byte
0xFF
0x00 7F91
DM_BK1RH
DM breakpoint 1 register high byte
0xFF
0x00 7F92
DM_BK1RL
DM breakpoint 1 register low byte
0xFF
0x00 7F93
DM_BK2RE
DM breakpoint 2 register extended byte
0xFF
0x00 7F94
DM_BK2RH
DM breakpoint 2 register high byte
0xFF
DM_BK2RL
DM breakpoint 2 register low byte
0xFF
0x00 7F96
DM_CR1
DM Debug module control register 1
0x00
0x00 7F97
DM_CR2
DM Debug module control register 2
0x00
0x00 7F98
DM_CSR1
DM Debug module control/status register 1
0x10
0x00 7F99
DM_CSR2
DM Debug module control/status register 2
0x00
0x00 7F9A
DM_ENFCTR
DM enable function register
0xFF
Address
0x00 7F95
Block
DM
0x00 7F9B
to
0x00 7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
Doc ID 15962 Rev 2
49/101
Interrupt vector mapping
STM8L151xx, STM8L152xx
6
Interrupt vector mapping
Table 9.
Interrupt mapping
IRQ
No.
Source
block
RESET
1
2
Description
Reset
Wakeup
from Halt
mode
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)(1)
Yes
Yes
Yes
Yes
0x00 8000
0x00 8004
Vector
address
TRAP
Software interrupt
-
-
-
-
FLASH
EOP/WR_PG_DIS
-
-
Yes
Yes(2)
0x00 800C
Yes
Yes
(2)
0x00 8010
0x00 8014
DMA1 0/1
DMA1 channels 0/1
-
-
3
DMA1 2/3
DMA1 channels 2/3
-
-
Yes
Yes(2)
4
RTC
RTC alarm interrupt
Yes
Yes
Yes
Yes
0x00 8018
Yes
Yes
Yes
Yes(2)
0x00 801C
Yes
Yes
Yes
Yes(2)
0x00 8020
Yes
Yes(2)
0x00 8024
Yes
Yes
(2)
0x00 8028
(2)
0x00 802C
5
6
7
8
EXTI
PortE/F interrupt/PVD
E/F/PVD(3) interrupt
EXTIB
EXTID
EXTI0
External interrupt port B
External interrupt port D
External interrupt 0
Yes
Yes
Yes
Yes
9
EXTI1
External interrupt 1
Yes
Yes
Yes
Yes
10
EXTI2
External interrupt 2
Yes
Yes
Yes
Yes(2)
0x00 8030
Yes
Yes
(2)
0x00 8034
Yes
Yes
(2)
0x00 8038
0x00 803C
11
12
EXTI3
EXTI4
External interrupt 3
External interrupt 4
Yes
Yes
Yes
Yes
13
EXTI5
External interrupt 5
Yes
Yes
Yes
Yes(2)
14
EXTI6
External interrupt 6
Yes
Yes
Yes
Yes(2)
0x00 8040
(2)
0x00 8044
15
EXTI7
Yes
Yes
Yes
16
LCD
-
-
Yes
Yes
0x00 8048
17
CLK/
TIM1/
DAC
System clock switch/CSS
interrupt/TIM1 Break/DAC
-
-
Yes
Yes
0x00 804C
18
COMP
/ADC1
Comparator
interrupt/ADC1
Yes
Yes
Yes
Yes(2)
0x00 8050
19
TIM2
Update
/Overflow/Trigger/Break
-
-
Yes
Yes(2)
0x00 8054
20
TIM2
Capture/Compare
-
-
Yes
Yes(2)
0x00 8058
21
TIM3
Update
/Overflow/Trigger/Break
-
-
Yes
Yes(2)
0x00 805C
22
TIM3
Capture/Compare
-
-
Yes
Yes(2)
0x00 8060
23
TIM1
Update /Overflow/Trigger/
COM
-
-
-
Yes(2)
0x00 8064
24
TIM1
Capture/Compare
-
-
-
Yes(2)
0x00 8068
50/101
External interrupt 7
LCD interrupt
Doc ID 15962 Rev 2
Yes
STM8L151xx, STM8L152xx
Table 9.
Interrupt vector mapping
Interrupt mapping (continued)
IRQ
No.
Source
block
25
TIM4
26
SPI1
27
USART 1
28
USART 1
29
I2C1
Description
Update/overflow/trigger
Wakeup
from Halt
mode
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)(1)
-
-
Yes
Yes(2)
0x00 806C
0x00 8070
Vector
address
Yes
Yes
Yes
Yes(2)
Transmission
complete/transmit data
register empty
-
-
Yes
Yes(2)
0x00 8074
Receive Register Data
full/overrun/idle line
detected/parity error
-
-
Yes
Yes(2)
0x00 8078
Yes
Yes
Yes
Yes(2)
0x00 807C
End of Transfer
I2C1 interrupt(4)
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode.
2. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes
back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
3. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).
4. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
Doc ID 15962 Rev 2
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Option bytes
7
STM8L151xx, STM8L152xx
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 10 for details on option byte addresses.
The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP, UBC and PCODESIZE values which can only be taken into account when they are
modified in ICP mode (with the SWIM).
Refer to the STM8L15x Flash programming manual (PM0051) and STM8 SWIM and Debug
Manual (UM0320) for information on SWIM programming procedures.
Table 10.
Addr.
Option byte addresses
Option name
Option
byte
No.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
00 4800
Read-out
protection
(ROP)
OPT1
ROP[7:0]
0x00
00 4802
UBC(User
Boot code size)
OPT3
UBC[7:0]
0x00
00 4807
PCODESIZE
OPT8
PCODE[7:0]
0x00
00 4808
Independent
watchdog
option
OPT5
[3:0]
Reserved
00 4809
Number of
stabilization
clock cycles for OPT10
HSE and LSE
oscillators
Reserved
00 480A
Brownout reset OPT11
[3:0]
(BOR)
Reserved
52/101
Doc ID 15962 Rev 2
WWDG WWDG IWDG
_HALT
_HW
_HALT
IWDG
_HW
HSECNT[1:0]
LSECNT[1:0]
BOR_TH
0x00
0x00
BOR_
ON
0x01
STM8L151xx, STM8L152xx
Table 11.
Option
byte
Option bytes
Option byte description
Option description
No.
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable Readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L15x reference manual (RM0031).
OPT1
UBC[7:0] Size of the user boot code area
0x00: no UBC
0x01: the UBC contains only the interrupt vectors.
0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt
vectors.
0x03 - Page 0 to 3 reserved for UBC, memory write-protected
≥ 0xFF - Page 0 to 255 reserved for UBC, memory write-protected
Refer to User boot code section in the STM8L15x reference manual (RM0031).
OPT2
PCODESIZE[7:0] Size of the proprietary code area
0x00: no proprietary code area
0x02: Page 0 and 1 reserved for the proprietary code and read/write protected. Page 0 contains only
the interrupt vectors.
≥ 0xFF - Page 0 o 254 reserved for the proprietary code. Only page 1 to 254 are read/write protected.
Page 255 is always left free.
Refer to Proprietary code area (PCODE) section in the STM8L reference manual (RM0013) for more
details.
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent window watchdog reset on Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
OPT3
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
HSECNT: Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
OPT4
LSECNT: Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
Doc ID 15962 Rev 2
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Option bytes
Table 11.
STM8L151xx, STM8L152xx
Option byte description (continued)
Option
byte
Option description
No.
OPT5
BOR_ON:
0 - Brownout reset off
1 - Brownout reset on
BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 16 for details on the thresholds according to
the value of BOR_TH bits.
54/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Electrical parameters
8
Electrical parameters
8.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
8.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
8.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
8.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
8.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Figure 9.
Pin loading conditions
STM8L PIN
50 pF
Doc ID 15962 Rev 2
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Electrical parameters
8.1.5
STM8L151xx, STM8L152xx
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 10. Pin input voltage
STM8L PIN
VIN
8.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 12.
Voltage characteristics
Symbol
Ratings
Min
Max
VDD- VSS
External supply voltage (including VDDA
and VDDIO)(1)
-0.3
4.0
Input voltage on true open-drain pins
(PC0 and PC1)
VSS-0.3
VDD + 4.6
Input voltage on FT pins (PA7 and PE0)
VSS-0.3
VDD + 4.6
Input voltage on any other pin (2)
VSS-0.3
4.6
VIN
VESD
Electrostatic discharge voltage
Unit
V
see Absolute maximum
ratings (electrical sensitivity)
on page 90
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN max imum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be
respected.
56/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 13.
Electrical parameters
Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into VDD power line (source)
80
IVSS
Total current out of VSS ground line (sink)
80
Output current sunk by IR_TIM pin (with high sink LED
driver capability)
80
Output current sunk by any other I/O and control pin
25
IIO
Output current source by any I/Os and control pin
IINJ(PIN)
(1)
ΣIINJ(PIN) (1)
mA
- 25
(2)
±5
Total injected current (sum of all I/O and control pins) (2)
± 25
Injected current on any pin
Unit
1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be
respected.
2. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 14.
Symbol
TSTG
TJ
Thermal characteristics
Ratings
Storage temperature range
Min
Unit
-65 to +150
°C
Maximum junction temperature
Doc ID 15962 Rev 2
150
57/101
Electrical parameters
8.3
STM8L151xx, STM8L152xx
Operating conditions
Subject to general operating conditions for VDD and TA.
8.3.1
General operating conditions
Table 15.
General operating conditions
Symbol
fSYSCLK(1)
Parameter
System clock
frequency
VDD
Standard operating
voltage
VDDA
Analog operating
voltage
Power dissipation at
TA= 85 °C for suffix 6
devices
PD(3)
Power dissipation at
TA= 125 °C for suffix 3
devices
Conditions
Min
Max
Unit
1.65 V ≤VDD < 3.6 V
0
16
MHz
1.65(2)
3.6
V
1.65(2)
3.6
V
1.8
3.6
V
ADC not used
Must be at the same
potential as VDD
ADC used
VFQFPN48 (4)
TBD
LQFP48
TBD
WFQFPN32
(5)
LQFP32
TBD
WFQFPN28 (6)
TBD
VFQFPN48(4)
TBD
LQFP48
TBD
WFQFPN32(5)
TBD
LQFP32
TBD
WFQFPN28(6)
TBD
1.65 V ≤VDD < 3.6 V
(6 suffix version)
TA
TJ
Temperature range
Junction temperature
range
TBD
mW
-40
85
°C
1.65 V ≤VDD < 3.6 V
(3 suffix version)
-40
125
-40 °C ≤TA < 85 °C
(6 suffix version)
-40
105
-40 °C≤ TA < 125 °C
(3 suffix version)
°C
-40
130
1. fSYSCLK = fCPU
2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled.
3. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/ΘJA with TJmax in this table and ΘJA in “Thermal characteristics”
table.
4. VFQFPN48 package is used in the sampling phase. In the production phase, the UFQFPN48 package will be used (with a
thickness equal to 0.6 mm).
5. WFQFPN32 package is used in the sampling phase. In the production phase, the UFQFPN32 package will be used (with a
thickness equal to 0.6 mm).
6. WFQFPN28 package is used in the sampling phase. In the production phase, the UFQFPN28 package will be used (with a
thickness equal to 0.6 mm).
58/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Electrical parameters
8.3.2
Power-up / power-down operating conditions
Table 16.
Operating conditions at power-up / power-down (1)
Symbol
tVDD
Parameter
Conditions
Min
Typ
Max
VDD rise time rate
0(2)
∞
VDD fall time rate
0(2)
∞
tTEMP
Reset release delay
VDD rising
VPDR
Power-down reset threshold
Falling edge
VBOR0
Brown-out reset threshold 0
(BOR_TH[2:0]=000)
VBOR1
TBD
TBD
TBD
1.5
TBD
Falling edge
TBD
1.7
TBD
Rising edge
TBD
1.76
TBD
Brown-out reset threshold 1
(BOR_TH[2:0]=001)
Falling edge
TBD
1.93
TBD
Rising edge
TBD
2.03
TBD
Brown-out reset threshold 2
(BOR_TH[2:0]=010)
Falling edge
TBD
2.30
TBD
VBOR2
Rising edge
TBD
2.41
TBD
Brown-out reset threshold 3
(BOR_TH[2:0]=011)
Falling edge
TBD
2.55
TBD
VBOR3
Rising edge
TBD
2.66
TBD
Brown-out reset threshold 4
(BOR_TH[2:0]=100)
Falling edge
TBD
2.80
TBD
VBOR4
Rising edge
TBD
2.90
TBD
Falling edge
TBD
1.85
TBD
VPVD0
PVD threshold 0
Rising edge
TBD
1.94
TBD
Falling edge
TBD
2.04
TBD
VPVD1
PVD threshold 1
Rising edge
TBD
2.14
TBD
Falling edge
TBD
2.24
TBD
VPVD2
PVD threshold 2
Rising edge
TBD
2.34
TBD
Falling edge
TBD
2.44
TBD
VPVD3
PVD threshold 3
Rising edge
TBD
2.54
TBD
Falling edge
TBD
2.64
TBD
VPVD4
PVD threshold 4
Rising edge
TBD
2.74
TBD
Falling edge
TBD
2.83
TBD
VPVD5
PVD threshold 5
Rising edge
TBD
2.94
TBD
Falling edge
TBD
3.05
TBD
VPVD6
PVD threshold 6
Rising edge
TBD
3.15
TBD
Unit
µs/V
ms
V
1. Based on characterization results, unless otherwise specified.
2. Guaranteed by design, not tested in production.
Doc ID 15962 Rev 2
59/101
Electrical parameters
STM8L151xx, STM8L152xx
Figure 11. POR/BOR thresholds
Vdd
6DD
6
Operating power supply
Vdd
6
"/2THRESHOLD
"/24HRESHOLD?
6"/2
60$2
2ESET
3AFE2ESET
3AFE2ESETRELEASE
WITHOUT"/2"ATTERYLIFEEXTENSION
0$24HRESHOLD
Internal NRST
WITH WITHOUT
"/2 "/2
WITH
"/2
"/2ACTIVATEDBYUSERFOR
POWERDOWNDETECTION
"/2ALWAYSACTIVE
ATPOWERUP
60/101
Doc ID 15962 Rev 2
4IME
STM8L151xx, STM8L152xx
8.3.3
Electrical parameters
Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except if explicitly mentioned.
Subject to general operating conditions for VDD and TA.
Table 17.
Total current consumption in Run mode(1)
Max
Symbol
Parameter
Conditions(2)
Typ
55°C
(3)
(4)
(4)
fCPU = 125 kHz 0.5
TBD
TBD
TBD
TBD
fCPU = 1 MHz
0.6
TBD
TBD
TBD
TBD
0.9
TBD
TBD
TBD
TBD
1.3
TBD
TBD
TBD
TBD
2
TBD
TBD
TBD
TBD
fCPU = 125 kHz TBD TBD
TBD
TBD
TBD
fCPU = 1 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 4 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 8 MHz
TBD TBD
TBD
TBD
TBD
HSI RC osc.
fCPU = 4 MHz
(16 MHz)
fCPU = 8 MHz
fCPU = 16 MHz
All peripherals
OFF,
Supply
code executed
IDD(RUN) current in
HSE
from RAM,
run mode(5) V from 1.65 V external
DD
clock
to 3.6 V
(16 MHz)
85 °C 105 °C 125 °C
fCPU = 16 MHz TBD TBD
LSI RC osc.
f
= LSI
(typ. 38 kHz) CPU
LSE external
clock
fCPU = LSE
TBD
(6)
TBD
Unit
mA
TBD
(6)
TBD
TBD TBD
TBD
(6)
TBD
TBD
(6)
(32.768 kHz)
Doc ID 15962 Rev 2
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Electrical parameters
Table 17.
STM8L151xx, STM8L152xx
Total current consumption in Run mode(1) (continued)
Max
Symbol
Conditions(2)
Parameter
Typ
55°C
Supply
IDD(RUN) current in
run mode
(3)
(4)
(4)
fCPU = 125 kHz TBD TBD
TBD
TBD
TBD
fCPU = 1 MHz
0.7
TBD
TBD
TBD
TBD
HSI RC osc. fCPU = 4 MHz
1.4
TBD
TBD
TBD
TBD
fCPU = 8 MHz
2.3
TBD
TBD
TBD
TBD
fCPU = 16 MHz TBD TBD
TBD
TBD
TBD
fCPU = 125 kHz TBD TBD
TBD
TBD
TBD
fCPU = 1 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 4 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 8 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 16 MHz TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
All peripherals
OFF, code
executed from
HSE
Flash,
VDD from 1.65 V external
clock
to 3.6 V
(16 MHz)
LSI RC osc.
fCPU = LSI
LSE external
fCPU = LSE
clock
(32.768 kHz)
TBD
TBD TBD
1. Based on characterization results, unless otherwise specified
2. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU=fSYSCLK
3. For devices with suffix 6.
4. For devices with suffix 3.
5. CPU executing typical data processing
6. Data guaranteed, each individual device tested in production.
62/101
85 °C 105 °C 125 °C
Doc ID 15962 Rev 2
Unit
mA
STM8L151xx, STM8L152xx
Table 18.
Electrical parameters
Total current consumption in Wait mode(1)
Max
Conditions(2)
Symbol Parameter
Typ
55°C
HSI
Supply
IDD(Wait) current in
Wait mode
CPU not
clocked,
all peripherals
OFF,
code executed
from RAM
with Flash
switched OFF,
VDD from
1.65 V to 3.6 V
HSE crystal
oscillator
(16 MHz)
Supply
IDD(Wait) current in
Wait mode
CPU not
clocked,
all peripherals
OFF,
code executed
from Flash,
VDD from
1.65 V to 3.6 V
HSE crystal
oscillator
(16 MHz)
(4)
TBD
TBD
TBD
fCPU = 1 MHz
450
TBD
TBD
TBD
TBD
fCPU = 4 MHz
515
TBD
TBD
TBD
TBD
fCPU = 8 MHz
600
TBD
TBD
TBD
TBD
fCPU = 16 MHz
770
TBD
TBD
TBD
TBD
fCPU = 125 kHz TBD TBD
TBD
TBD
TBD
fCPU = 1 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 4 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 8 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 16 MHz TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD
TBD
TBD
TBD
fCPU = 1 MHz
500
TBD
TBD
TBD
TBD
fCPU = 4 MHz
560
TBD
TBD
TBD
TBD
fCPU = 8 MHz
660
TBD
TBD
TBD
TBD
fCPU = 16 MHz
840
TBD
TBD
TBD
TBD
fCPU = 125 kHz TBD TBD
TBD
TBD
TBD
fCPU = 1 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 4 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 8 MHz
TBD TBD
TBD
TBD
TBD
fCPU = 16 MHz TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
LSE crystal
fCPU = LSE
oscillator
(32.768 kHz)
Unit
µA
32
fCPU = 125 kHz 480
fCPU = LSI
LSI
(4)
TBD
LSE crystal
fCPU = LSE
oscillator
(32.768 kHz)
HSI
(3)
fCPU = 125 kHz 430
fCPU = LSI
LSI
85 °C 105 °C 125 °C
µA
83
TBD TBD
1. Based on characterization results, unless specified
2. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU = fSYSCLK
3. For temperature range 6.
4. For temperature range 3.
Doc ID 15962 Rev 2
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Electrical parameters
Table 19.
STM8L151xx, STM8L152xx
Total current consumption and timing in Low power run mode at VDD = 1.65 V to
3.6 V (1)(2)
Symbol
Parameter
Conditions
all peripherals OFF
LSI RC osc.
(at 38 kHz)
with TIM2 active(3)
IDD(LPR)
Supply current in Low
power run mode
all peripherals OFF
LSE external
clock
(32.768 kHz)
with TIM2 active (3)
1. No floating I/Os
2. Based on characterization results, unless otherwise specified
3. Timer 2 clock enabled and counter running
64/101
Doc ID 15962 Rev 2
Typ
Max
TA = -40 °C
to 25 °C
5.4
TA = 55 °C
TBD
TA = 85 °C
6.8
TA = 105 °C
9.2
TA = 125 °C
13.4
TA = -40 °C
to 25 °C
5.7
TA = 55 °C
TBD
TA = 85 °C
7.2
TA = 105 °C
9.4
TA = 125 °C
13.8
TA = -40 °C
to 25 °C
TBD
TBD
TA = 55 °C
TBD
TBD
TA = 85 °C
TBD
TBD
TA = 105 °C
TBD
TBD
TA = 125 °C
TBD
TBD
TA = -40 °C
to 25 °C
TBD
TBD
TA = 55 °C
TBD
TBD
TA = 85 °C
TBD
TBD
TA = 105 °C
TBD
TBD
TA = 125 °C
TBD
TBD
Unit
μA
STM8L151xx, STM8L152xx
Table 20.
Symbol
Electrical parameters
Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V (1)(2)
Parameter
Conditions
Typ Max Unit
TA = -40 °C to 25 °C
all peripherals OFF
LSI RC osc.
(at 38 kHz)
with TIM2
IDD(LPW)
active(3)
Supply current in
Low power wait mode
all peripherals OFF
LSE external
clock
(32.768 kHz)
with TIM2 active
(3)
3
TA = 55 °C
TBD
TA = 85 °C
4.4
TA = 105 °C
6.7
TA = 125 °C
11
TA = -40 °C to 25 °C
3.4
TA = 55 °C
TBD
TA = 85 °C
4.8
TA = 105 °C
7
TA = 125 °C
11.3
TA = -40 °C to 25 °C
TBD TBD
TA = 55 °C
TBD TBD
TA = 85 °C
TBD TBD
TA = 105 °C
TBD TBD
TA = 125 °C
TBD TBD
TA = -40 °C to 25 °C
TBD TBD
TA = 55 °C
TBD TBD
TA = 85 °C
TBD TBD
TA = 105 °C
TBD TBD
TA = 125 °C
TBD TBD
μA
1. No floating I/Os.
2. Based on characterization results, unless otherwise specified.
3. Timer 2 clock enabled and counter running.
Doc ID 15962 Rev 2
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Electrical parameters
Table 21.
STM8L151xx, STM8L152xx
Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V (1)(2)
Symbol
Parameter
Conditions
LCD OFF
LSI RC
(at 38 kHz)
IDD(AH)
LCD ON
(static duty)
(3)
66/101
TBD
TA = 55 °C
TBD
TA = 85 °C
TBD
TA = 105 °C
TBD
TA = 125 °C
TBD
TA = -40 °C to 25 °C
TBD
TA = 55 °C
TBD
TA = 85 °C
TBD
TA = 105 °C
TBD
TA = 125 °C
TBD
TA = -40 °C to 25 °C
TBD
TA = 125 °C
TBD
TA = -40 °C to 25 °C
TBD TBD
TA = 55 °C
TBD TBD
TA = 85 °C
TBD TBD
TA = 105 °C
TBD TBD
TA = 125 °C
TBD TBD
TA = -40 °C to 25 °C
TBD TBD
TA = 55 °C
TBD TBD
TA = 85 °C
TBD TBD
TA = 105 °C
TBD TBD
TA = 125 °C
TBD TBD
TA = -40 °C to 25 °C
TBD TBD
LCD ON
(static duty)
(3)
TBD
TBD
TA = 55 °C
LCD ON
T = 85 °C
(1/4 duty) (4) A
TA = 105 °C
TBD TBD
TA = 125 °C
TBD TBD
Supply current during
wakeup time from
Active-halt mode
(using HSI)
μA
TBD TBD
TBD TBD
TBD
Doc ID 15962 Rev 2
Unit
μA
TBD
LCD OFF
IDD(WUFAH)
TA = -40 °C to 25 °C
Max
TA = 55 °C
LCD ON
T = 85 °C
(1/4 duty) (4) A
TA = 105 °C
Supply current in
Active-halt mode
LSE external
clock
(32.768 kHz)
Typ
mA
STM8L151xx, STM8L152xx
Table 21.
Electrical parameters
Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V (1)(2) (continued)
Symbol
Parameter
Conditions
Wakeup time from
tWU_HSI(AH)(5)(6) Active-halt mode to
Run mode (using HSI)
Wakeup time from
tWU_LSI(AH)(5)(6) Active-halt mode to
Run mode (using LSI)
Typ
Max
Unit
5
TBD
μs
TBD TBD
μs
1. No floating I/O, unless otherwise specified.
2. Based on characterization results, unless otherwise specified.
3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.
4. LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
5. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU.
6. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
Table 22.
Total current consumption and timing in Halt mode at VDD = 2 V (1)(2)
Symbol
IDD(Halt)
Parameter
Condition
Supply current in Halt mode
(Ultra low power ULP bit =1 in
the PWR_CSR2 register)
Typ
Max
TA = -40 °C to 25 °C
400
TBD
TA = 55 °C
TBD
TBD(3)
TA = 85 °C
TBD
TBD
TA = 105 °C
TBD
TBD(3)
Unit
nA
IDD(WUHalt)
Supply current during wakeup
time from Halt mode (using
HSI)
TBD
tWU_HSI(Halt)(4)(5)
Wakeup time from Halt to Run
mode (using HSI)
5
TBD
µs
tWU_LSI(Halt) (4)(5)
Wakeup time from Halt mode
to Run mode (using LSI)
TBD
TBD
µs
mA
1. TA = -40 to 125 °C, no floating I/O, unless otherwise specified
2. Based on characterization results, unless otherwise specified
3. Tested in production
4. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register
5. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU
Doc ID 15962 Rev 2
67/101
Electrical parameters
STM8L151xx, STM8L152xx
Current consumption of on-chip peripherals
Table 23.
Peripheral current consumption
Symbol
Typ.
Parameter
VDD = 3.0 V
IDD(TIM1)
TIM1 supply current(1)
13
IDD(TIM2)
TIM2 supply current (1)
8
IDD(TIM3)
TIM3 supply current (1)
8
IDD(TIM4)
TIM4 timer supply current (1)
3
USART1 supply current (2)
6
IDD(SPI1)
SPI1 supply current (2)
3
IDD(I2C1)
I2C1 supply current (2)
5
IDD(DMA1)
DMA1 supply current
3
IDD(WWDG)
WWDG supply current
2
Peripherals ON(3)
44
IDD(USART1)
IDD(ALL)
RTC supply current when clocked by LSI
TBD
RTC supply current when clocked at 1 MHz
TBD
LCD supply current when clocked at 32 kHz /2
TBD
LCD supply current when clocked at 1 MHz /2
TBD
IDD(ADC1)
ADC1 supply current(4)
1500
IDD(DAC)
DAC supply current(5)
370
IDD(RTC)
Unit
µA/MHz
µA/MHz
µA
IDD(LCD)
IDD(COMP1)
Comparator 1 supply current(6)
IDD(COMP2)
Comparator 2 supply current(6)
IDD(PVD/BOR)
IDD(IDWDG)
0.160
Slow mode
2
Fast mode
5
Power voltage detector and brownout Reset unit supply current
(7)
Independent watchdog supply current
µA
2.8
TBD
1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in wait mode in both cases. No I/O pins toggling.
Not tested in production.
3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD
/2. DAC output is in high-impedance.
6. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
enabled with static inputs. Supply current of internal reference voltage excluded.
7. Including supply current of internal reference voltage.
68/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
8.3.4
Electrical parameters
Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
Table 24.
Symbol
HSE external clock characteristics
Parameter
Conditions
Min
Typ
Max
Unit
1
16
MHz
fHSE_ext
External clock source
frequency(1)
VHSEH(2)
OSC_IN input pin high level
voltage
0.7 x VDD
TBD
VHSEL(2)
OSC_IN input pin low level
voltage
VSS
0.3 x VDD
Cin(HSE)
OSC_IN input
capacitance(1)
V
ILEAK_HSE
TBD
OSC_IN input leakage
current
VSS < VIN < VDD
TBD
pF
TBD
nA
1. Guarenteed by design, not tested in production.
2. Data based on characterization results, not tested in production.
LSE external clock (LSEBYP=1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
Table 25.
LSE external clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
1
32.768
TBD
kHz
fLSE_ext
External clock source frequency(1)
VLSEH(2)
OSC32_IN input pin high level voltage
0.7 x VDD
TBD
VLSEL(2)
OSC32_IN input pin low level voltage
VSS
0.3 x VDD
Cin(HSE)
OSC32_IN input capacitance(1)
ILEAK_HSE
OSC32_IN input leakage current
V
TBD
TBD
pF
TBD
nA
1. Guarenteed by design, not tested in production.
2. Data based on characterization results, not tested in production.
Doc ID 15962 Rev 2
69/101
Electrical parameters
STM8L151xx, STM8L152xx
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 26.
HSE oscillator characteristics
Symbol
fHSE
Parameter
Conditions
Min
High speed external oscillator
frequency
Typ
1
Max
Unit
16
MHz
RF
Feedback resistor
TBD
kΩ
C(1)
Recommended load capacitance (2)
TBD
pF
IDD(HSE)
gm
HSE oscillator power consumption
C = 20 pF,
fOSC = 16 MHz
TBD (startup)
TBD (stabilized)(3)
C = 10 pF,
fOSC =16 MHz
TBD (startup)
TBD (stabilized)(3)
Oscillator transconductance
mA
3.5
tSU(HSE)(4) Startup time
VDD is stabilized
mA/V
1
ms
1. C=CL1=CL2 is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data based on characterization results, not tested in production.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This
value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 12. HSE oscillator circuit diagram
fHSE to core
Rm
RF
CO
Lm
CL1
OSC_IN
Cm
gm
Resonator
Consumption
control
Resonator
STM8
OSC_OUT
CL2
HSE oscillator critical gm formula
g mcrit = ( 2 × Π × f HSE ) 2 × R m ( 2Co + C )
2
Rm: Notional resistance (see crystal specification), Lm: Notional inductance (see crystal specification),
Cm: Notional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
CL1=CL2=C: Grounded external capacitance
gm >> gmcrit
70/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Electrical parameters
LSE crystal/ceramic resonator oscillator
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 27.
LSE oscillator characteristics
Symbol
Parameter
Conditions
fLSE
Low speed external oscillator
frequency
RF
C(1)
IDD(LSE)
gm
Typ
Max
Unit
32.768
kHz
Feedback resistor
TBD
kΩ
Recommended load capacitance (2)
TBD
pF
TBD(3)
LSE oscillator power consumption
Oscillator transconductance
tSU(LSE)(4)
Min
TBD
Startup time
µA
µA/V
VDD is stabilized
ms
1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.
Refer to crystal manufacturer for more details
3. Data based on characterization results, not tested in production.
4.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 13. LSE oscillator circuit diagram
fLSE
Rm
Lm
RF
CO
CL1
OSC_IN
Cm
gm
Resonator
Consumption
control
Resonator
STM8
OSC_OUT
CL2
Doc ID 15962 Rev 2
71/101
Electrical parameters
STM8L151xx, STM8L152xx
Internal clock sources
Subject to general operating conditions for VDD, and TA.
High speed internal RC oscillator (HSI)
Table 28.
Symbol
fHSI
HSI oscillator characteristics (1)
Parameter
Conditions
Frequency
VDD = 3.0 V
VDD = 3.0 V, 0 °C ≤TA ≤ 55 °C
VDD = 3.0 V, -10 °C ≤TA ≤ 70 °C
Accuracy of HSI
oscillator (factory
calibrated)
VDD = 3.0 V, -10 °C ≤TA ≤ 85 °C
VDD = 3.0 V, -10 °C ≤TA ≤ 125 °C
1.65 V ≤VDD ≤ 3.6 V,
-40 °C ≤TA ≤ 125 °C
TRIM
HSI user trim
resolution
tsu(HSI)
IDD(HSI)
Typ
Max
16
VDD = 3.0 V, TA = 25 °C
ACCHSI
Min
-1
(2)
MHz
1
-1.5 (2)
(2)
1.5 (2)
%
%
(2)
%
-2.5
(2)
2(2)
%
-4.5
(2)
(2)
%
3
%
-2
(2)
Unit
2
2
-4.5
1.65 V ≤VDD ≤ 3.6 V,
-40 °C ≤TA ≤ 125 °C
%
±0.4 (2)
±0.5
HSI oscillator setup
time (wakeup time)
3.7
7.4 (2)
µs
HSI oscillator power
consumption
100
140 (2)
µA
Min
Typ
Max
Unit
26
38
56
kHz
TBD
TBD(2)
µs
4
%
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
Low speed internal RC oscillator (LSI)
Table 29.
Symbol
fLSI
LSI oscillator characteristics (1)
Parameter
Conditions
Frequency
tsu(LSI)
LSI oscillator wakeup time
IDD(LSI)
LSI oscillator frequency
drift(3)
0 °C ≤TA ≤ 85 °C
-10
1. VDD = 1.8 V to 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. This is a deviation for an individual part, once the initial frequency has been measured.
72/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
8.3.5
Electrical parameters
Memory characteristics
TA = -40 to 125 °C unless otherwise specified.
Table 30.
RAM and hardware registers
Symbol
Parameter
Conditions
Min
VRM
Data retention mode (1)
Halt mode (or Reset)
1.4
Typ
Max
Unit
V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.
Flash memory
Table 31.
Symbol
VDD
tprog
Iprog
tRET
NRW
Flash program memory
Parameter
Unit
3.6
V
Programming time for 1 or 128 bytes (block)
erase/write cycles (on programmed byte)
TBD
ms
Programming time for 1 to 128 bytes (block)
write cycles (on erased byte)
TBD
ms
Programming/ erasing consumption
Min
fSYSCLK = 16 MHz
1.65
Typ
Max
(1)
Operating voltage
(all modes, read/write/erase)
Conditions
TA=+25 °C, VDD = 3.0 V
TBD
TA=+25 °C, VDD = 1.8 V
TBD
mA
Data retention (program memory) after 10000
erase/write cycles at TA=+85 °C
TRET=+55 °C
TBD(1)
Data retention (data memory) after 10000
erase/write cycles at TA=+85 °C
TRET=+55 °C
TBD(1)
Data retention (data memory) after 10000
erase/write cycles at TA=+85 °C
TRET=+85 °C
TBD(1)
Erase/write cycles (program memory)
See notes (1)(2)
TBD(1)
Erase/write cycles (data memory)
See notes (1)(3)
TBD(1)
years
kcycles
(4)
1. Data based on characterization results, not tested in production.
2. Retention guaranteed after cycling is 10 years @ 55 °C.
3. Retention guaranteed after cycling is 1 year @ 55 °C.
4. Data based on characterization performed on the whole data memory.
Doc ID 15962 Rev 2
73/101
Electrical parameters
8.3.6
STM8L151xx, STM8L152xx
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 32.
I/O static characteristics (1)
Symbol
Parameter
VIL
VIH
Vhys
Ilkg
RPU
CIO(7)
Input low level voltage(2)
Input high level voltage (2)
Schmitt trigger voltage hysteresis (3)
Input leakage current (4)
Weak pull-up equivalent resistor(6)
Conditions
Min
Max
Typ
Input voltage on true
open-drain pins (PC0
and PC1)
VSS -0.3
0.3 x VDD
Input voltage on FT
pins (PA7 and PE0)
VSS -0.3
0.3 x VDD
Input voltage on any
other pin
VSS -0.3
0.3 x VDD
Input voltage on true
open-drain pins (PC0
and PC1)
0.70 x VDD
VDD+3.6
Input voltage on FT
pins (PA7 and PE0)
0.70 x VDD
VDD+3.6
Input voltage on any
other pin
0.70 x VDD
VDDmax+0.3
Standard I/Os
200
True open drain I/Os
250
V
V
mV
VSS≤VIN≤VDD
Standard I/Os
-
-
50 (5)
VSS≤VIN≤VDD
True open drain I/Os
-
-
200(5)
VSS≤VIN≤VDD
PA0 with high sink LED
driver capability
-
-
200(5)
30
45
60
VIN=VSS
I/O pin capacitance
5
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
6. RPU pull-up equivalent resistor based on a resistive transistor.
7. Data guaranteed by Design, not tested in production.
74/101
Unit
Doc ID 15962 Rev 2
nA
kΩ
pF
STM8L151xx, STM8L152xx
Electrical parameters
Output driving current
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 33.
Output driving current (standard ports)
I/O
Symbol
Type
Output low level voltage for an I/O pin
Standard
VOL (1)
Parameter
VOH (2) Output high level voltage for an I/O pin
Conditions
Min
Max
Unit
IIO = +2 mA,
VDD = 3.0 V
0.45
V
IIO = +2 mA,
VDD = 1.8 V
0.45
V
IIO = +10 mA,
VDD = 3.0 V
0.7
V
IIO = -2 mA,
VDD = 3.0 V
VDD-0.45
V
IIO = -1 mA,
VDD = 1.8 V
VDD-0.45
V
IIO = -10 mA,
VDD = 3.0 V
VDD-0.7
V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD.
Table 34.
Output driving current (true open drain ports)
Open drain
I/O
Symbol
Type
VOL
(1)
Parameter
Output low level voltage for an I/O pin
Conditions
Min
Max
IIO = +3 mA,
VDD = 3.0 V
0.45
IIO = +1 mA,
VDD = 1.8 V
0.45
Unit
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
Table 35.
Output driving current (PA0 with high sink LED driver capability)
IR
I/O
Symbol
Type
VOL (1)
Parameter
Output low level voltage for an I/O pin
Conditions
IIO = +20 mA,
VDD = 2.0 V
Min
Max
Unit
TBD
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
Doc ID 15962 Rev 2
75/101
Electrical parameters
STM8L151xx, STM8L152xx
NRST pin
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 36.
Symbol
NRST pin characteristics
Parameter
Conditions
Min
Typ (1)
Max
VIL(NRST)
NRST Input low level voltage (1)
VSS
0.8
VIH(NRST)
NRST Input high level voltage (1)
1.4
VDD
VOL(NRST)
NRST Output low level voltage
RPU(NRST)
NRST Pull-up equivalent resistor (2)
VF(NRST)
NRST Input filtered pulse (3)
VNF(NRST)
NRST Input not filtered pulse (3)
IOL = 2 mA
Unit
V
VDD-0.8
30
45
60
kΩ
50
ns
300
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor
3. Data guaranteed by design, not tested in production.
The reset network shown in Figure 14 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 36. Otherwise the reset is not taken into account internally.
Figure 14. Recommended NRST pin configuration
VDD
RPU
RSTIN
EXTERNAL
RESET
CIRCUIT
0.01 μF
76/101
Filter
INTERNAL RESET
STM8L
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
8.3.7
Electrical parameters
Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 37 are derived from tests
performed under ambient temperature, fSYSCLK frequency and VDD supply voltage
conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 37.
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
tsu(NSS)(2)
(2)
th(NSS)
SPI1 characteristics
Parameter
Min
Max
Master mode
0
8
Slave mode
0
8
-
TBD
SPI clock frequency
SPI clock rise and fall time Capacitive load: C = 30 pF
NSS setup time
Slave mode
4 x 1/fSYSCLK
-
NSS hold time
Slave mode
TBD
-
SCK high and low time
Master mode,
fSYSCLK = 8 MHz, fSCK= 4 MHz
TBD
TBD
Master mode
TBD
-
Slave mode
TBD
-
Master mode
TBD
-
Slave mode
TBD
-
(2)
tw(SCKH)
tw(SCKL)(2)
Conditions(1)
tsu(MI) (2)
tsu(SI)(2)
Data input setup time
th(MI) (2)
th(SI)(2)
Data input hold time
Data output access time
Slave mode
-
3x 1/fSYSCLK
tdis(SO)(2)(4)
Data output disable time
Slave mode
TBD
-
tv(SO) (2)
Data output valid time
Slave mode (after enable edge)
-
TBD
tv(MO)(2)
Data output valid time
Master mode (after enable
edge)
-
TBD
Slave mode (after enable edge)
TBD
-
Master mode (after enable
edge)
TBD
-
th(MO)(2)
Data output hold time
MHz
ns
ta(SO)(2)(3)
th(SO)(2)
Unit
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Doc ID 15962 Rev 2
77/101
Electrical parameters
STM8L151xx, STM8L152xx
Figure 15. SPI timing diagram - slave mode and CPHA=0
NSS input
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tc(SCK)
th(NSS)
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
th(SI)
ai14134
Figure 16. SPI timing diagram - slave mode and CPHA=1(1)
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
B I T1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
78/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Electrical parameters
Figure 17. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
CPHA= 0
CPOL=0
SCK Input
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
B I T1 OUT
tv(MO)
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Doc ID 15962 Rev 2
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Electrical parameters
STM8L151xx, STM8L152xx
I2C - Inter IC control interface
Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified.
The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 38.
Symbol
I2C characteristics
Parameter
Standard mode
I2C
Fast mode I2C(1)
Min(2)
Min (2)
Max (2)
Unit
Max (2)
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0
0
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
300
th(STA)
START condition hold time
4.0
0.6
tsu(STA)
Repeated START condition setup
time
4.7
0.6
tsu(STO)
STOP condition setup time
4.0
0.6
μs
STOP to START condition time (bus
free)
4.7
1.3
μs
tw(STO:STA)
Cb
Capacitive load for each bus line
400
μs
900
ns
μs
400
1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
2. Data based on standard I2C protocol requirement, not tested in production.
Note:
For speeds around 200 kHz, the achieved speed can have a± 5% tolerance
For other speed ranges, the achieved speed can have a± 2% tolerance
The above variations depend on the accuracy of the external components used.
80/101
Doc ID 15962 Rev 2
pF
STM8L151xx, STM8L152xx
Electrical parameters
Figure 18. Typical application with I2C bus and timing diagram 1)
VDD
4.7kΩ
I2C
VDD
4.7kΩ
BUS
100Ω
SDA
100Ω
SCL
STM8L
REPEATED START
START
tsu(STA)
tw(STO:STA)
START
SDA
tr(SDA)
tf(SDA)
tsu(SDA)
STOP
th(SDA)
SCL
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tsu(STO)
tf(SCK)
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
8.3.8
LCD controller (STM8L152xx only)
Table 39.
LCD characteristics(1)
Symbol
Parameter
VLCD
LCD external voltage
VLCD0
LCD internal reference voltage 0
2.6
V
VLCD1
LCD internal reference voltage 1
2.7
V
VLCD2
LCD internal reference voltage 2
2.8
V
VLCD3
LCD internal reference voltage 3
2.9
V
VLCD4
LCD internal reference voltage 4
3.0
V
VLCD5
LCD internal reference voltage 5
3.1
V
VLCD6
LCD internal reference voltage 6
3.2
V
VLCD7
LCD internal reference voltage 7
3.3
V
Cext
VLCD external capacitance
Supply
IDD
current(2)
Min
Typ
0.1
at VDD = 1.8 V
Max.
Unit
3.6
V
2
µF
TBD
Supply current(2) at VDD = 3 V
TBD
RH
Low drive resistive network
TBD
MΩ
RL
High drive resistive network
TBD
kΩ
V33
Segment/Common higher level voltage
V23
Segment/Common 2/3 level voltage
2/3VLCDx
V
V12
Segment/Common 1/2 level voltage
1/2VLCDx
V
V13
Segment/Common 1/3 level voltage
1/3VLCDx
V
V0
Segment/Common lowest level voltage
VLCDx
0
V
V
1. Data guaranteed by Design, not tested in production.
2. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
Doc ID 15962 Rev 2
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Electrical parameters
STM8L151xx, STM8L152xx
VLCD external capacitor (STM8L152xx only)
The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor CEXT to the VLCD pin. CEXT is specified in Table 39.
8.3.9
Embedded reference voltage
Table 40.
Reference voltage characteristics(1)
Symbol
Parameter
Min
IREFINT
Internal reference voltage consumption
1.4
TS_VREFINT
ADC sampling time when reading the
internal reference voltage(2)
5
10
µs
IBUF
Internal reference voltage buffer
consumption (used for ADC)
13.5
25
µA
VREFINT out
Reference voltage output
1.225
TBD
V
VREFINT_DIV1
1/4 reference voltage
25
VREFNT_DIV2
1/2 reference voltage
50
VREFNT_DIV3
3/4 reference voltage
75
ILPBUF
Internal reference voltage low power buffer
consumption (used for comparators or
output)
730
IREFOUT
TBD
Typ
Max.
Unit
µA
%VREFINT_COMP
1200
nA
Buffer ouptut current(3)
1
µA
CREFOUT
Reference voltage output load
50
pF
tVREFINT
Internal reference voltage startup time
TBD
ms
tBUFEN
Internal reference voltage buffer startup
time once enabled (2)
10
µs
ACCVREFINT
Accuracy of VREFINT stored in engibyte
±5
mV
STABVREFINT
Stability of VREFINT in temperature
50
ppm/°C
STABVREFINT
Stability of VREFINT after 1000 hours
TBD
ppm
2
20
1. Based on characterization results, unless otherwise specified
2. Defined when ADC output reaches its final value ±1/2LSB
3. To guaranty less than 1% VREFOUT deviation
8.3.10
Temperature sensor
Table 41.
Symbol
Parameter
Min
Typ
Max.
Unit
V25
Sensor reference voltage at 25°C
TBD
0.495
TBD
V
TBD
TBD
°C
TBD
TBD
mV/°C
3.4
6
µA
TL
82/101
TS characteristics(1)
VSENSOR linearity with temperature
Avg_slope
Average slope
IDD(TEMP)
Consumption
Doc ID 15962 Rev 2
TBD
STM8L151xx, STM8L152xx
Table 41.
Electrical parameters
TS characteristics(1) (continued)
Symbol
Parameter
TSTART
Min
Temperature sensor startup time
Typ
(2)
ADC sampling time when reading the
temperature sensor
TS_TEMP
5
Max.
Unit
10
µs
10
µs
1. Based on characterization results, unless otherwise specified.
2. Defined for ADC output reaches its final value ±1/2LSB.
8.3.11
Comparator characteristics
Table 42.
Comparator 1 characteristics
Symbol
VDDA
TA
R400
Err400
Min (1)
Parameter
Err10
3.6
V
Temperature range
-40
125
°C
R400 value
TBD
TBD
kΩ
TBD
%
TBD
kΩ
TBD
%
VDDA
V
400
Error on R400
TBD
Comparator input voltage range
VREFINT
tSTART
td
Unit
1.65
10
Error on R10
VIN
Max(1)
Analog supply voltage
R10 value
R10
Typ
Internal reference reference voltage
0
1.225
TBD
Startup time after enable
7
TBD
µs
Propagation delay(2)
3
TBD
µs
3
TBD
mV
160
TBD
nA
Voffset
Comparator offset error
ICMP1
Consumption(3)
TBD
TBD
1. Data guaranteed by design, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
Table 43.
Symbol
VDDA
Comparator 2 characteristics
Parameter
Conditions
Min (1)
Typ
Max(1)
Unit
Analog supply voltage
1.65
3.6
V
TA
Temperature range
-40
125
°C
VIN
Comparator input voltage range
0
VDDA
V
Startup time after enable
in fast mode
1.65 V to 2.7 V
TBD
2.7 V to 3.6 V
TBD
Startup time after enable
in slow mode
1.65 V to 2.7 V
TBD
2.7 V to 3.6 V
TBD
tSTART
µs
µs
Doc ID 15962 Rev 2
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Electrical parameters
Table 43.
STM8L151xx, STM8L152xx
Comparator 2 characteristics
Symbol
Parameter
Min (1)
Conditions
Typ
Max(1)
Unit
µs
Propagation delay in fast
mode(2)
1.65 V to 2.7 V
TBD
TBD
tdf
2.7 V to 3.6 V
TBD
TBD
Propagation delay in slow
mode(2)
1.65 V to 2.7 V
TBD
TBD
tds
2.7 V to 3.6 V
TBD
TBD
1.65 V to 2.7 V
TBD
TBD
2.7 V to 3.6 V
TBD
TBD
1.65 V to 2.7 V
TBD
TBD
2.7 V to 3.6 V
TBD
TBD
1.65 V to 2.7 V
TBD
TBD
2.7 V to 3.6 V
TBD
TBD
Voffset
µs
mV
Comparator offset error
IDD(CMP2F) Consumption in fast mode
IDD(CMP2S) Consumption in slow mode
µA
µA
1. Data guaranteed by design, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
8.3.12
12-bit DAC characteristics
Table 44.
DAC characteristics, output on PF0(1)
Symbol
Parameter
Conditions
Min (2)
Typ
Max(1)
Unit
VDDA
Analog supply voltage
1.8
3.6
V
VREF+
Reference supply voltage
1.8
3.6
V
Temperature range
-40
125
°C
TA
IVDDA
IVREF+
Current on VDDA supply
No load, middle code
0x800 on the inputs
370
TBD
No load, worst code
0xF1C @ VREF+=3.6V
on the inputs
500
TBD
210
TBD
Current on VREF+ supply
(3)
RL
Resistive load
DACOUT buffer ON
RO
Output impedance
DACOUT buffer OFF
CL
Capacitive load(4)
DAC_OUT
DNL
84/101
DAC_OUT voltage(5)
Differential non
linearity(6)
5
µA
kΩ
TBD
kΩ
50
pF
DACOUT buffer ON
0.2
VREF+-0.2
V
DACOUT buffer OFF
0
VREF+
V
RL ≥5 kΩ, CL≤50 pF
DACOUT buffer ON
CL≤50 pF
DACOUT buffer OFF
Doc ID 15962 Rev 2
±1
TBD
12-bit
LSB
-
TBD
TBD
STM8L151xx, STM8L152xx
Table 44.
Electrical parameters
DAC characteristics, output on PF0(1) (continued)
Symbol
INL
Parameter
Conditions
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON
Integral non linearity(7)
CL≤ 50 pF
DACOUT buffer OFF
Offset
Offset
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON
error(8)
CL≤ 50 pF
DACOUT buffer OFF
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON
Gain error
Gain error
CL≤ 50 pF
Min (2)
Typ
Max(1)
±2
TBD
TBD
TBD
± 20
TBD
Unit
12-bit
LSB
mV
TBD
TBD
0.5
TBD
%
TBD
TBD
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON
TBD
TBD
CL≤ 50 pF
DACOUT buffer OFF
TBD
TBD
tsettling
Settling time (full scale: for a 12bit input code transition between
the lowest and the highest input
codes when DAC_OUT reaches
the final value ±1LSB
RL ≥5 kΩ, CL≤ 50 pF
7
TBD
µs
Update rate
Max frequency for a correct
DAC_OUT (@95%) change
when small variation of the input
code (from code i to i+1LSB).
RL ≥ 5 kΩ, CL ≤50 pF
1
Msps
tWAKEUP
Wakeup time from OFF state.
Input code between lowest and
highest possible codes.
RL ≥5 kΩ, CL≤50 pF
9
TBD
µs
PSRR+
Power supply rejection ratio (to
VDDA) (static DC measurement)
RL≥ 5 kΩ, CL≤50 pF
-60
-35
dB
DACOUT buffer OFF
TUE
Total unadjusted error
12-bit
LSB
1. For 48-pin package only.
2. Data guaranteed by design, not tested in production.
3. Resistive load between DACOUT and GNDA.
4. Capacitive load at DACOUT pin.
5. It gives the output excursion of the DAC.
6. Difference between two consecutive codes - 1 LSB.
7. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023.
8. Difference between measured value and ideal value=VREF/2.
Doc ID 15962 Rev 2
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Electrical parameters
Table 45.
STM8L151xx, STM8L152xx
DAC output on PB4-PB5-PB6(1)
Symbol
Rint
Parameter
Internal resistance between DAC
output and PB4-PB5-PB6 output
Min (2)
Typ
Max(1)
Unit
TBD
TBD
kΩ
1. 32 or 28-pin packages only. The DAC channel can be routed either on PB4, PB5 or PB6 using the routing
interface I/O switch registers.
2. Data guaranteed by design, not tested in production.
86/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Electrical parameters
8.3.13
12-bit ADC1 characteristics
Table 46.
ADC1 characteristics
Symbol
Parameter
VDDA
Analog supply voltage
VREF+
Reference supply voltage
VREF-
Conditions
2.4 V ≤VDDA≤ 3.6 V
Min (1)
Max(1)
Unit
1.8
3.6
V
2.4
VDDA
V
1.8 V≤VDDA≤ 2.4 V
Typ
VDDA
V
Lower reference voltage
VSSA
V
IVDDA
Current on the VDDA input pin
1000
µA
IVREF+
Current on the VREF+ input pin
400
VAIN
TA
0(2)
VREF+
Temperature range
-40
125
°C
TBD(3)
kΩ
on PF0 fast channel
TBD
kΩ
on all other channels
TBD
kΩ
on PF0 fast channel
TBD
pF
on all other channels
TBD
pF
External resistance on VAIN
RADC
Sampling switch resistance
CADC
Internal sample and hold capacitor
fS
µA
Conversion voltage range
RAIN
fADC
TBD
ADC sampling clock frequency
2.4 V≤VDDA≤3.6 V
without zooming
0.320
16
MHz
1.8 V≤VDDA≤2.4 V
with zooming
0.320
8
MHz
VAIN on PF0 fast
channel
0.02
1(4)
MHz
Sampling rate
VAIN on all other
channels
fTRIG
External trigger frequency
TBD
1/fADC
tLAT
External trigger latency
TBD
1/fADC
tS
tconv
tWKUP
tVREFINT
Sampling time
VAIN on fast channel
PF0
4(4)
1/fADC
VAIN on slow channels
TBD
1/fADC
Conversion time
16 MHz
Wakeup time from OFF state
Internal reference voltage startup time
12 + tS
1/fADC
1(3)
µs
3
µs
refer to
Table 40
ms
1. Data guaranteed by design, not tested in production.
2. VREF- or VDDA must be tied to ground.
3. For 1 Msps, maximum Rext is 0.5 kΩ.
4. Value obtained for continous conversion on fast channel.
Doc ID 15962 Rev 2
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Electrical parameters
Table 47.
STM8L151xx, STM8L152xx
ADC1 accuracy
Symbol
Parameter
Typ
Max(1)
Unit
DNL
Differential non linearity
TBD
±1
LSB
INL
Integral non linearity
TBD
±2
LSB
TUE
Total unadjusted error
TBD
±5
LSB
Offset
Offset error
TBD
±2
LSB
Gain
Gain error
TBD
± 3.5
LSB
ENOB
Effective number of bits
TBD
± 9.5
Bits
SINAD
Signal-to-noise and distortion ratio
TBD
TBD
dB
SNR
Signal-to-noise ratio
TBD
TBD
dB
THD
Total harmonic distorsion
TBD
TBD
dB
1. Data based on characterization, not tested in production.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 19 or Figure 20,
depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.
Figure 19. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM8L
V REF+
1 µF // 10 nF
V DDA
1 µF // 10 nF
V SSA/V REF-
ai17031
88/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Electrical parameters
Figure 20. Power supply and reference decoupling (VREF+ connected to VDDA)
STM8L
VREF+/VDDA
1 µF // 10 nF
VREF–/VSSA
ai17032
8.3.14
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000 standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Doc ID 15962 Rev 2
89/101
Electrical parameters
Table 48.
STM8L151xx, STM8L152xx
EMS data
Symbol
Parameter
Level/
Class
Conditions
VFESD
VDD = 3.3 V, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fCPU= 16 MHz,
induce a functional disturbance
conforms to IEC 61000
TBD
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fCPU = 16 MHz,
conforms to IEC 61000
TBD
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.
Table 49.
EMI data (1)
Symbol
Parameter
SEMI
Peak level
Conditions
VDD = 3.6 V,
TA = +25 °C,
LQFP32
conforming to
IEC61967-2
Monitored
frequency band
Max vs.
Unit
16 MHz
0.1 MHz to 30 MHz
TBD
30 MHz to 130 MHz
TBD
130 MHz to 1 GHz
TBD
SAE EMI Level
1
dBμV
-
1. Not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.
90/101
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Table 50.
ESD absolute maximum ratings
Symbol
VESD(HBM)
VESD(CDM)
Electrical parameters
Ratings
Conditions
Electrostatic discharge voltage
(human body model)
Electrostatic discharge voltage
(charge device model)
Maximum
value (1)
Unit
2000
TA = +25 °C
V
1000
1. Data based on characterization results, not tested in production.
Static latch-up
●
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
Table 51.
Electrical sensitivities
Symbol
LU
8.4
Parameter
Static latch-up class
Class
II
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 15: General operating conditions on page 58.
The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
●
TAmax is the maximum ambient temperature in ° C
●
ΘJA is the package junction-to-ambient thermal resistance in ° C/W
●
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
●
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
●
PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in
the application.
Doc ID 15962 Rev 2
91/101
Electrical parameters
Table 52.
Symbol
STM8L151xx, STM8L152xx
Thermal characteristics(1)
Parameter
Value
Unit
ΘJA
Thermal resistance junction-ambient
WFQFPN28 - 4 x 4 mm
TBD
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
TBD
°C/W
ΘJA
Thermal resistance junction-ambient
VFQFPN 32 - 5 x 5 mm
TBD
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 48- 7 x 7 mm
TBD
°C/W
ΘJA
Thermal resistance junction-ambient
VFQFPN 48- 7 x 7mm
TBD
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
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Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Package characteristics
9
Package characteristics
9.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 15962 Rev 2
93/101
Package characteristics
9.2
STM8L151xx, STM8L152xx
Package mechanical data
Figure 21. WFQFPN28 – 28-lead very very thin fine
pitch quad flat no-lead package outline
(4 x 4)(1)
A
A3
Figure 22. Recommended footprint
(dimensions in mm)(1)
ddd
A1
D
e
14
15
7
e
b
E
1
21
L2
L1
28
22
DG_ME b
1. Drawing is not to scale.
Table 53.
WFQFPN28 – 28-lead very very thin fine pitch quad flat no-lead package (4 x 4),
package mechanical data(1)
inches(2)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A(1)
0.7
0.75
0.8
0.0276
0.0295
0.0315
A1
0
0.02
0.05
0
0.0008
0.002
A3
b
0.2
0.18
0.25
0.0079
0.3
0.0071
0.0098
D
4
0.1575
E
4
0.1575
e
0.5
0.0197
0.0118
L1
0.25
0.35
0.45
0.0098
0.0138
0.0177
L2
0.3
0.4
0.5
0.0118
0.0157
0.0197
ddd
0.08
0.0031
Number of pins
N
28
1. Thickness valid for the WFQFPN28 package in the sampling phase. In the production phase, the UFQFPN28 package will
be used with a thickness equal to 0.6 mm.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
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Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
Package characteristics
Figure 23. WFQFPN32 – 32-lead very very thin fine pitch quad flat no-lead package
outline (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
E2
E
b
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
A0A3_ME
1. The exposed pad must be soldered to the PCB. It is recommended to connect it to VSS.
Table 54.
WFQFPN32 – 32-lead very very thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data(1)
inches(2)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A(1)
0.70
0.75
0.80
0.0276
0.0295
0.0315
A1
0
0.02
0.05
0.0008
0.0020
A3
0.20
0.0079
b
0.18
0.25
0.30
0.0071
0.0098
0.0118
D
4.85
5.00
5.15
0.1909
0.1969
0.2028
D2
3.20
3.45
3.70
0.1260
0.1358
0.1457
E
4.85
5.00
5.15
0.1909
0.1969
0.2028
E2
3.20
3.45
3.70
0.1260
0.1358
0.1457
e
L
ddd
0.50
0.30
0.40
0.0197
0.50
0.0118
0.08
0.0157
0.0197
0.0031
Number of pins
N
32
1. Thickness valid for the WFQFPN32 package in the sampling phase. In the production phase, the UFQFPN32 package will
be used with a thickness equal to 0.6 mm.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM8L151xx, STM8L152xx
Figure 24. LQFP32 – 32-pin low profile quad flat package outline
ccc C
D
D1
D3
24
A
A2
17
16
25
L1
b
E3
32
Pin 1
identification
E1 E
9
L
A1
1
K
c
8
5V_ME
Table 55.
LQFP32 – 32-pin low profile quad flat package, package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.6
A1
0.05
A2
1.35
b
0.3
c
0.09
D
8.8
D1
6.8
D3
Max
0.063
0.15
0.0020
1.4
1.45
0.0531
0.0551
0.0571
0.37
0.45
0.0118
0.0146
0.0177
0.2
0.0035
9
9.2
0.3465
0.3543
0.3622
7
7.2
0.2677
0.2756
0.2835
5.6
0.0059
0.0079
0.2205
E
8.8
9
9.2
0.3465
0.3543
0.3622
E1
6.8
7
7.2
0.2677
0.2756
0.2835
E3
5.6
0.2205
e
0.8
0.0315
L
0.45
L1
k
ccc
0.6
0.75
0.0177
1
0.0 °
3.5 °
7.0 °
0.0 °
0.1
3.5 °
0.0039
32
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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0.0295
0.0394
Number of pins
N
0.0236
Doc ID 15962 Rev 2
7.0 °
STM8L151xx, STM8L152xx
Package characteristics
Figure 25. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package Figure 26. Recommended footprint
outline(1)(2)
(dimensions in mm)(1)
D2
L
b
24
13
L
7.30
25
12
48
37
1
E
E2
b
36
6.20
0.20
e
7.30
1
6.20
36
5.80
5.60
0.30
37
48
e
12
25
13
D
A3
A1
A
5.60
0.55
24
5.80
0.50
0.75
ai15697
C
A2
Seating
plane
V0_ME
1. Drawing is not to scale.
2. The exposed pad must be soldered to the PCB. It is recommended to connect it to VSS.
Table 56.
VFQFPN48 – very thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm
pitch package mechanical data(1)
inches(2)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A(1)
0.900
0.800
1.000
0.0354
0.0315
0.0394
A1
0.020
0.050
0.0008
0.0020
A2
0.650
1.000
0.0256
0.0394
A3
0.250
b
0.230
0.180
0.300
0.0091
0.0071
0.0118
D
7.000
6.850
7.150
0.2756
0.2697
0.2815
D2
4.700
2.250
5.250
0.1850
0.0886
0.2067
E
7.000
6.850
7.150
0.2756
0.2697
0.2815
E2
4.700
2.250
5.250
0.1850
0.0886
0.2067
e
0.500
0.450
0.550
0.0197
0.0177
0.0217
L
0.400
0.300
0.500
0.0157
0.0118
0.0197
ddd
0.0098
0.080
0.0031
1. Thickness valid for the VFQFPN48 package in the sampling phase. In the production phase, the UFQFPN48 package will
be used with a thickness equal to 0.6 mm.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM8L151xx, STM8L152xx
Figure 27. LQFP48 – 48-pin low profile quad flat package outline (7x7)
D
ccc C
D1
D3
A
A2
25
36
24
37
L1
b
E3 E1 E
48
Pin 1
identification
13
1
L
A1
K
c
12
5B_ME
Table 57.
LQFP48 – 48-pin low profile quad flat package (7x7), package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.6
A1
0.05
A2
1.35
b
0.17
c
0.09
D
8.8
D1
6.8
D3
Max
0.063
0.15
0.002
1.4
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.2
0.0035
9
9.2
0.3465
0.3543
0.3622
7
7.2
0.2677
0.2756
0.2835
5.5
0.0059
0.0079
0.2165
E
8.8
9
9.2
0.3465
0.3543
0.3622
E1
6.8
7
7.2
0.2677
0.2756
0.2835
E3
5.5
0.2165
e
0.5
0.0197
L
0.45
L1
k
ccc
0.6
0.75
0.0177
1
0.0°
3.5°
7.0°
0.0°
0.08
3.5°
7.0°
0.0031
48
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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0.0295
0.0394
Number of pins
N
0.0236
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
10
Device ordering information
Device ordering information
Figure 28. STM8L15xxx ordering information scheme
Example:
STM8
L
151
C
4
U
6
Product class
STM8 microcontroller
Family type
L = Low power
Sub-family type
151 = Ultralow power
152 = Ultralow power with LCD
Pin count
C = 48 pins
K = 32 pins
G = 28 pins
Program memory size
4 = 16 Kbytes
6 = 32 Kbytes
Package
U = WFQFPN or VFQFPN
T = LQFP
Temperature range
3 = - 40 °C to 125 °C
6 = - 40 °C to 85 °C
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please contact the ST sales office nearest to you.
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Revision history
11
STM8L151xx, STM8L152xx
Revision history
Table 58.
Document revision history
Date
Revision
06-Aug-2009
1
Initial release
2
Updated peripheral naming throughout document.
Added Figure 6: STM8L151Cx 48-pin pinout (without LCD) on page 24
Added capacitive sensing channels in Features on page 1
Updated PA7, PC0 and PC1 in Table 4: STM8L15x pin description
Changed CLK and REMAP register names in Table 7
Changed description of WDGHALT in Table 11
Added typical power consumption values in Table 16 to Table 23
Correct VIH max in Table 32
10-Sep-2009
100/101
Changes
Doc ID 15962 Rev 2
STM8L151xx, STM8L152xx
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