STMICROELECTRONICS STP7NK30Z

STP7NK30Z
STF7NK30Z
N-CHANNEL 300V - 0.80Ω - 5A TO-220/TO-220FP
Zener-Protected SuperMESH™MOSFET
Table 1: General Features
TYPE
STP7NK30Z
STF7NK30Z
■
■
■
■
■
■
Figure 1: Package
VDSS
RDS(on)
ID
Pw
300 V
300 V
< 0.9 Ω
< 0.9 Ω
5A
5A
50 W
20 W
TYPICAL RDS(on) = 0.80 Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
GATE CHARGE MINIMIZED
VERY LOW INTRINSIC CAPACITANCES
VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ product
3
1
TO-220
2
TO-220FP
Figure 2: Internal Schematic Diagram
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
■ LIGHTING
Table 2: Order Codes
SALES TYPE
MARKING
PACKAGE
PACKAGING
STF7NK30Z
F7NK30Z
TO-220FP
TUBE
STP7NK30Z
P7NK30Z
TO-220
TUBE
Rev. 2
September 2005
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STP7NK30Z - STF7NK30Z
Table 3: Absolute Maximum ratings
Symbol
Parameter
Value
STP7NK30Z
VDS
VDGR
VGS
Unit
STF7NK30Z
Drain-source Voltage (VGS = 0)
300
V
Drain-gate Voltage (RGS = 20 kΩ)
300
V
Gate- source Voltage
± 30
V
ID
Drain Current (continuous) at TC = 25°C
5
5 (*)
A
ID
Drain Current (continuous) at TC = 100°C
3.2
3.2 (*)
A
Drain Current (pulsed)
20
20 (*)
A
Total Dissipation at TC = 25°C
50
20
W
Derating Factor
0.4
0.16
W/°C
IDM ()
PTOT
VESD(G-S)
dv/dt (1)
Gate source ESD(HBM-C=100pF, R=1.5KΩ)
Peak Diode Recovery voltage slope
VISO
Insulation Withstand Voltage (DC)
Tj
Tstg
Operating Junction Temperature
Storage Temperature
2800
V
4.5
V/ns
-
2500
-55 to 150
-55 to 150
V
°C
°C
( ) Pulse width limited by safe operating area
(1) ISD ≤5.7A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.
(*) Limited only by maximum temperature allowed
Table 4: Thermal Data
TO-220
TO-220FP
2.50
6.25
Rthj-case
Thermal Resistance Junction-case Max
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
°C/W
Maximum Lead Temperature For Soldering Purpose
300
°C
Max Value
Unit
5
A
130
mJ
Tl
°C/W
Table 5: Avalanche Characteristics
Symbol
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
Table 6: Gate-Source Zener Diode
Symbol
Parameter
Test Conditions
Min.
BVGSO
Gate-Source Breakdown
Voltage
Igs=± 1mA (Open Drain)
30
Typ.
Max.
Unit
V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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STP7NK30Z - STF7NK30Z
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 7: On /Off
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
300
Unit
Drain-source
Breakdown Voltage
ID =1 mA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating, TC = 125 °C
1
50
µA
µA
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20V
±10
µA
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 50µA
3.75
4.5
V
RDS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 2.5 A
0.80
0.90
Ω
Typ.
Max.
Unit
V(BR)DSS
3
V
Table 8: Dynamic
Symbol
gfs (1)
Parameter
Min.
VDS =15 V, ID = 2.5 A
2.5
S
VDS = 25V, f = 1 MHz, VGS = 0
380
74
15
pF
pF
pF
Equivalent Output Capacitance VGS = 0V, VDS = 0V to 400V
30
pF
td(on)
tr
td(off)
tf
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
VDD = 425 V, ID = 2.8 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 18)
11
25
20
10
ns
ns
ns
ns
tr(Voff)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
VDD = 320V, ID = 5A,
RG = 4.7Ω, VGS = 10V
(see Figure 17)
8.5
8.5
20
ns
ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 320V, ID = 5 A,
VGS = 10V
(see Figure 21)
13
4.5
7.6
17
nC
nC
nC
Typ.
Max.
Unit
5
20
A
A
1.6
V
Ciss
Coss
Crss
Coss eq. (3)
Forward Transconductance
Test Conditions
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Table 9: Source Drain Diode
Symbol
Parameter
ISD
ISDM (2)
Source-drain Current
Source-drain Current (pulsed)
VSD (1)
Forward On Voltage
ISD = 5 A, VGS = 0
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 5 A, di/dt = 100A/µs
VDD = 40, Tj = 150°C
(see Figure 19)
trr
Qrr
IRRM
Test Conditions
Min.
154
716
9.3
ns
nC
A
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
(3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
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STP7NK30Z - STF7NK30Z
Figure 3: Safe Operating Area for TO-220
Figure 6: Thermal Impedance for TO-220
Figure 4: Safe Operating Area for TO-220FP
Figure 7: Thermal Impedance for TO-220FP
Figure 5: Output Characteristics
Figure 8: Transfer Characteristics
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STP7NK30Z - STF7NK30Z
Figure 9: Transconductance
Figure 12: Static Drain-source On Resistance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 13: Capacitance Variations
Figure 11: Normalized Gate Thereshold Voltage vs Temperature
Figure 14: Normalized BVDSS vs Temperature
5/12
STP7NK30Z - STF7NK30Z
Figure 15: Normalized On Resistance vs TemperatureS
6/12
Figure 16: Source-Drain Diode Forward Characteristics
STP7NK30Z - STF7NK30Z
Figure 17: Unclamped Inductive Load Test Circuit
Figure 20: Unclamped Inductive Wafeform
Figure 18: Switching Times Test Circuit For
Resistive Load
Figure 21: Gate Charge Test Circuit
Figure 19: Test Circuit For Inductive Load
Switching and Diode Recovery Times
7/12
STP7NK30Z - STF7NK30Z
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at: www.st.com
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STP7NK30Z - STF7NK30Z
TO-220FP MECHANICAL DATA
mm.
DIM.
MIN.
A
4.4
inch
TYP
MAX.
MIN.
TYP.
4.6
0.173
0.181
MAX.
0.106
B
2.5
2.7
0.098
D
2.5
2.75
0.098
0.108
E
0.45
0.7
0.017
0.027
F
0.75
1
0.030
0.039
F1
1.15
1.7
0.045
0.067
F2
1.15
1.7
0.045
0.067
G
4.95
5.2
0.195
0.204
G1
2.4
2.7
0.094
0.106
H
10
10.4
0.393
0.409
L2
16
0.630
L3
28.6
30.6
1.126
1.204
L4
9.8
10.6
.0385
0.417
L5
2.9
3.6
0.114
0.141
L6
15.9
16.4
0.626
0.645
9
9.3
0.354
0.366
Ø
3
3.2
0.118
0.126
B
D
A
E
L7
L3
L6
F2
H
G
G1
F
F1
L7
L2
L5
1 2 3
L4
9/12
STP7NK30Z - STF7NK30Z
TO-220 MECHANICAL DATA
DIM.
mm.
MIN.
inch
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
b
0.61
0.88
0.024
0.034
b1
1.15
1.70
0.045
0.066
c
0.49
0.70
0.019
0.027
D
15.25
15.75
0.60
0.620
E
10
10.40
0.393
0.409
e
2.40
2.70
0.094
0.106
e1
4.95
5.15
0.194
0.202
F
1.23
1.32
0.048
0.052
H1
6.20
6.60
0.244
0.256
J1
2.40
2.72
0.094
0.107
0.551
L
13
14
0.511
L1
3.50
3.93
0.137
L20
16.40
L30
10/12
TYP
0.154
0.645
28.90
1.137
øP
3.75
3.85
0.147
0.151
Q
2.65
2.95
0.104
0.116
STP7NK30Z - STF7NK30Z
Table 10: Revision History
Date
Revision
10-May-2005
05-Sep-2005
1
2
Description of Changes
New stylesheet
Inserted Ecopack indication
11/12
STP7NK30Z - STF7NK30Z
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