SN74LVC1G3157-Q1 www.ti.com ............................................................................................................................................................ SCES463E – JUNE 2003 – REVISED APRIL 2008 SINGLE-POLE DOUBLE-THROW ANALOG SWITCH FEATURES 1 • • • • • • • • Qualified for Automotive Applications ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 1.65-V to 5.5-V VCC Operation Useful for Both Analog and Digital Applications Specified Break-Before-Make Switching • • Rail-to-Rail Signal Handling High Degree of Linearity High Speed, Typically 0.5 ns (VCC = 3 V, CL = 50 pF) Low On-State Resistance, Typically ≈6 Ω (VCC = 4.5 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II DBV PACKAGE (TOP VIEW) B2 1 DCK PACKAGE (TOP VIEW) 6 S GND 2 5 VCC B1 3 4 A B2 1 6 S GND 2 5 VCC B1 3 4 A See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This single-pole double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of up to VCC (peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION (1) TA –40°C to 125°C (1) (2) PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOT (SOT-23) – DBV Reel of 3000 1P1G3157QDBVRQ1 CC50 SOT (SC-70) – DCK Reel of 3000 1P1G3157QDCKRQ1 C50 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE CONTROL INPUTS ON CHANNEL L B1 H B2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2008, Texas Instruments Incorporated SN74LVC1G3157-Q1 SCES463E – JUNE 2003 – REVISED APRIL 2008 ............................................................................................................................................................ www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) B2 S B1 1 6 4 A 3 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range (2) –0.5 6.5 V VIN Control input voltage range (2) (3) –0.5 6.5 V –0.5 VCC + 0.5 (2) (3) (4) (5) VI/O Switch I/O voltage range IIK Control input clamp current VIN < 0 IIOK I/O port diode current VI/O < 0 II/O On-state switch current VI/O = 0 to VCC (6) Continuous current through VCC or GND θJA Package thermal impedance (7) Tstg Storage temperature range (1) (2) (3) (4) (5) (6) (7) 2 V –50 mA –50 mA ±128 mA ±100 mA DBV package 165 DCK package 258 –65 UNIT 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 5.5 V maximum. VI, VO, VA, and VBn are used to denote specific conditions for VI/O. II, IO, IA, and IBn are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 SN74LVC1G3157-Q1 www.ti.com ............................................................................................................................................................ SCES463E – JUNE 2003 – REVISED APRIL 2008 Recommended Operating Conditions (1) MIN MAX UNIT VCC 1.65 5.5 V VI/O 0 VCC V VIN 0 5.5 V VIH High-level input voltage, control input VIL Low-level input voltage, control input Δt/Δv VCC = 1.65 V to 1.95 V VCC × 0.75 VCC × 0.25 VCC = 1.65 V to 1.95 V VCC × 0.3 VCC = 2.3 V to 5.5 V Input transition rise/fall time VCC = 1.65 V to 1.95 V 20 VCC = 2.3 V to 2.7 V 20 VCC = 3 V to 3.6 V 10 VCC = 4.5 V to 5.5 V TA (1) V VCC × 0.7 VCC = 2.3 V to 5.5 V V ns/V 10 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 Submit Documentation Feedback 3 SN74LVC1G3157-Q1 SCES463E – JUNE 2003 – REVISED APRIL 2008 ............................................................................................................................................................ www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS On-state switch resistance (2) ron rrange See Figure 1 and Figure 2 VI = 0 V, IO = 4 mA VI = 1.65 V, IO = –4 mA VI = 0 V, IO = 8 mA VI = 2.3 V, IO = –8 mA VI = 0 V, IO = 24 mA VI = 3 V, IO = –24 mA VI = 0 V, IO = 30 mA VI = 2.4 V, IO = –30 mA VI = 4.5 , IO = –30 mA 0 ≤ VBn ≤ VCC (see Figure 1 and Figure 2) On-state switch resistance over signal range (2) (3) VCC Difference in on-state resistance between switches (2) (4) (5) See Figure 1 On-state resistance flatness (2) (4) (6) 3V 4.5 V 20 15 50 8 12 11 30 7 9.5 9 20 6 7.5 7 12 7 140 IA = –8 mA 2.3 V 45 IA = –24 mA 3V 18 4.5 V 1.65 V 0.5 VBn = 1.6 V, IA = –8 mA 2.3 V 0.1 VBn = 2.1 V, IA = –24 mA 3V 0.1 4.5 V 0.1 IA = –4 mA 1.65 V 110 IA = –8 mA 2.3 V 26 IA = –24 mA 3V 9 IA = –30 mA 4.5 V 4 1.65 V to 5.5 V Ω Ω 10 VBn = 1.15 V, IA = –4 mA 0 ≤ VBn ≤ VCC UNIT 15 1.65 V VBn = 3.15 V, IA = –30 mA ron(flat) 2.3 V MAX 11 IA = –4 mA IA = –30 mA Δron 1.65 V MIN TYP (1) Ω Ω ±1 µA Ioff (7) Off-state switch leakage current 0 ≤ VI, VO ≤ VCC (see Figure 3) IS(on) On-state switch leakage current VI = VCC or GND, VO = Open (see Figure 4) IIN Control input current 0 ≤ VIN ≤ VCC ICC Supply current VIN = VCC or GND 5.5 V ΔICC Supply-current change VIN = VCC – 0.6 V 5.5 V Cin Control input capacitance S 5V 2.7 pF Cio(off) Switch input/output capacitance Bn 5V 5.2 pF Cio(on) Switch input/output capacitance (1) (2) (3) (4) (5) (6) (7) 4 ±0.05 ±1 5.5 V 0V to 5.5 V Bn 5V A ±1 (1) ±0.1 (1) ±1 µA µA ±0.05 ±1 (1) 1 10 µA 500 µA 17.3 17.3 pF TA = 25°C Measured by the voltage drop between I/O pins at the indicated current through the switch. On-state resistance is determined by the lower of the voltages on the two (A or B) ports. Specified by design Δron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels This parameter is characterized, but not tested in production. Flatness is defined as the difference between the maximum and minimum values of on-state resistance over the specified range of conditions. Ioff is the same as IS(off) (off-state switch leakage current). Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 SN74LVC1G3157-Q1 www.ti.com ............................................................................................................................................................ SCES463E – JUNE 2003 – REVISED APRIL 2008 Analog Switch Characteristics TA = 25°C FROM (INPUT) PARAMETER Frequency response (switch on) (1) A or Bn Crosstalk (between switches) (2) A or Bn Charge injection (3) S Total harmonic distortion TEST CONDITIONS A or Bn VCC RL = 50 Ω, fin = sine wave (see Figure 6) Bn or A B1 or B2 Feedthrough attenuation (switch off) (2) (1) (2) (3) TO (OUTPUT) RL = 50 Ω, fin = 10 MHz (sine wave) (see Figure 7) B2 or B1 Bn or A CL = 5 pF, RL = 50 Ω, fin = 10 MHz (sine wave) (see Figure 8) A CL = 0.1 nF, RL = 1 MΩ (see Figure 9) VI = 0.5 Vp-p, RL = 600 Ω, fin = 600 Hz to 20 kHz (sine wave) (see Figure 10) Bn or A TYP UNIT 1.65 V 300 2.3 V 300 3V 300 4.5 V 300 1.65 V –54 2.3 V –54 3V –54 4.5 V –54 1.65 V –57 2.3 V –57 3V –57 4.5 V –57 3.3 V 3 5V 7 1.65 V 0.1 2.3 V 0.025 3V 0.015 4.5 V 0.01 MHz dB dB pC % Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB. Adjust fin voltage to obtain 0 dBm at input. Specified by design Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5 and Figure 11) PARAMETER tpd (1) ten FROM (INPUT) TO (OUTPUT) A or Bn Bn or A S Bn (2) tdis (3) tB-M (4) (1) (2) (3) (4) VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN 2 MAX VCC = 3.3 V ± 0.3 V MIN 1.2 MAX VCC = 5 V ± 0.5 V MIN 0.8 0.3 7 24 3.5 14 2.5 7.6 1.7 5.7 3 13 2 7.5 1.5 5.3 0.8 3.8 0.5 0.5 0.5 UNIT MAX 0.5 ns ns ns tpd is the slower of tPLH or tPHL. Propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). ten is the slower of tPZL or tPZH. tdis is the slower of tPLZ or tPHZ. Specified by design Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 Submit Documentation Feedback 5 SN74LVC1G3157-Q1 SCES463E – JUNE 2003 – REVISED APRIL 2008 ............................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION VCC VCC S VIL or VIH S 1 VIL 2 VIH 1 B1 SW B2 VO 2 A VI = VCC or GND SW GND IO r on + V Ť Ť VI * VO W IO VI – VO Figure 1. On-State Resistance Test Circuit 120 VCC = 1.65 V 100 ron − W 80 60 40 VCC = 2.3 V 20 VCC = 3 V VCC = 4.5 V 0 0 1 2 3 4 5 VI − V Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC 6 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 SN74LVC1G3157-Q1 www.ti.com ............................................................................................................................................................ SCES463E – JUNE 2003 – REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC S VIL or VIH SW B1 VI 1 VIL 2 VIH 1 SW B2 S VO 2 A A GND Condition 1: VI = GND, VO = VCC Condition 2: VI = VCC, VO = GND Figure 3. Off-State Switch Leakage-Current Test Circuit VCC VCC S VIL or VIH SW B1 VI 1 VIL 2 VIH 1 SW B2 S VO VO = Open 2 A A GND VI = VCC or GND Figure 4. On-State Switch Leakage-Current Test Circuit Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 Submit Documentation Feedback 7 SN74LVC1G3157-Q1 SCES463E – JUNE 2003 – REVISED APRIL 2008 ............................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC VCC VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 VCC/2 VCC/2 2 × VCC 2 × VCC 2 × VCC 2 × VCC 50 pF 50 pF 50 pF 50 pF 500 Ω 500 Ω 500 Ω 500 Ω 0.3 V 0.3 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 5. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 SN74LVC1G3157-Q1 www.ti.com ............................................................................................................................................................ SCES463E – JUNE 2003 – REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC S VIL or VIH SW S 1 VIL 2 VIH 1 B1 SW B2 2 A VO RL 50 Ω GND 50 Ω fin Figure 6. Frequency Response (Switch On) S VCC VIL or VIH TEST CONDITION VIL 20log10(VO2/VI) VIH 20log10(VO1/VI) VCC S B1 VB1 fin VB2 A Analyzer B2 GND 50 Ω RL 50 Ω Figure 7. Crosstalk (Between Switches) Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 Submit Documentation Feedback 9 SN74LVC1G3157-Q1 SCES463E – JUNE 2003 – REVISED APRIL 2008 ............................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC S VIL or VIH SW S 1 VIL 2 VIH 1 B1 SW Analyzer B2 A 2 RL 50 Ω GND fin 50 Ω Figure 8. Feedthrough VCC VCC S 1 B1 Logic Input SW B2 VOUT 2 RGEN VGE A GND RL CL RL/CL = 1 MΩ/100 pF Logic Input OFF ON OFF ∆VOUT VOUT Q = (∆VOUT)(CL) Figure 9. Charge-Injection Test 10 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 SN74LVC1G3157-Q1 www.ti.com ............................................................................................................................................................ SCES463E – JUNE 2003 – REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC S VIL or VIH B1 1 SW S 1 VIL 2 VIH 10 µF SW B2 A 2 VO RL 10 kΩ CL 50 pF GND 600 Ω fin VCC/2 VCC = 1.65 V, VI = 1.4 VP-P VCC = 2.30 V, VI = 2.0 VP-P VCC = 3.00 V, VI = 2.5 VP-P VCC = 4.50 V, VI = 4.0 VP-P Figure 10. Total Harmonic Distortion VCC VCC S B1 VI = VCC/2 B2 VO A GND VS RL CL RL/CL = 50 Ω/35 pF VO 0.9 y VO tB-M Figure 11. Break-Before-Make Internal Timing Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G3157-Q1 Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 8-Jul-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 1P1G3157QDBVRQ1 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 1P1G3157QDCKRQ1 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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