WINBOND WMS7202010P

PRELIMINARY
WMS7204
256-TAP QUAD-CHANNEL NON-VOLATILE DIGITAL
POTENTIOMETER
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Publication Release Date: January 2003
Revision 1.0
WMS7204
1. GENERAL DESCRIPTION
The WMS7204 is a 256-tap, quad-channel non-volatile digital potentiometer available in 10KΩ, 50KΩ
and 100KΩ end-to-end resistances. These devices can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of applications.
The output of each potentiometer is determined by the wiper position, which varies linearly between
VA and VB terminal according to the content stored in the volatile Tap Register (TR). The settings of
the TR can be provided either directly by the user through the industry standard SPI interface, or by
the non-volatile memory (NVMEM0~3) where the previous settings are stored. When changes are
made to the TR to establish a new wiper position, the value of the setting can be saved into any nonvolatile memory location (NVMEM0~3) by executing a NVMEM save operation. Each channel has its
own four non-volatile memory locations (NVMEM0~3) that can be directly written to, and read by,
users through the SPI interface. Upon powerup the content of the NVMEM0 is automatically loaded to
the Tap Register.
The WMS7204 contains four independent channels in 20-pin PDIP, SOIC and TSSOP packages and
can operate over a wide operating voltage range from 2.7V to 5.5V. A selectable output buffer is builtin for each channel for those applications where an output buffer is required.
2. FEATURES
•
256 taps for each potentiometer
•
Four independent, linear-taper channels in one package
•
End-to-end resistance available in 10KΩ, 50KΩ and 100KΩ
•
Selectable output buffer for each channel
•
SPI Serial Interface for data transfer and potentiometer control
•
Daisy-chain operation for multiple devices
•
Nonvolatile storage of four wiper positions per channel with power-on recall from NVMEM0
•
Low standby current (1µA Max. with output buffer inactive)
•
Endurance 100K typical stores per bit
•
Register Data Retention 100 years
•
Industrial temperature range: -40 ~ 85°C
•
Wide operating voltage range: 2.7V ~ 5.5V
•
Package option:
20-pin TSSOP, 20-pin SOIC, 20-pin PDIP
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WMS7204
Serial
3 Addressable Preset Tap
th
9
bit
9th
bit
VA2
MUX
NV Memory
Control
Tap
Register
SDO
RDY
R/B
MUX
NV Memory-1
Power on/Preset Mem Tap
SDI
WP
VW1
VB1
Interface
Decoder
CS
VA1
Decoder
CLK
Tap
Register
3. BLOCK DIAGRAM
VW2
VB2
NV Memory-2
Power on/Preset Mem Tap
VA3
MUX
Decoder
Tap
Register
3 Addressable Preset Tap
9th
bit
9th
bit
VW3
VB3
NV Memory-3
Power on/Preset Mem Tap
VA4
MUX
Decoder
Tap
Register
3 Addressable Preset Tap
th
9
bit
th
9
bit
VW4
VB4
VDD
V
DD
NV Memory-4
Power on/Preset Mem Tap
3 Addressable Preset Tap
-3-
9th
bit
9th
bit
GND
V
SS
Publication Release Date: January 2003
Revision 1.0
WMS7204
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 5
6. PIN DESCRIPTION ............................................................................................................................. 6
7. FUNCTIONAL DESCRIPTION............................................................................................................ 8
7.1. Potentiometer and Rheostat Modes ............................................................................................. 8
7.1.1. Rheostat Configuration .......................................................................................................... 8
7.1.2. Potentiometer Configuration .................................................................................................. 8
7.2. Programming Modes .................................................................................................................... 8
7.3. Non-Volatile Memory (NVMEM) ................................................................................................... 9
7.3.1 Write Protect of NVMEM ......................................................................................................... 9
7.4 Flow Control................................................................................................................................... 9
7.5. Daisy Chain ................................................................................................................................ 10
7.6. Serial Data Interface ................................................................................................................... 11
7.7. Instruction Set............................................................................................................................. 12
7.8. Basic Operation .......................................................................................................................... 13
7.8.1 Sending a Command ............................................................................................................ 14
7.8.2 Wake Up/Sleep/Power Commands ...................................................................................... 14
7.8.3 Write to Tap Register (TR).................................................................................................... 14
7.8.4 Programming Non-Volatile Memory (NVMEM)..................................................................... 16
7.8.5 Reading Tap Registers and NVMEM Locations ................................................................... 17
8. TIMING DIAGRAMS.......................................................................................................................... 18
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21
10.1 Test Circuits............................................................................................................................... 23
11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 24
11.1. Layout Considerations .............................................................................................................. 27
12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 28
13. ORDERING INFORMATION........................................................................................................... 31
14. VERSION HISTORY ....................................................................................................................... 32
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WMS7204
VW3
20 - PDIP
VA3
VW3
VA2
VB2
VW2
VB1
VA1
VW1
VDD
SDO
VA3
VA2
VB2
VB1
3
5
6
7
8
20 - SOIC
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9 10
4
5
6
7
8
9 10
VB3
VA3
11
2
4
VB4
12
10
1
3
VA4
9
VB3
2
VW4
VB4
1
VSS
VA2
R/B
13
SDI
WP
14
8
CLK
7
VW4
CS
VB2
VW2
VW3
15
VB3
6
VA4
VB4
VB1
VA4
VW1
16
20 19 18 17 16 15 14 13 12 11
VW4
17
5
VW2
4
20 19 18 17 16 15 14 13 12 11
R/B
VA1
VW1
18
VSS
19
3
SDI
WP
R/B
2
VA1
VDD
VSS
VDD
SDO
CS
SDI
WP
20
1
CLK
CS
CLK
SDO
5. PIN CONFIGURATION
20 - TSSOP
Publication Release Date: January 2003
Revision 1.0
WMS7204
6. PIN DESCRIPTION
TABLE 1 – PIN DESCRIPTION
PIN NAME
CLK
CS
PIN NO
2
1
I/O
I
Serial Clock pin. Data Shifts in one bit at a time on positive clock
(CLK) edges
I
Chip Select pin. When CS is HIGH, WMS7204 is deselected and
the SDO pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby state. CS LOW
enables WMS7204, placing it in the active power mode. It should
be noted that after a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
I
Serial Data Input pin. All opcodes, byte addresses and data to be
written to the registers are input on this pin. Data is latched by the
rising edge of the serial clock.
O
Serial Data Output pin with open-drain output. During a read cycle,
data is shifted out on this pin. Data is clocked out by the falling
edge of the serial clock except for the 1st bit , which is clocked out
by the falling edge of CS. Also can be used to daisy-chain several
parts.
O
Ready signal with active-LOW, open-drain output, and
acknowledges the completion of commands 2, 4, 5, 6, and 7.
3
SDI
18
SDO
DESCRIPTION
R/B
6
WP
4
I
Hardware Write Protect pin. When active LOW WP prevents any
changes to the present contents except retrieving NVMEM
contents.
VDD
20
-
Power Supply
VSS
5
-
Ground pin, logic ground reference
-
A terminal of potentiometer ‘1’, equivalent to the HI terminal
connection on a mechanical potentiometer
-
B terminal of potentiometer ‘1’, equivalent to the LO terminal
connection on a mechanical potentiometer
O
Wiper terminal of potentiometer ‘1’, equivalent to the wiper terminal
of a mechanical potentiometer
-
A terminal of potentiometer ‘2’, equivalent to the HI terminal
connection on a mechanical potentiometer.
-
B terminal of potentiometer ‘2’, equivalent to the LO terminal
connection on a mechanical potentiometer.
O
Wiper terminal of potentiometer ‘2’, equivalent to the wiper terminal
of a mechanical potentiometer.
-
A terminal of potentiometer ‘3’, equivalent to the HI terminal
VA1
VB1
VW1
18
16
17
VA2
13
VB2
15
VW2
14
VA3
12
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WMS7204
connection on a mechanical potentiometer.
VB3
10
VW3
11
VA4
7
VB4
9
VW4
8
-
B terminal of potentiometer ‘3’, equivalent to the LO terminal
connection on a mechanical potentiometer.
O
Wiper terminal of potentiometer ‘3’, equivalent to the wiper terminal
of a mechanical potentiometer.
-
A terminal of potentiometer ‘4’, equivalent to the HI terminal
connection on a mechanical potentiometer.
-
B terminal of potentiometer ‘4’, equivalent to the LO terminal
connection on a mechanical potentiometer.
O
Wiper terminal of potentiometer ‘4’, equivalent to the wiper terminal
of a mechanical potentiometer.
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Publication Release Date: January 2003
Revision 1.0
WMS7204
7. FUNCTIONAL DESCRIPTION
The WMS7204 series, a family of 256-tap, nonvolatile digitally programmable potentiometers is
designed to operate as both a potentiometer or a variable resistor depending upon the output
configuration selected.
The chip can store four 9-bit words in nonvolatile memory (NVMEM0 ~ NVMEM3) and the word stored
in the NVMEM0 will be used to set the tap register values when the device is powered up.
The WMS7204 is controlled by a serial SPI interface that allows setting tap register values as well as
storing data in the nonvolatile memory.
7.1. POTENTIOMETER AND RHEOSTAT MODES
The WMS7204 can operate as either a rheostat or as a potentiometer (voltage divider). When in the
potentiometer configuration there are two possible modes. One is without the output buffer and the
other mode is with the output buffer. Selecting the mode is done by controlling bit D8 of the data
register. D8 = 0 sets the output buffer off and D8 = 1 sets it on. Each channel can be independently
set to either buffer On or Off.
Note that this bit can only be set by loading the value to the NVMEM with instructions #5 and
then loading the TAP register with instruction #6 from NVMEM. This bit cannot be controlled by
directly writing the value to the chip when the tap register is set.
7.1.1. Rheostat Configuration
The WMS7204 acts as a two terminal resistive element in the rheostat configuration where one
terminal is either one of the end point pins of the resistor (VA and VB) and the other terminal is the
wiper (VW) pin. This configuration controls the resistance between the two terminals and the
resistance can be adjusted by sending the corresponding tap register setting commands to the
WMS7204 or loading a pre-set tap register value from nonvolatile memory NVMEM0 ~ MVMEM3.
7.1.2. Potentiometer Configuration
In potentiometer configuration an input voltage is connected to one of the end point pins (VA or VB).
The voltage on the wiper pin will be proportional to the voltage difference between VA and VB and the
wiper setting. The resistance cannot be directly measured in this configuration.
7.2. PROGRAMMING MODES
Two program modes are available for the WMS7204:
•
Direct program mode. The tap register setting can be changed either by loading a
predetermined value from an external microcontroller or by using the UP/DOWN commands.
The UP and DOWN commands change the tap register setting incrementally i.e., 1 LSB at a
time. The UP and DOWN commands will not wrap around at the ends of the scale.
•
NVMEM restore mode. One of the previously stored settings can be loaded into the TR
register from the non-volatile memory. Four 9-bit non-volatile memories, are available for each
channel to store tap register settings. The first register, NVMEM0, stores the favorite or
default tap register setting that will be loaded into the tap register at system power up or
software power on reset operation.
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WMS7204
7.3. NON-VOLATILE MEMORY (NVMEM)
Each channel has four NVMEM positions available for storing the output buffer operating mode and
the potentiometer setting. These NVMEM positions can be directly written through the SPI using a
write command (#5) with address and data bytes. Another command (#7) is available that stores the
current output buffer operating mode and potentiometer settings into the selected NVMEM position.
Bit A3 and A2 in the instruction byte decide which NVMEM position is used. (See Table 5)
All potentiometers are loaded with the value stored in the NVMEM position 0 for their respective
channel on power up.
7.3.1 Write Protect of NVMEM
Write-protect ( WP ) disables any changes of current content in the NVMEM regardless of the
commands, except that NVMEM setting can be retrieved using commands 4, 6 of Table 5. Therefore,
Write-Protect ( WP ) pin provides hardware NVMEM protection feature with WP tied to Vss. WP ,
which is active at logic LOW, should be tied directly to VDD if it is not being used.
7.4 FLOW CONTROL
Reading and writing to NVMEM requires an internal access cycle to complete before the next
command can be sent. The following commands have additional flow control using the R/B pin.
Read Tap Register (#2)
Read NVMEM (#4)
Program NVMEM (#5)
Load Tap Register(#6)
Program NVMEM with Tap Register (#7)
The R/B bit will be pulled HIGH when CS goes LOW, and will stay HIGH indicating the chip is
ready to accept another command. After sending one of those commands, the R/B pin should be
polled to determine when the device is ready to accept the additional data.
This flow control can be used on all commands without any performance penalty although it is only
needed on the commands listed above.
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Publication Release Date: January 2003
Revision 1.0
WMS7204
7.5. DAISY CHAIN
Multiple devices can be controlled by the same bus without the need for extra CS lines from the
microcontroller by daisy chaining the devices with the SDO of the first device connected to SDI of the
next device as shown in figure 3
VDD
CS
CLK
Micro
controller
SDO
CS
CLK
CS
CLK
CS
CLK
SDI SDO
SDI SDO
SDI SDO
Device
Device
Device
FIGURE 3 – DAISY CHAIN CONFIGURATION
A complete command is 24 bits including the instruction and the two data bytes. When shifting 24 bits
in to the first device in the chain, the 24 bits of the previous command will be shifted out. So to set up
two devices in a daisy chain, a total of 48 bits must be sent where the first 24 bits will be shifted out to
the second device and the 24 bits shifted in last will remain in the first device.
1. Command and data for device 2 is shifted into device 1; this will propagate to Device 2 when
the next 24 bits are shifted in.
Device
Command 1
Data
2
Data
2
Device
xx
xx
xx
2. Command and data for device 1 is shifted into device 1. Now Device 1 and 2 are correctly set
up
Device
Command 2
Data
1
Data
Device
Command A
1
Data
2
Data
2
FIGURE 4 – DAISY CHAIN COMMAND EXAMPLE
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WMS7204
7.6. SERIAL DATA INTERFACE
The WMS7204 contains a four-wire SPI interface:
•
SDO (Serial Data Output) Used for reading out the internal register contents and for daisy
chaining multiple devices.
•
SDI (Serial Data Input) Used for clocking in commands and potentiometer settings.
•
CS (Chip Select) This pin must be pulled LOW before starting to send a command and pulled
HIGH to signal the end of the command. This pin can be used to control multiple devices on
the bus.
•
CLK (Clock) The SDI bits are shifted in on the rising edge of the clock and SDO data is
shifted out on the falling edge of the clock.
The key features of this interface include:
•
Independently programmable Read & Write to all registers
•
Direct parallel refresh of all Tap registers from corresponding internal NVMEM registers
•
Increment and decrement instruction for each Tap register
•
Nonvolatile storage of the present Tap register values into one of the four NVMEM registers
available to each channel
•
Configurable output buffer amplifier to allow both the functions of a potentiometer and a
variable resistor
•
Four 9-bit non-volatile registers store four preset wiper positions and the first one will be
recalled to set the wiper position during power up.
The serial interface uses an SPI compatible uniform 24-bit word format as shown below. This format is
used for all members of the WMS720x family. The data is sent MSB first.
TABLE 2 – 24-BIT DATA WORD FORMAT
MSB
C3
LSB
C2
C1
C0
A3
A2
A1
A0
X
X
X
X
X
X
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
C3-C0 are the command bits that control the operation of the digital potentiometer according to the
command instructions shown in the Instruction Set in Table 5 in Section 7.7.
A1 and A0 are the address bits that determine which channel is activated, as shown in the table
below.
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Publication Release Date: January 2003
Revision 1.0
WMS7204
TABLE 3 – A1 AND A0 ADDRESS BIT DECODE TABLE
[A1 A0]
[0 0]
[0 1]
[1 0]
[1 1]
Channel
0
1
2
3
A3 and A2 are the address bits that decide which NVMEM memory to be accessed, as shown in the
table below.
TABLE 4 – A3 AND A2 ADDRESS BIT DECODE TABLE
[A3 A2]
[0 0]
[0 1]
[1 0]
[1 1]
NVMEM
0
1
2
3
D7-D0 are the data values to be loaded into the Tap Register to set the wiper position, while D8 is
used to set the output mode. D8 has to be loaded into the NVMEM0~3 first and then the “Load Tap
Register” command (#6) has be executed to load D8 into the output-selection MUX to set the output
mode. D8=0 sets the output to Buffer Off mode while D8=1 sets to Buffer On mode.
CS is taken LOW
before command
starts
CS
1
2 3
4 5
CLK
6
CS is taken HIGH
after command is
sent
7
8
9 1
0
C3 C2 C1 C0 A3 A2 A1 A0 x
`
SDI
x
1 1 1
1 2 3
x
x
1
4
x x
1 1 1
5 6 7
1 1
8 9
2
0
2 2
1 2
2 2
3 4
x D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO SDI must be valid on the rising edge of the clock SDO is valid on the falling edge of the clock or
CS
R/B
Note:
•
A multiple of 24 bits must always be sent or the
command will not be valid
•
Bits marked ‘x’ are don’t care bits.
R/B goes LOW at completion of commands
2, 4, 5, 6 and 7 to allow NVMEM to program
for TSV. For other commands, R/B stays
HIGH after command is sent.
FIGURE 5 – SPI COMMAND WAVEFORMS
7.7. INSTRUCTION SET
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WMS7204
TABLE 5 – INSTRUCTION SET
Inst
No.
Instruction Byte
Data Byte 1
Data Byte 2
C3 C2 C1 C0 A3 A2 A1 A0
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
x
x
2
1
A0
1
0
0
x
3
0
A0
1
0
0
4
1
0
1
5
0
0
6
1
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
No Operation
(NOP). Do nothing
x A1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Read Tap Register
and output selection
MUX register
x
x A1
x
x
x
x
x
x
x
x
D7 D6 D5 D4 D3 D2 D1 D0
0
A3
A2 A1
A0
x
x
x
x
x
x
x
x
x
1
0
A3
A2 A1
A0
x
D8
x
x
x
x
x
x
0
1
1
A3
A2 A1
A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Load Tap Register
and output selection
MUX register with
the contents of
NVMEM pointed to
by A3-A0
0
0
1
1
A3
A2 A1
A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Program NVMEM
pointed to by A3-A0
with the contents of
Tap Register and
output selection
MUX register
8
0
A0
1
1
1
x
x A1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Up: Increment
setting of TR by one
tap
9
1
A0
1
1
1
x
x A1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Down: Decrement
setting of TR by one
tap
10
1
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Sleep: Discontinue
clock supply to the
logic and memories
11
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Wake Up: Clock
supply to the logic
and memories
12
1
1
0
1
A3
A2 A1
A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Byte-erase
NVMEM pointed to
by A3-A0
13
1
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Power On Reset:
Software reset the
part to the power up
state
x
x
x
x
Operation
x
x
x
x
x
x
Write to Tap
Register with D7D0
x
D7 D6 D5 D4 D3 D2 D1 D0
Read NVMEM
pointed to by A3-A0
Program NVMEM
pointed to by A3-A0
with D8-D0
Note: C3-C0 are the command op-code; A3, A2 are the NVMEM address; A1, A0 are the channel address.
7.8. BASIC OPERATION
This chapter describes the sequences of commands to send to the WMS7204 and how to use the
different features.
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Publication Release Date: January 2003
Revision 1.0
WMS7204
7.8.1 Sending a Command
1. Take the chip out of SLEEP mode.
2. Check that the write protect is set correctly if writing to NVMEM.
3. Check that R/B is HIGH before issuing command.
4. Pull the CS pin LOW before sending data to the device.
5. 24 clock pulses are sent for each command. SDI must be valid on the rising edge of the clock,
SDO is valid on the falling edge of the clock or CS .
6. Take CS HIGH after the command has completed.
7. If command 2, 4, 5, 6 or 7 is sent, wait for the R/B pin to go HIGH before sending the next
command.
7.8.2 Wake Up/Sleep/Power Commands
The chip is in SLEEP mode after:
•
VDD is applied
•
A Power on Reset command is sent
•
A SLEEP command is sent
Before any operations can be performed the WAKE UP command must be sent.
When a SLEEP command is sent, the chip retains its resistor settings as long as the chip is powered
up but cannot accept any other commands than a WAKE UP command.
TABLE 6 – POWER RELATED COMMANDS
Inst.
No.
Command Name:
Command Byte
Data Byte 1
Data Byte 2
Comment
11
Wake Up
0001xxxx
xxxxxxxx
xxxxxxxx
Wake Up entire chip
10
Sleep
1000xxxx
xxxxxxxx
xxxxxxxx
Send chip into power save
mode
13
Power on Reset
1001xxxx
xxxxxxxx
xxxxxxxx
Reset Chip
1
NOP
0000xxxx
xxxxxxxx
xxxxxxxx
Dummy instruction
The commands above control the entire chip. There is no way to independently power on or off
individual potentiometers.
7.8.3 Write to Tap Register (TR)
The microcontroller can write a value directly into the tap register or send an increment or decrement
command to control the tap register. Alternatively, the contents of an NVMEM location can be written
- 14 -
WMS7204
to the tap register. The only way to change the output buffer mode is to write the desired value of bit
D8 into an NVMEM location and then load the corresponding NVMEM location into the tap register.
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Publication Release Date: January 2003
Revision 1.0
WMS7204
TABLE 7 – WRITING TO THE TAP REGISTERS
Inst.
No.
Command
Name:
Command Byte
Data Byte 1
Data Byte 2
Comment
3
Write to
Tap
Register
0
1
0
0
x
x
A1 A0
x
x
x
x
x
x
x
x
D7 D6 D5 D4 D3 D2 D1 D0
Writes a value to
the tap register of
the selected
channel
8
Up
0
1
1
1
x
x
A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Increment tap
register value by
one
9
Down
1
1
1
1
x
x
A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Decrement tap
register value by
one
6
Load Tap
Register
1
0
1
1
A3 A2 A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Load the selected
NVMEM location
into the tap
register
7.8.4 Programming Non-Volatile Memory (NVMEM)
The value stored in the NVMEM location is 9 bits, the 8 bits (D7-D0) of the tap register plus 1 bit (D8)
of the output buffer mode. The NVMEM position must be erased before writing to it. There are two
ways to program a value into NVMEM.
Write a value directly from the microcontroller
Load the current potentiometer setting into NVMEM.
TABLE 8 – PROGRAMMING NVMEM
Inst.
No
Command
Name
Command Byte
Data Byte 1
Data Byte 2
12
Erase
NVMEM
1
1
0
1
A3 A2 A1 A0
x
x
x
x
x
x
x
x
5
Program
NVMEM
0
0
1
0
A3 A2 A1 A0
x
x
x
x
x
x
x
D8
7
Program
NVMEM with
Tap Register
0
0
1
1
A3 A2 A1 A0
x
x
x
x
x
x
x
x
x
2. Program word at NVMEM location
- 16 -
x
x
x
x
x
x
D7 D6 D5 D4 D3 D2 D1 D0
x
For programming NVMEM, the following sequence must be followed:
1. Erase word at NVMEM location
x
Comment
x
x
x
x
x
x
x
Erases the 9 bit
word pointed to by
A3, A2, A1 and A0.
Writes a value to
the selected
NVMEM register of
the selected
channel
Takes the current
potentiometer
settings and saves
in the selected
NVMEM location.
WMS7204
7.8.5 Reading Tap Registers and NVMEM Locations
The contents of the tap register for any channel or any NVMEM location can be read back through the
SDO pin. When a command is sent, the data is clocked out on the falling edge of the clock. Since
daisy-chain operation requires data from one command to be clocked out when the next command
arrives, any read command must be followed by another command to get the correct data on the SDO
pin.
TABLE 9 – READING THE TAP REGISTERS
Inst.
No.
Command
Name:
Command Byte
Data Byte 1
4
Read
NVMEM
1
0
1
0
A3 A2 A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Read the
value of the
selected
NVMEM
location
2
Read Tap
Register
1
1
0
0
x
x
A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Read the
value of the
selected
tap register
1
NOP to
Read
Register
0
0
0
0
x
x
x
x
x
x
x
x
x
x D8
x
Data Byte 2
Comment
D7 D6 D5 D4 D3 D2 D1 D0
Output data
to SDO pin
To read the contents of either the tap register or a NVMEM location, the following sequence must be
followed.
1. Send the desired read command (#2 or #4) to select the register to read
2. Send another command such as NOP and read the SDO pin on the falling edge of the clock.
The other command could be any command, but to make sure that the chip does not change
anything, send either another Read command or a NOP command (#1).
- 17 -
Publication Release Date: January 2003
Revision 1.0
WMS7204
8. TIMING DIAGRAMS
CLK
tCYC
tWL
tWH
tLEAD
tLAG
CS
tDSU
tDH
MSB
SDI
LSB
tPD
tLAC
tLRL
MSB
SDO
tCS
LSB
tRSU
tST
tSV
R/B
tWPSU
tWPH
WP
FIGURE 6 – WMS7204 TIMING DIAGRAM
- 18 -
WMS7204
TABLE 10 – TIMING PARAMETERS
PARAMETER
SYMBOL
MIN.
SPI Clock Cycle Time
tCYC
100
ns
SPI Clock HIGH Time
tWH
50
ns
SPI Clock LOW Time
tWL
50
ns
Lead Time
tLEAD
100
ns
Lag Time
tLAG
100
ns
SDI Setup Time
tDSU
20
ns
SDI Hold Time
tDH
20
ns
CS to SDO – SPI Line Acquire
tLAC
5
ns
CS to SDO – SPI Line Release
tLRL
5
ns
CLK to SDO Propagation Delay
tPD
1
ns
R/B Rise to CS Fall
tRSU
500
ns
Store to NVMEM Save Time
tSV
CS Deselect Time
tCS
600
ns
Startup Time
tST
0.1
ms
WP Setup Time
tWPSU
10
ns
WP Hold Time
tWPH
10
ns
MAX.
2
UNIT
ms
Note: The interface timing characteristics apply to all parts but are guaranteed by design and not
subject to production test.
- 19 -
Publication Release Date: January 2003
Revision 1.0
WMS7204
9. ABSOLUTE MAXIMUM RATINGS
TABLE 11 – ABSOLUTE MAXIMUM RATINGS
Condition
Value
Junction temperature
150ºC
Storage temperature
-65º to +150ºC
Voltage applied to any pad
(Vss – 0.3V) to (VDD + 0.3V)
Vdd - Vss
-0.3 to 7.0V
Note: Exposure to conditions beyond those listed under: Absolute Maximum Ratings, may adversely affect the life and reliability
of the device.
- 20 -
WMS7204
10. ELECTRICAL CHARACTERISTICS
TABLE 12 – ELECTRICAL CHARACTERISTICS
All Parameters apply across specified operating ranges unless noted (VDD: 2.7V~5.5V; Temp: –40°C~85°C)
Typical values: VDD=5V and T=25°C
PARAMETER
Rheostat Mode
Nominal Resistance
Different Non Linearity
Integral Non Linearity
R
DNL
INL
Rheostat Tempco1
∆RAB/∆T
Wiper Resistance2
RW
Potentiometer Mode
Resolution1
Different Non Linearity2
Integral Non Linearity2
Potentiometer Tempco1
Full Scale Error
Zero Scale Error
Resistor Terminal
Voltage Range1
Terminal Capacitance1
Wiper Capacitance1
Dynamic Characteristics1
Bandwidth –3dB
Settling Time to 1 LSB
SYMBOL
MIN.
-20
-1
-1
8
-1
-1
VFSE
VZSE
-1
0
Total Harmonic Distortion1
THD
Digital Inputs/Outputs
Input High Voltage
Input Low Voltage
Output Low Voltage
Input Leakage Current
VIH
VIL
VOL
ILI
UNITS
0.3
0.5
+20
+1
+1
%
LSB
LSB
50
100
Ω
80
120
Ω
+1
+1
0
1
VSS
VDD
Bits
LSB
LSB
ppm/°
C
LSB
LSB
VDD=5V,
I=VDD/RTotal
VDD=2.7V,
I=VDD/RTotal
Code = 80h
Code = Full Scale
Code = Zero Scale
V
pF
pF
1.5
300
200
80
100
MHz
KHz
KHz
uS
VDD=5V, VB=VSS
Code = 80h
CL=30pf
VDD=5.5V=VA,
VB=VSS
10
mA
Ω
VO=1/2 scale
1
0.08
%
0.3VDD
0.4
+1
V
V
V
uA
0.7VDD
- 21 -
T=25ºC, VW open
30
30
3
-1
CONDITIONS
ppm/°
C
+20
BW10K
BW50K
BW100K
TS
Analog Output (Buffer enabled)
Amp Output Current2
IOUT
Amp Output Resistance2
Rout
MAX.
500
N
DNL
INL
∆Vw/∆T
VA,VB,VW
CA, CB
TYP.
VA=2.5V, VDD=5V,
f=1kHz, VIN=1VRMS
IOL=2mA
CS =VDD,Vin=Vss
~ VDD
Publication Release Date: January 2003
Revision 1.0
WMS7204
Output Leakage Current
ILo
Input Capacitance1
CIN
25
pF
Output Capacitance1
COUT
25
pF
-1
+1
uA
CS =VDD,Vin=VSS
~ VDD
VDD=5V, fc = 1Mhz
Code = 80h
VDD=5V, fc = 1Mhz
Code = 80h
Power Requirements
Operating Voltage1
VDD
Operating Current
IDDR
Operating Current
IDDW
ISA
Standby Current
Power Supply Rejection Ratio
2.7
5.5
V
1
1.8
mA
1
2
mA
1
mA
1
uA
1
LSB/V
0.5
ISB2
0.1
PSRR
All ops except
NVMEM program
During Nonvolatile memory
program
Buffer is active, no
load
Buffer is inactive,
Power Down, No
load
VDD=5V±10%,
Code=80h
Note: 1. Not subject to production test; 2. Only on Final Test; 3. VDD = +2.7V to 5.5V, VSS = 0V, T = 25ºC, unless otherwise
noted.
- 22 -
WMS7204
10.1 TEST CIRCUITS
VA
VW
V+
V+ = VDD
1LSB= V+/255
VA
VW
V+
VB
WMS7204
VMS*
VB
WMS7204
*Assume infinite input impedance
VMS*
*Assume infinite input impedance
Potentiometer divider nonlinearity error
test circuit (INL, DNL)
Power supply sensitivity test circuit (PSS, PSRR)
No Connection
VA
WMS7204
IW
VA
V+ = VDD ±10%
PSRR(dB) = 20LOG( ∆VMS )
∆VDD
VMS
PSS(%/%) = ∆
∆VDD
WMS7204
VW
W
VW
VB
+5V
VOUT
VB
VMS *
~
VIN
2.5V DC
Offset
*Assume infinite input impedance
Resistor position nonlinearity error test
circuit (Rheostat Operation: R-INL, R-DNL)
Capacitance test circuit
VMS*
VA
VW
VB
WMS7204
WMS7204
+5V
VA
IW = VDD /RTotal
IW
VIN
VW
~
VOUT
VB
RW = VMS /IW
OFFSET
GND
2.5V DC
*Assume infinite input impedance
Gain vs. frequency test circuit
Wiper resistance test circuit
FIGURE 7 – TEST CIRCUITS
- 23 -
Publication Release Date: January 2003
Revision 1.0
WMS7204
11. TYPICAL APPLICATION CIRCUIT
RA
RB
Vin
WMS7204
_
OP
AMP
VOUT
+
VOUT = - VIN
RA =
RB
RA
RAB(256 − D)
,
256
RB =
RABD
256
RAB = Total resistance of potentiometer
D = Wiper setting for WMS7204
FIGURE 8 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7204
VIN
RA
+
OP
_ AMP
VOUT
RB
WMS7204
VOUT = VIN (1+
RA =
RB
)
RA
RAB(256 − D)
RABD
, RB =
256
256
RAB = Total resistance of potentiometer
D = Wiper setting for WMS7204
FIGURE 9 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7204
- 24 -
WMS7204
V+
I = 32mA
VREFH
VREF = 5.0v
WMS7204
GND
20
19
18
17
16
15
14
13
12
11
3
2
U2
6
1
VDD
SDO
VA1
VW1
VB1
VB2
VW2
VA2
VA3
VW3
+
U3
CS
CLK
SDI
WP
VSS
R/B
VA4
VW4
VB4
VB3
-
C1
1
2
3
4
5
6
7
8
9
10
8
FIGURE 10 – WMS7204 TRIMMING VOLTAGE REFERENCE
WMS7204P-20
FIGURE 11 – WMS7204 AUDIO TONE CONTROL
- 25 -
Publication Release Date: January 2003
Revision 1.0
WMS7204
7
12
9
1/4 WMS7204
CS\
CLK
SDI
WP\
R2
CONTROL
1
20
3
19
5 6
2
6
Vout
1/4 WMS7204
2
4
3
1
R1
8
10
+
Vin
8
-
11
VDD
SDO
R/B\
VSS
Title
FIGURE 12 – PROGRAMMABLE LOW-PASS FILTER
- 26 -
WMS7204 EXA
WMS7204
11.1. LAYOUT CONSIDERATIONS
A 0.1µF bypass capacitor as close as possible to the VDD pin is recommended for best performance.
Often this can be done by placing the surface mount capacitor on the bottom side of the PC board,
directly between the VDD and VSS pins. Care should be taken to separate the analog and digital traces.
Sensitive traces should not run under the device or close to the bypass capacitors.
A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals.
FIGURE 13 – WMS7204 LAYOUT
- 27 -
Publication Release Date: January 2003
Revision 1.0
WMS7204
12. PACKAGE DRAWINGS AND DIMENSIONS
D
20
11
1
10
1
E
E
S
c
1
2
AA
A
L
Base Plane
Seating Plane
B
e1
α
B1
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
Dimension in inch
Min
Dimension in mm
Max
Min
Nom
0.010
Max
4.45
0.175
0.25
0.125
0.130
0.135
3.18
3.30
3.43
0.016
0.018
0.022
0.41
0.46
0.56
0.058
0.060
0.064
1.47
1.52
1.63
0.010
0.014
0.20
1.026
1.040
0.290
0.300
0.310
0.245
0.250
0.255
0.090
0.120
0.008
α
0
eA
0.335
S
Nom
0.25
0.36
20.06
26.42
7.37
7.62
7.87
6.22
6.35
6.48
0.100
0.110
2.29
2.54
2.79
0.130
0.140
3.05
3.30
3.56
15
0
0.375
8.51
9.02
9.53
0.355
0.075
15
1.91
FIGURE 14 – 20L PDIP – 300MIL
- 28 -
eA
WMS7204
11
20
E
10
1
Control demensions are in milmeters .
E
θ
FIGURE 15 – 20L SOIC – 150MIL
- 29 -
Publication Release Date: January 2003
Revision 1.0
WMS7204
FIGURE 16 – 20L TSSOP – 4.4MM
- 30 -
WMS7204
13. ORDERING INFORMATION
Winbond’s WinPot Part Number Description:
WMS72
XX
XXX X
Winbond WinPot Products
Features:
•
01: Single channel with SPI Interface
•
02: Dual channels with SPI Interface
•
04: Quad channels with SPI Interface
End-to-end Resistance:
• 010: 10KΩ
• 050: 50KΩ
• 100: 100KΩ
Package Index:
• T: TSSOP
• S: SOIC
• P: PDIP
• M: MSOP*
* Single-Channel Devices Only.
For the latest product information, access Winbond’s worldwide website at
http://www.winbond-usa.com
- 31 -
Publication Release Date: January 2003
Revision 1.0
WMS7204
14. VERSION HISTORY
VERSION
DATE
PAGE
1.0
Jan. 2003
All
DESCRIPTION
Initial issue
The contents of this document are provided only as a guide for the applications of Winbond
products. Winbond makes no representation or warranties with respect to the accuracy or
completeness of the contents of this publication and reserves the right to discontinue or make
changes to specifications and product descriptions at any time without notice. No license, whether
express or implied, to any intellectual property or other right of Winbond or others is granted by this
publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond
assumes no liability whatsoever and disclaims any express or implied warranty of merchantability,
fitness for a particular purpose or infringement of any Intellectual property.
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipments intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further, Winbond products are not intended for applications wherein failure of Winbond products
could result or lead to a situation wherein personal injury, death or severe property or
environmental injury could occur.
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441797
http://www.winbond-usa.com/
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62356998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
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TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
This product incorporates SuperFlash® technology licensed From SST.
- 32 -