VECTRON VS-702-EDT-KE

VS-702
Voltage Controlled SAW Oscillator
Previous Vectron Model VS-720
VS-702
Description
The VS-702 is a SAW Based Voltage Controlled Oscillator that achieves low phase noise and very low jitter performance. The VS702 is housed in an industry standard hermetically sealed LCC package and available in tape and reel.
Features
•
Industry Standard Package, 5.0 x 7.5 x 2.0 mm
•
ASIC Technology for Ultra Low Jitter
Applications
Ideal for PLL circuits for clock smoothing and frequency
translation
0.100 ps-rms typical across 12 kHz to 20 MHz BW
•
SONET, SDH
0.120 ps-rms typical across 50 kHz to 80 MHz BW
•
Synchronous Ethernet
•
Output Frequencies from 150 MHz to 1 GHz
•
Fiber Channel
•
3.3 V Operation
•
LAN / WAN
•
LV-PECL or LVDS Configuration with Fast Transition Times
•
Test and Measurement
•
Improved Temperature Stability over Standard VCSO (±20 ppm)
•
Output Disable Feature
•
0/70°C or -40/85°C operating temperature
•
Product is free of lead and compliant to EC RoHS Directive
Block Diagram
Complementary
Output
Output
VDD
BAW
SAW
VC
E/D
Gnd
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page1
Performance Specifications
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical
Maximum
Units
3.3
3.63
V
55
70
mA
Supply
Voltage1
VDD
Current (No Load)
IDD
2.97
Frequency
2
Nominal Frequency
fN
150
Absolute Pull Range 3,6
APR
±50
Linearity3
Lin
5
KV
+100
ppm/V
fSTAB
±20
ppm
3
Gain Transfer Positive (See pg 5)
Temperature Stability3
1000
MHz
ppm
10
%
Outputs
3
VDD-1.5
Mid Level
VDD-1.3
VDD-1.2
V
Single Ended Swing3
750
mV-pp
Double Ended Swing3
1.5
V-pp
Current
Rise Time4
Fall Time4
Symmetry3
IOUT
20
mA
tR
tF
500
500
ps
ps
55
%
SYM
45
50
5
Jitter (12 kHz - 20 MHz BW)622.08MHz
фJ
0.1
0.250
ps-rms
Jitter (50 kHz - 80 MHz BW)155.52MHz5
фJ
0.12
0.300
ps-rms
Period Jitter, RMS (622.08MHz)7
фJ
2.5
3.0
ps
Period Jitter, Peak - Peak (622.08MHz)
7
фJ
Spurious Suppression2
16
24
ps
-60
-50
dBc
Control Voltage
Control Voltage Range for APR
VC
0.3
Control Voltage Input Impedance
ZIN
75
3.0
KΩ
V
Control Voltage Modulation BW
BW
50
kHz
Output Enabled, Option A
Output Disabled, Option A
VIH
VIL
Output Enabled, Option C
Output Disabled, Option C
VIL
VIH
Operating Temperature
TOP
Enable/Disable
0.7*VDD
0.2*VDD
0.7*VDD
Package Size
1]
2]
3]
4]
5]
6]
7]
V
V
0.3*VDD
0/70 or -40/85
°C
5.0 x 7.5 x 2.0
mm
The VS-702 power supply should be filtered, eg, 0.1 and 0.01uF to ground
See Standard Frequencies and Ordering Information tables for more specific information
Parameters are tested with production test circuit below (Fig 1).
Measured from 20% to 80% of a full output swing (Fig 2).
Integrated across stated bandwidth.
Tested with Vc = 0.3V to 3.0V unless otherwise stated in part description
Broadband Period Jitter measured using Lecroy Wavemaster 8600A 6 GHz Oscilloscope, 25K samples taken. See application note.
Fig 1: Test Circuit
Fig 2: LVPECL Waveform
tR
tF
SYM = 100 x tA / tR
tA
tR
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page2
Outline Drawing & Pad Layout
6
5
4
XXX.XXXX
VS702
YWW
VDUGLA
CCC-CCCC
XXX.XX
35.328
VI YWW
XXXMXXX
2
3
Dimensions in inches (mm)
Table 2. Pin Out
Pin
Symbol
Function
1
VC
VCXO Control Voltage
2
OE
Enable/Disable
**See Ordering Options**
3
GND
Case and Electrical Ground
4
Output
Output
5
COutput
Complementary Output
6
VDD
Power Supply Voltage (3.3V ±10%)
Typical Phase Noise
Typical Gain
VS-702 @ 622.08 MHz
200
120
150
110
100
100
0
90
0
0.5
1
1.5
2
2.5
3
-50
80
-100
70
-150
-200
60
Vc (volts)
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page3
Gain (ppm/V)
50
Pull (ppm)
1
Series1
Series2
Suggested Output Load Configurations
The VS-702 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 3. There are numerous application notes on
terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, and a pull-up/pull-down scheme as
shown in Figure 5. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Figure 3 Standard PECL Output Configuration
Figure 4 Single Resistor Termination Scheme
Resistor values are typically 120 to 240 ohms
Figure 5 Pull-Up Pull-Down Termination
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow
simulation. The VS-702 family is capable of meeting the following qualification tests:
Table 3. Environmental Compliance
Parameter
Conditions
Mechanical Shock
MIL-STD-883, Method 2002
Typical Characteristics - Phase Noise
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross and Fine Leak
MIL-STD-883, Method 1014
Resistance to Solvents
MIL-STD-883, Method 2015
Moisture Sensitivity Level
MSL 1
Contact Pads
Gold over Nickel
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not
implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet.
Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Permanent damage is
also possible if OD or Vc is applied before Vcc.
Table 4. Absolute Maximum Ratings
Parameter
Symbol
Ratings
Unit
Power Supply
VDD
0 to 6
V
Output Current
IOUT
25
mA
Voltage Control Range
VC
0 to VDD
V
Storage Temperature
TS
-55 to 125
°C
Soldering Temp/Time
TLS
260 / 40
°C / sec
Although ESD protection circuitry has been designed into the VS-702 proper precautions should be taken when handling
and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing
and design protection evaluation.
Table 5. ESD Ratings
Model
Minimum
Conditions
Human Body Model
500V
MIL-STD-883, Method 3015
Charged Device Model
500V
JESD22-C101
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
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IR
IR Reflow
Table 6. Reflow Profile (IPC/JEDEC J-STD-020C)
Parameter
Symbol
Value
PreHeat Time
Ts-min
Ts-max
tS
60 sec Min, 180 sec Max
150°C
200°C
Ramp Up
RUP
3 °C/sec Max
Time Above 217 °C
tL
60 sec Min, 150 sec Max
Time To Peak Temperature
T25C to peak
480 sec Max
Time at 260 °C
tP
20 sec Min, 40 sec Max
Ramp Down
RDN
6 °C/sec Max
The device is qualified to meet the JEDEC
standard for Pb-Free assembly. The
temperatures and time intervals listed
are based on the Pb-Free small body
requirements. The VS-702 device is
hermetically sealed so an aqueous wash is
not an issue.
Termination Plating:
Electroless Gold Plate over Nickel Plate
Tape & Reel (EIA-481-2-A)
Table 7. Tape and Reel Information
Tape Dimensions (mm)
Reel Dimensions (mm)
Dimension
W
F
Do
Po
P1
A
B
C
D
N
W1
W2
Tolerance
Typ
Typ
Typ
Typ
Typ
Typ
Min
Typ
Min
Min
Typ
Max
# Per
Reel
VS-702
16
7.5
1.5
4
8
178
1.5
13
20.2
50
16.4
22.4
200
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page5
Table 8. Standard Output Frequencies (MHz)
155M520000
156M250000
160M000000
162M000000
175M000000
187M500000
200M000000
212M500000
240M000000
245M760000
250M000000
260M000000
268M800000
300M000000
311M040000
312M500000
320M000000
324M000000
350M000000
375M000000
384M000000
389M600000
400M000000
480M000000
491M520000
500M000000
531M250000
532M000000
533M000000
537M600000
622M080000
625M000000
635M040000
637M500000
640M000000
644M531300
657M421900
666M514300
669M326600
672M162700
690M569200
693M483000
704M380600
707M352700
720M000000
742M434700
768M000000
796M875000
800M000000
901M120000
1000M00000
Ordering Information
VS-702- E C E - K X A N - xxxMxxxxxx
Frequency in MHz
Product Family
VS: VCSO
Other (Future Use)
N: Standard
Package
702: 5 x 7.5 x 2.0 mm
Enable/Disable
A: Enable High
C: Enable Low
Input
E: 3.3 Vdc ±10%
Stability
X: Standard
E: ±20ppm Temperature Stability
Output
C: LVPECL (45/55% Symmetry)
D: LVDS (45/55% Symmetry)
Absolute Pull Range
K: ±50ppm
Operating Temperature
T: 0/70°C
E: -40/85°C
*Note: not all combination of options are available.
Other specifications may be available upon request.
Example: VS-702-ECE-KXAN-622M080000
For Additional Information, Please Contact
USA:
Europe:
Asia:
Vectron International
267 Lowell Road
Hudson, NH 03051
Tel: 1.888.328.7661
Fax: 1.888.329.8328
Vectron International
Landstrasse, D-74924
Neckarbischofsheim, Germany
Tel: +49 (0) 3328.4784.17
Fax: +49 (0) 3328.4784.30
Vectron International
1F-2F, No 8 Workshop, No 308 Fenju Road
WaiGaoQiao Free Trade Zone
Pudong, Shanghai, China 200131
Tel: 86.21.5048.0777
Fax: 86.21.5048.1881
Disclaimer
Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application.
No rights under any patent accompany the sale of any such product(s) or information.
Rev: 1/10/2009
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
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