CATALYST CAT24FC16ZD4ITE13

H
CAT24FC16
EE
GEN FR
ALO
16-kb I2C Serial EEPROM
LE
A D F R E ETM
FEATURES
■ 400 kHz (2.5 V) I2C bus compatible
■ 100 year data retention
■ 2.5 to 5.5 volt operation
■ 8-pin DIP, SOIC, TSSOP, MSOP and TDFN
■ Low power CMOS technology
packages
■ 16-byte page write buffer
- “Green” package option available
■ Hardware write protect
■ Self-timed write cycle with auto-clear
■ 1,000,000 program/erase cycles
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DESCRIPTION
The CAT24FC16 is a 16-kb Serial CMOS EEPROM
internally organized as 2048 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC16
PIN CONFIGURATION
DIP Package (P, L)
NC
NC
NC
VSS
1
2
3
8
7
6
VCC
WP
SCL
NC
NC
NC
1
2
3
4
5
SDA
VSS
4
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TSSOP Package (U, Y)
NC
NC
NC
VSS
D
1
2
3
4
MSOP Package (R, Z)
NC
NC
NC
VSS
1
2
3
4
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SOIC Package (J, W)
8
7
6
5
VCC
WP
SCL
SDA
8
7
6
5
8
7
6
VCC
WP
SCL
5
SDA
features a 16-byte page write buffer. The device operates
via the I2C bus serial interface and is available in 8-pin
DIP, SOIC, TSSOP, MSOP and TDFN packages.
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BLOCK DIAGRAM
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
WP
CONTROL
LOGIC
COLUMN
DECODERS
E2PROM
XDEC
VCC
WP
SCL
SDA
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
TDFN Package (RD4, ZD4)
SCL
VCC 1
8 NC
WP 2
7 NC
SCL 3
6 NC
SDA 4
5 VSS
STATE COUNTERS
PIN FUNCTIONS
Pin Name
* Catalyst Semiconductor is licensed by Philips Corporation
to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
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■ 2,048 x 8 memory organization
■ Industrial and extended temperature ranges
1
Function
NC
No Connect
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
2.5 V to 5.5 V Power Supply
VSS
Ground
Doc. No. 1054, Rev. I
CAT24FC16
Lead Soldering Temperature (10 seconds) ...... 300°C
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
Output Short Circuit Current(2) ....................... 100 mA
–55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
*COMMENT
Voltage on Any Pin with
Respect to Ground(1) ............ –2.0 V to VCC + 2.0 V
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
VCC with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
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RELIABILITY CHARACTERISTICS(3)
Symbol
Parameter
Min
NEND
Endurance
1,000,000
TDR
Data Retention
100
VZAP
ESD Susceptibility
4000
ILTH(4)
Latch-up
100
VCC = 2.5 V to 5.5 V, unless otherwise specified.
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Parameter
Test Conditions
ICC
Power Supply Current (Read)
fSCL = 400 kHz
ICC
Power Supply Current (Write)
fSCL = 400 kHz
ISB(5)
Standby Current (VCC = 5.0 V)
VIN = GND or VCC
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage (VCC = 3.0 V)
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Units
Years
Volts
Typ
mA
Max
Units
1
mA
3
mA
1
µA
VIN = GND to VCC
1
µA
VOUT = GND to VCC
1
µA
–1
VCC x 0.3
V
VCC x 0.7
VCC + 1.0
V
0.4
V
Max
Units
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Min
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Max
Cycles/Byte
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D.C. OPERATING CHARACTERISTICS
Symbol
Typ
IOL = 3 mA
CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol
Test
Conditions
Min
Typ
CI/O(3)
Input/Output Capacitance (SDA)
VI/O = 0 V
8
pF
CIN(3)
Input Capacitance (other pins)
VIN = 0 V
6
pF
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to VCC + 1.0 V.
(5) Maximum standby current (ISB) = 10µA for the Extended Automotive temperature range.
Doc. No. 1054, Rev. I
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CAT24FC16
A.C. CHARACTERISTICS
VCC = 2.5 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
2.5 V - 5.5 V
Min
Max
Units
kHz
FSCL
Clock Frequency
400
TI(1)
Noise Suppression Time Constant at SCL, SDA Inputs
100
SCL Low to SDA Data Out and ACK Out
900
tAA
tBUF
(1)
Time the Bus Must be Free Before a New Transmission
Can Start
1300
tHD:STA
Start Condition Hold Time
600
tLOW
Clock Low Period
1300
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
tSU:DAT
Data In Setup Time
tR(1)
SDA and SCL Rise Time
tF
(1)
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SDA and SCL Fall Time
tSU:STO
Stop Condition Setup Time
tDH
Data Out Hold Time
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Power-Up Timing(1)(2)
Symbol
Parameter
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600
600
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Min
0
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100
ns
ns
ns
ns
ns
ns
ns
ns
300
ns
300
ns
600
ns
100
ns
Typ
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Max
Units
5
ms
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Write Cycle Limits
Symbol
Parameter
tWR
Write Cycle Time
Min
Typ
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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Doc No. 1054, Rev. I
CAT24FC16
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT24FC16 supports the I2C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC16 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
SCL: Serial Clock
The CAT24FC16 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT24FC16 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
WP: Write Protect
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This input, when tied to GND, allows write operations to
the entire memory. For CAT24FC16 when this pin is tied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
Figure 1. Bus Timing
tF
tHIGH
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
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SDA IN
tAA
SDA OUT
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Figure 2. Write Cycle Timing
SCL
SDA
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8TH BIT
BYTE n
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tR
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tSU:DAT
tBUF
tDH
ACK
tWR
STOP
CONDITION
START
CONDITION
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1054, Rev. I
tSU:STO
STOP BIT
4
ADDRESS
CAT24FC16
I2C BUS PROTOCOL
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
The following defines the features of the I2C bus protocol:
After the Master sends a START condition and the slave
address byte, the CAT24FC16 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC16 then performs a Read or a Write operation
depending on the state of the R/W bit.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC16 monitor the
SDA and SCL lines and will not respond until this
condition is met.
DEVICE ADDRESSING
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The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC16 (see Fig. 5). The next three
significant bits (A10, A9, A8) are the memory array
address bits. The last bit of the slave address specifies
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Figure 4. Acknowledge Timing
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SCL FROM
MASTER
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The CAT24FC16 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
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STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
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Acknowledge
When the CAT24FC16 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this acknowledge, the CAT24FC16 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
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1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 5. Slave Address Bits
1
0
1
0
A10
A9
A8
R/W
Normal Read and Write
DEVICE ADDRESS
5
Doc No. 1054, Rev. I
CAT24FC16
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24FC16 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24FC16. After receiving another
acknowledge from the Slave, the Master device transmits
the data byte to be written into the addressed memory
location. The CAT24FC16 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24FC16 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC16 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC16 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
Page Write
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If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
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BUS ACTIVITY:
MASTER
D
SDA LINE
S
T
A
R
T
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WRITE PROTECTION
The CAT24FC16 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24FC16 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
Figure 6. Byte Write Timing
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The CAT24FC16 is designed with a hardware protect
pin that enables the user to protect the entire memory.
The hardware protection feature of the CAT24FC16 is
designed into the part to provide added flexibility to the
design engineers. The write protection feature of
CAT24FC16 allows the user to protect against inadvertent
programming of the memory array. If the WP pin is tied
to Vcc, the entire memory array is protected and becomes
read only. The entire memory becomes write protected
regardless of whether the write protect register has been
written or not. When WP pin is tied to Vcc, the user
cannot program the write protect register. If the WP pin
is left floating or tied to Vss, the device can be written
into.
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SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
S
P
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
S
DATA n
DATA n+1
DATA n+P
P
*
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1054, Rev. I
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A
C
K
A
C
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CAT24FC16
Sequential Read
Read Operations
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC16 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC16 will continue to output a byte for
each acknowledge sent by the Master. The operation
will terminate operation when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The READ operation for the CAT24FC16 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24FC16’s address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to address
N, the READ immediately following would access data
from address N + 1. If N = 2047 for 24FC16, then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT24FC16 receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
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Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24FC16 acknowledge the word
address, the Master device resends the START condition
and the slave address, this time with the R/W bit set to
one. The CAT24FC16 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
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The data being transmitted from the CAT24FC16 is
outputted sequentially with data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT24FC16
address bits so that the entire memory array can be read
during one operation. If more than the 2047 bytes are
read out, the counter will “wrap around” and continue to
clock out data bytes.
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Figure 8. Immediate Address Read Timing
SCL
SDA
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
8
9
8TH BIT
DATA OUT
NO ACK
7
STOP
Doc No. 1054, Rev. I
CAT24FC16
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
S
T
O
P
SLAVE
ADDRESS
S
A
C
K
P
A
C
K
A
C
K
DATA n
N
O
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A
C
K
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
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SDA LINE
A
C
K
A
C
K
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Doc. No. 1054, Rev. I
A
C
K
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8
A
C
K
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S
T
O
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DATA n+x
P
N
O
A
C
K
CAT24FC16
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
Suffix
24FC16
J
I
TE13
Temperature Range
I = Industri
E = Extended (-40°C to +125°C)
Product
Number
REV-F
Tape & Reel
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Die Revision
Package
P: PDIP
J: SOIC (JEDEC)
R: MSOP
U: TSSOP
RD4: TDFN
L: PDIP (Lead-free, Halogen-free)
W: SOIC (JEDEC), (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
Z: MSOP (Lead-free, Halogen-free)
ZD4: TDFN (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC (JEDEC) (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GD4: TDFN (Lead-free, Halogen-free, NiPdAu lead plating)
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Notes:
(1) The device used in the above example is a 24FC16JI-TE13 (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating Voltage, Tape & Reel)
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Doc No. 1054, Rev. I
CAT24FC16
REVISION HISTORY
Date
Revision Comments
11/18/03
A
Initial Issue
12/09/03
B
Changed Industrial Temp to “ I” from “ Blank” in ordering
information
03/10/04
C
Corrected TDFN ordering info
04/02/04
D
Eliminated data sheet designation
05/15/04
E
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Removed reference to a write protect register in “ Write Protection”
D.C. Operating Characteristics
Write Cycle Limits
Update Ordering Information
Update Revision History
Update Rev Number
06/07/04
F
Update Write Cycle Limits
7/27/04
G
Update notes on page 2
03/24/05
H
Updated
Updated
Updated
Updated
Updated
Updated
Updated
06/23/05
I
Update Ordering Information
Features
Description
Pin Function
Reliability Characteristics
Operating Characteristics
A.C. Characteristics
Ordering Information
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Doc. No. 1054, Rev. I
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Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
DPPs ™
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AE2 ™
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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
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Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #:
Revison:
Issue date:
1054
I
06/23/05