SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS099C – DECEMBER 1982 – REVISED APRIL 1999 SN54HC112 . . . J OR W PACKAGE SN74HC112 . . . D OR N PACKAGE (TOP VIEW) Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs 1CLK 1K 1J 1PRE 1Q 1Q 2Q GND description The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1CLR 2CLR 2CLK 2K 2J 2PRE 2Q 1K 1CLK NC VCC 1CLR SN54HC112 . . . FK PACKAGE (TOP VIEW) 1J 1PRE NC 1Q 1Q 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q GND NC 2Q The SN54HC112 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC112 is characterized for operation from –40°C to 85°C. 4 2CLR 2CLK NC 2K 2J 2PRE D NC – No internal connection FUNCTION TABLE INPUTS PRE CLR OUTPUTS CLK J K Q Q L H X X X H L H L X X X L L X X X L H† H H† H H ↓ L L Q0 Q0 H H ↓ H L H L H H ↓ L H L H H ↓ H H H Toggle H H H X X Q0 Q0 † This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS099C – DECEMBER 1982 – REVISED APRIL 1999 logic symbol† 4 1PRE S 3 1J 1 1CLK C1 2 1K 9 11 2J 1Q 1Q R 10 2PRE 6 1K 15 1CLR 5 1J 2Q 13 2CLK 7 12 2K 2Q 14 2CLR † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages. logic diagram, each flip-flop (positive logic) PRE C J C Q TG TG K C CLK C C C TG TG C C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS099C – DECEMBER 1982 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54HC112 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage tt‡ Input transition (rise and fall) time SN74HC112 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 V V 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC VCC = 2 V VCC = 4.5 V 0 1000 0 1000 0 500 0 500 VCC = 6 V 0 400 0 400 VCC = 4.5 V VCC = 6 V UNIT V V V ns TA Operating free-air temperature –55 125 –40 85 °C ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS099C – DECEMBER 1982 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 µA VOH IOL = 20 µA II ICC VI = VCC or 0 VI = VCC or 0, TA = 25°C TYP MAX MIN MAX SN74HC112 MIN 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 4 80 40 µA 3 10 10 10 pF IO = 0 6V Ci SN54HC112 1.9 VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA MIN 2V VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA VOL VCC 2 V to 6 V V timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency PRE or CLR low tw Pulse duration CLK high or low Data (J, K) tsu ↓ Setup time before CLK↓ PRE or CLR inactive th 4 Hold time, data after CLK↓ ↓ POST OFFICE BOX 655303 TA = 25°C MIN MAX SN54HC112 MIN MAX SN74HC112 MIN MAX 2V 5 3.4 4 4.5 V 25 17 20 6V 29 20 24 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS099C – DECEMBER 1982 – REVISED APRIL 1999 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd d CLK tt Q or Q Q or Q VCC MIN TA = 25°C TYP MAX SN54HC112 MIN MAX SN74HC112 MIN 2V 5 10 3.4 4 4.5 V 25 50 17 20 6V 29 60 20 24 MAX UNIT MHz 2V 54 165 245 205 4.5 V 16 33 49 41 6V 13 28 42 35 2V 56 125 185 155 4.5 V 16 25 37 31 6V 13 21 31 26 2V 29 75 110 95 4.5 V 9 15 22 19 6V 8 13 19 16 ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 35 UNIT pF 5 SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS099C – DECEMBER 1982 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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