CENTRAL CP645

PROCESS
CP645
Central
Power Transistor
TM
Semiconductor Corp.
PNP, 8.0A Power Transistor Chip
PROCESS DETAILS
Process
MULTIEPITAXIAL MESA
Die Size
120 x 145 MILS
Die Thickness
13 MILS
Base Bonding Pad Area
20 x 45 MILS
Emitter Bonding Pad Area
14 x 70 MILS
Top Side Metalization
Al - 50,000Å
Back Side Metalization
Cr / Ni / Ag - 10,000Å
GEOMETRY
GROSS DIE PER 4 INCH WAFER
640
PRINCIPAL DEVICE TYPES
MJE15031
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R0 (4- April 2005)