TI SN74CBTLV3245APW

SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H – JULY 1997 – REVISED NOVEMBER 1999
D
D
D
D
D
D
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
Standard ’245-Type Pinout
5-Ω Switch Connection Between Two Ports
Isolation Under Power-Off Conditions
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Shrink
Small-Outline (DBQ), Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)
Packages
NC
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
NC – No internal connection
description
The SN74CBTLV3245A provides eight bits of high-speed bus switching in a standard ’245 device pinout. The
low on-state resistance of the switch allows connections to be made with minimal propagation delay.
The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on and A port
is connected to B port. When OE is high, the switch is open and the high-impedance state exists between the
two ports.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3245A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
logic diagram (positive logic)
2
A1
18
B1
SW
9
A8
11
SW
B8
19
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H – JULY 1997 – REVISED NOVEMBER 1999
simplified schematic, each FET switch
A
B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High level control input voltage
High-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low level control input voltage
Low-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
MIN
MAX
2.3
3.6
1.7
UNIT
V
V
2
0.7
0.8
V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H – JULY 1997 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
Control inputs
Data inputs
II
Ioff
ICC
∆ICC‡
Control inputs
Ci
Control inputs
Cio(OFF)
TEST CONDITIONS
TYP†
MAX
–1.2
VCC = 3 V
V,
II = –18
18 mA
VCC = 3.6 V,
VCC = 0,
VI = VCC or GND
VI or VO = 0 to 3.6 V
VCC = 3.6 V,
VCC = 3.6 V,
IO = 0,
One input at 3 V,
VI = 3 V or 0
VO = 3 V or 0,
MIN
–0.8
VI = VCC or GND
Other inputs at VCC or GND
VI = 0
VCC = 2.3
2 3 V,
V
TYP at VCC = 2.5
25V
VI = 1.7 V,
ron§
VI = 0
VCC = 3 V
V
±60
µA
40
µA
20
µA
300
µA
4
OE = VCC
UNIT
pF
9
pF
IO = 64 mA
IO = 24 mA
5
8
5
8
IO = 15 mA
IO = 64 mA
27
40
5
7
Ω
IO = 24 mA
5
7
VI = 2.4 V,
IO = 15 mA
10
15
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd¶
A or B
B or A
ten
OE
A or B
1
6
tdis
OE
A or B
1
6.1
PARAMETER
MIN
MAX
MIN
0.15
UNIT
MAX
0.25
ns
1
4.7
ns
1
6.4
ns
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
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3
SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H – JULY 1997 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
500 Ω
From Output
Under Test
S1
Open
GND
CL = 30 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
Output
Control
(low-level
enabling)
LOAD CIRCUIT
VCC
VCC/2
0V
tPZL
VCC
VCC/2
Input
VCC/2
0V
tPLH
VCC/2
tPLZ
VCC
VCC/2
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VOL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H – JULY 1997 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
VCC
Output
Control
LOAD CIRCUIT
VCC/2
0V
tPZL
VCC
VCC/2
Input
VCC/2
0V
tPLH
VCC/2
tPLZ
VCC
VCC/2
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VOL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
5
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Copyright  1999, Texas Instruments Incorporated